ar5416reg.h revision 221806
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188968Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 221806 2011-05-12 10:11:24Z adrian $ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416REG_H 20185377Ssam#define _DEV_ATH_AR5416REG_H 21185377Ssam 22188968Ssam#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23185377Ssam 24185377Ssam/* 25185377Ssam * Register added starting with the AR5416 26185377Ssam */ 27185377Ssam#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28185377Ssam#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29185377Ssam#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30185377Ssam#define AR_GTXTO 0x0064 /* global transmit timeout */ 31185377Ssam#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32185377Ssam#define AR_CST 0x006C /* carrier sense timeout */ 33185377Ssam#define AR_MAC_LED 0x1f04 /* LED control */ 34188979Ssam#define AR_WA 0x4004 /* PCIE work-arounds */ 35188979Ssam#define AR_PCIE_PM_CTRL 0x4014 36185377Ssam#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37185377Ssam#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38185377Ssam#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39185377Ssam#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40185377Ssam#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41185377Ssam#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42185377Ssam#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43185377Ssam#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44185377Ssam#define AR5416_PCIE_SERDES 0x4040 45185377Ssam#define AR5416_PCIE_SERDES2 0x4044 46188976Ssam#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 47188976Ssam#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 48188976Ssam#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 49188976Ssam#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 50188976Ssam#define AR_GPIO_INPUT_MUX1 0x4058 51188976Ssam#define AR_GPIO_INPUT_MUX2 0x405c 52188976Ssam#define AR_GPIO_OUTPUT_MUX1 0x4060 53188976Ssam#define AR_GPIO_OUTPUT_MUX2 0x4064 54188976Ssam#define AR_GPIO_OUTPUT_MUX3 0x4068 55185377Ssam#define AR_EEPROM_STATUS_DATA 0x407c 56185377Ssam#define AR_OBS 0x4080 57221163Sadrian 58221163Sadrian#ifdef AH_SUPPORT_AR9130 59221163Sadrian#define AR_RTC_BASE 0x20000 60221163Sadrian#else 61221163Sadrian#define AR_RTC_BASE 0x7000 62221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 63221163Sadrian 64221163Sadrian#define AR_RTC_RC AR_RTC_BASE + 0x00 /* reset control */ 65221163Sadrian#define AR_RTC_PLL_CONTROL AR_RTC_BASE + 0x14 66221163Sadrian#define AR_RTC_RESET AR_RTC_BASE + 0x40 /* RTC reset register */ 67221163Sadrian#define AR_RTC_STATUS AR_RTC_BASE + 0x44 /* system sleep status */ 68221163Sadrian#define AR_RTC_SLEEP_CLK AR_RTC_BASE + 0x48 69221163Sadrian#define AR_RTC_FORCE_WAKE AR_RTC_BASE + 0x4c /* control MAC force wake */ 70221163Sadrian#define AR_RTC_INTR_CAUSE AR_RTC_BASE + 0x50 /* RTC interrupt cause/clear */ 71221163Sadrian#define AR_RTC_INTR_ENABLE AR_RTC_BASE + 0x54 /* RTC interrupt enable */ 72221163Sadrian#define AR_RTC_INTR_MASK AR_RTC_BASE + 0x58 /* RTC interrupt mask */ 73221163Sadrian 74221163Sadrian#ifdef AH_SUPPORT_AR9130 75221163Sadrian/* RTC_DERIVED_* - only for AR9130 */ 76221163Sadrian#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 77221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 78221163Sadrian#define AR_RTC_DERIVED_CLK_PERIOD_S 1 79221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 80221163Sadrian 81185377Ssam#define AR_RESET_TSF 0x8020 82185377Ssam#define AR_RXFIFO_CFG 0x8114 83185377Ssam#define AR_PHY_ERR_1 0x812c 84185377Ssam#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 85185377Ssam#define AR_PHY_ERR_2 0x8134 86185377Ssam#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 87185377Ssam#define AR_TSFOOR_THRESHOLD 0x813c 88185377Ssam#define AR_PHY_ERR_3 0x8168 89185377Ssam#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 90185377Ssam#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 91185377Ssam#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 92185377Ssam#define AR_TXOP_4_7 0x81f4 93185377Ssam#define AR_TXOP_8_11 0x81f8 94185377Ssam#define AR_TXOP_12_15 0x81fc 95185377Ssam/* generic timers based on tsf - all uS */ 96185377Ssam#define AR_NEXT_TBTT 0x8200 97185377Ssam#define AR_NEXT_DBA 0x8204 98185377Ssam#define AR_NEXT_SWBA 0x8208 99185377Ssam#define AR_NEXT_CFP 0x8208 100185377Ssam#define AR_NEXT_HCF 0x820C 101185377Ssam#define AR_NEXT_TIM 0x8210 102185377Ssam#define AR_NEXT_DTIM 0x8214 103185377Ssam#define AR_NEXT_QUIET 0x8218 104185377Ssam#define AR_NEXT_NDP 0x821C 105185377Ssam#define AR5416_BEACON_PERIOD 0x8220 106185377Ssam#define AR_DBA_PERIOD 0x8224 107185377Ssam#define AR_SWBA_PERIOD 0x8228 108185377Ssam#define AR_HCF_PERIOD 0x822C 109185377Ssam#define AR_TIM_PERIOD 0x8230 110185377Ssam#define AR_DTIM_PERIOD 0x8234 111185377Ssam#define AR_QUIET_PERIOD 0x8238 112185377Ssam#define AR_NDP_PERIOD 0x823C 113185377Ssam#define AR_TIMER_MODE 0x8240 114185377Ssam#define AR_SLP32_MODE 0x8244 115185377Ssam#define AR_SLP32_WAKE 0x8248 116185377Ssam#define AR_SLP32_INC 0x824c 117185377Ssam#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 118185377Ssam#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 119185377Ssam#define AR_SLP_MIB_CTRL 0x8258 120185377Ssam#define AR_2040_MODE 0x8318 121185377Ssam#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 122185377Ssam#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 123185377Ssam#define AR_PCU_TXBUF_CTRL 0x8340 124208711Srpaulo#define AR_PCU_MISC_MODE2 0x8344 125185377Ssam 126185377Ssam/* DMA & PCI Registers in PCI space (usable during sleep)*/ 127185377Ssam#define AR_RC_AHB 0x00000001 /* AHB reset */ 128185377Ssam#define AR_RC_APB 0x00000002 /* APB reset */ 129185377Ssam#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 130185377Ssam 131185377Ssam#define AR_MIRT_VAL 0x0000ffff /* in uS */ 132185377Ssam#define AR_MIRT_VAL_S 16 133185377Ssam 134185377Ssam#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 135185377Ssam#define AR_TIMT_LAST_S 0 136185377Ssam#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 137185377Ssam#define AR_TIMT_FIRST_S 16 138185377Ssam 139185377Ssam#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 140185377Ssam#define AR_RIMT_LAST_S 0 141185377Ssam#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 142185377Ssam#define AR_RIMT_FIRST_S 16 143185377Ssam 144185377Ssam#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 145185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 146185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 147185377Ssam 148185377Ssam#define AR_GTTM_USEC 0x00000001 // usec strobe 149185377Ssam#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 150185377Ssam#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 151185377Ssam#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 152185377Ssam 153185377Ssam#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 154185377Ssam#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 155185377Ssam#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 156185377Ssam 157185377Ssam/* MAC tx DMA size config */ 158185377Ssam#define AR_TXCFG_DMASZ_MASK 0x00000003 159185377Ssam#define AR_TXCFG_DMASZ_4B 0 160185377Ssam#define AR_TXCFG_DMASZ_8B 1 161185377Ssam#define AR_TXCFG_DMASZ_16B 2 162185377Ssam#define AR_TXCFG_DMASZ_32B 3 163185377Ssam#define AR_TXCFG_DMASZ_64B 4 164185377Ssam#define AR_TXCFG_DMASZ_128B 5 165185377Ssam#define AR_TXCFG_DMASZ_256B 6 166185377Ssam#define AR_TXCFG_DMASZ_512B 7 167185377Ssam#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 168185377Ssam 169185377Ssam/* MAC rx DMA size config */ 170185377Ssam#define AR_RXCFG_DMASZ_MASK 0x00000007 171185377Ssam#define AR_RXCFG_DMASZ_4B 0 172185377Ssam#define AR_RXCFG_DMASZ_8B 1 173185377Ssam#define AR_RXCFG_DMASZ_16B 2 174185377Ssam#define AR_RXCFG_DMASZ_32B 3 175185377Ssam#define AR_RXCFG_DMASZ_64B 4 176185377Ssam#define AR_RXCFG_DMASZ_128B 5 177185377Ssam#define AR_RXCFG_DMASZ_256B 6 178185377Ssam#define AR_RXCFG_DMASZ_512B 7 179185377Ssam 180185377Ssam/* MAC Led registers */ 181221479Sadrian#define AR_CFG_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ 182221479Sadrian#define AR_CFG_SCLK_RATE_IND_S 0 183221479Sadrian#define AR_CFG_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ 184221479Sadrian#define AR_CFG_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ 185221479Sadrian#define AR_CFG_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ 186221479Sadrian#define AR_CFG_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ 187185377Ssam#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 188185377Ssam#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 189185377Ssam#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 190185377Ssam#define AR_MAC_LED_MODE_S 7 191185377Ssam#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 192185377Ssam#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 193185377Ssam#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 194185377Ssam#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 195185377Ssam#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 196185377Ssam#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 197185377Ssam#define AR_MAC_LED_ASSOC 0x00000c00 198185377Ssam#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 199185377Ssam#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 200185377Ssam#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 201185377Ssam#define AR_MAC_LED_ASSOC_S 10 202185377Ssam 203188979Ssam#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 204188979Ssam#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 205188979Ssam#define AR_WA_ANALOG_SHIFT 0x00100000 206188979Ssam#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 207188979Ssam 208188979Ssam#define AR_WA_DEFAULT 0x0000073f 209188979Ssam#define AR9280_WA_DEFAULT 0x0040073f 210188979Ssam#define AR9285_WA_DEFAULT 0x004a05cb 211188979Ssam 212188979Ssam#define AR_PCIE_PM_CTRL_ENA 0x00080000 213188979Ssam 214185377Ssam#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 215185377Ssam#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 216185377Ssam#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 217185377Ssam#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 218185377Ssam#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 219185377Ssam#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 220185377Ssam#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 221185377Ssam#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 222185377Ssam 223185377Ssam/* MAC PCU Registers */ 224185377Ssam#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 225185377Ssam 226185377Ssam/* Extended PCU DIAG_SW control fields */ 227185377Ssam#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 228185377Ssam#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 229185377Ssam#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 230185377Ssam#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 231185377Ssam#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 232185377Ssam#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 233185377Ssam 234185377Ssam#define AR_TXOP_X_VAL 0x000000FF 235185377Ssam 236185377Ssam#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 237185377Ssam 238185377Ssam/* Interrupts */ 239185377Ssam#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 240185377Ssam#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 241185377Ssam#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 242185377Ssam#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 243185377Ssam 244185377Ssam#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 245185377Ssam#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 246185377Ssam#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 247185377Ssam 248208711Srpaulo#define AR_ISR_S5 0x0098 249208711Srpaulo#define AR_ISR_S5_S 0x00d8 250208711Srpaulo#define AR_ISR_S5_TIM_TIMER 0x00000010 251208711Srpaulo 252185377Ssam#define AR_INTR_SPURIOUS 0xffffffff 253185377Ssam#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 254185377Ssam#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 255185377Ssam#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 256185377Ssam#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 257185377Ssam#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 258185377Ssam 259185377Ssam/* Interrupt Mask Registers */ 260185377Ssam#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 261185377Ssam#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 262185377Ssam#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 263185377Ssam#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 264185377Ssam 265185377Ssam#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 266185377Ssam#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 267185377Ssam 268185377Ssam/* synchronous interrupt signals */ 269185377Ssam#define AR_INTR_SYNC_RTC_IRQ 0x00000001 270185377Ssam#define AR_INTR_SYNC_MAC_IRQ 0x00000002 271185377Ssam#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 272185377Ssam#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 273185377Ssam#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 274185377Ssam#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 275185377Ssam#define AR_INTR_SYNC_HOST1_PERR 0x00000040 276185377Ssam#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 277185377Ssam#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 278185377Ssam#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 279185377Ssam#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 280185377Ssam#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 281185377Ssam#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 282185377Ssam#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 283185377Ssam#define AR_INTR_SYNC_PM_ACCESS 0x00004000 284185377Ssam#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 285185377Ssam#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 286185377Ssam#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 287185377Ssam#define AR_INTR_SYNC_ALL 0x0003FFFF 288185377Ssam 289185377Ssam/* default synchronous interrupt signals enabled */ 290185377Ssam#define AR_INTR_SYNC_DEFAULT \ 291185377Ssam (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 292185377Ssam AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 293185377Ssam AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 294185377Ssam AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 295185377Ssam AR_INTR_SYNC_MAC_SLEEP_ACCESS) 296185377Ssam 297188976Ssam#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 298188976Ssam#define AR_INTR_SYNC_MASK_GPIO_S 18 299188976Ssam 300188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 301188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO_S 18 302188976Ssam 303188976Ssam#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 304188976Ssam#define AR_INTR_ASYNC_MASK_GPIO_S 18 305188976Ssam 306188976Ssam#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 307188976Ssam#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 308188976Ssam 309188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 310188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 311188976Ssam 312185377Ssam/* RTC registers */ 313185377Ssam#define AR_RTC_RC_M 0x00000003 314185377Ssam#define AR_RTC_RC_MAC_WARM 0x00000001 315185377Ssam#define AR_RTC_RC_MAC_COLD 0x00000002 316221163Sadrian#ifdef AH_SUPPORT_AR9130 317221163Sadrian#define AR_RTC_RC_COLD_RESET 0x00000004 318221163Sadrian#define AR_RTC_RC_WARM_RESET 0x00000008 319221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 320185377Ssam#define AR_RTC_PLL_DIV 0x0000001f 321185377Ssam#define AR_RTC_PLL_DIV_S 0 322185377Ssam#define AR_RTC_PLL_DIV2 0x00000020 323185377Ssam#define AR_RTC_PLL_REFDIV_5 0x000000c0 324185377Ssam 325185377Ssam#define AR_RTC_SOWL_PLL_DIV 0x000003ff 326185377Ssam#define AR_RTC_SOWL_PLL_DIV_S 0 327185377Ssam#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 328185377Ssam#define AR_RTC_SOWL_PLL_REFDIV_S 10 329185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 330185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL_S 14 331185377Ssam 332185377Ssam#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 333185377Ssam 334185377Ssam#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 335221163Sadrian#ifdef AH_SUPPORT_AR9130 336221163Sadrian#define AR_RTC_STATUS_M 0x0000000f /* RTC Status */ 337221163Sadrian#else 338185377Ssam#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 339221163Sadrian#endif /* AH_SUPPORT_AR9130 */ 340185377Ssam#define AR_RTC_STATUS_SHUTDOWN 0x00000001 341185377Ssam#define AR_RTC_STATUS_ON 0x00000002 342185377Ssam#define AR_RTC_STATUS_SLEEP 0x00000004 343185377Ssam#define AR_RTC_STATUS_WAKEUP 0x00000008 344185377Ssam#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 345185377Ssam#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 346185377Ssam 347185377Ssam#define AR_RTC_SLEEP_DERIVED_CLK 0x2 348185377Ssam 349185377Ssam#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 350185377Ssam#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 351185377Ssam 352185377Ssam#define AR_RTC_PLL_CLKSEL 0x00000300 353185377Ssam#define AR_RTC_PLL_CLKSEL_S 8 354185377Ssam 355185377Ssam/* AR9280: rf long shift registers */ 356221806Sadrian#define AR_AN_RF2G1_CH0 0x7810 357221806Sadrian#define AR_AN_RF5G1_CH0 0x7818 358221806Sadrian#define AR_AN_RF2G1_CH1 0x7834 359221806Sadrian#define AR_AN_RF5G1_CH1 0x783C 360221806Sadrian#define AR_AN_TOP2 0x7894 361221806Sadrian#define AR_AN_SYNTH9 0x7868 362221806Sadrian 363185377Ssam#define AR_AN_RF2G1_CH0_OB 0x03800000 364185377Ssam#define AR_AN_RF2G1_CH0_OB_S 23 365185377Ssam#define AR_AN_RF2G1_CH0_DB 0x1C000000 366185377Ssam#define AR_AN_RF2G1_CH0_DB_S 26 367185377Ssam 368185377Ssam#define AR_AN_RF5G1_CH0_OB5 0x00070000 369185377Ssam#define AR_AN_RF5G1_CH0_OB5_S 16 370185377Ssam#define AR_AN_RF5G1_CH0_DB5 0x00380000 371185377Ssam#define AR_AN_RF5G1_CH0_DB5_S 19 372185377Ssam 373185377Ssam#define AR_AN_RF2G1_CH1_OB 0x03800000 374185377Ssam#define AR_AN_RF2G1_CH1_OB_S 23 375185377Ssam#define AR_AN_RF2G1_CH1_DB 0x1C000000 376185377Ssam#define AR_AN_RF2G1_CH1_DB_S 26 377185377Ssam 378185377Ssam#define AR_AN_RF5G1_CH1_OB5 0x00070000 379185377Ssam#define AR_AN_RF5G1_CH1_OB5_S 16 380185377Ssam#define AR_AN_RF5G1_CH1_DB5 0x00380000 381185377Ssam#define AR_AN_RF5G1_CH1_DB5_S 19 382185377Ssam 383218420Sadrian#define AR_AN_TOP1 0x7890 384218420Sadrian#define AR_AN_TOP1_DACIPMODE 0x00040000 385218420Sadrian#define AR_AN_TOP1_DACIPMODE_S 18 386218420Sadrian 387185377Ssam#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 388185377Ssam#define AR_AN_TOP2_XPABIAS_LVL_S 30 389185377Ssam#define AR_AN_TOP2_LOCALBIAS 0x00200000 390185377Ssam#define AR_AN_TOP2_LOCALBIAS_S 21 391185377Ssam#define AR_AN_TOP2_PWDCLKIND 0x00400000 392185377Ssam#define AR_AN_TOP2_PWDCLKIND_S 22 393185377Ssam 394185377Ssam#define AR_AN_SYNTH9_REFDIVA 0xf8000000 395185377Ssam#define AR_AN_SYNTH9_REFDIVA_S 27 396185377Ssam 397203159Srpaulo#define AR9271_AN_RF2G6_OFFS 0x07f00000 398203159Srpaulo#define AR9271_AN_RF2G6_OFFS_S 20 399203159Srpaulo 400185377Ssam/* Sleep control */ 401185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 402185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 403185377Ssam 404185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 405185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 406185377Ssam 407185377Ssam/* Sleep Registers */ 408185377Ssam#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 409185377Ssam#define AR_SLP32_ENA 0x00100000 410185377Ssam#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 411185377Ssam 412185377Ssam#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 413185377Ssam 414185377Ssam#define AR_SLP32_TST_INC 0x000FFFFF 415185377Ssam 416185377Ssam#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 417185377Ssam#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 418185377Ssam 419185377Ssam#define AR_TIMER_MODE_TBTT 0x00000001 420185377Ssam#define AR_TIMER_MODE_DBA 0x00000002 421185377Ssam#define AR_TIMER_MODE_SWBA 0x00000004 422185377Ssam#define AR_TIMER_MODE_HCF 0x00000008 423185377Ssam#define AR_TIMER_MODE_TIM 0x00000010 424185377Ssam#define AR_TIMER_MODE_DTIM 0x00000020 425185377Ssam#define AR_TIMER_MODE_QUIET 0x00000040 426185377Ssam#define AR_TIMER_MODE_NDP 0x00000080 427185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 428185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 429185377Ssam#define AR_TIMER_MODE_THRESH 0xFFFFF000 430185377Ssam#define AR_TIMER_MODE_THRESH_S 12 431185377Ssam 432185377Ssam/* PCU Misc modes */ 433185377Ssam#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 434185377Ssam#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 435185377Ssam#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 436185377Ssam#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 437185377Ssam#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 438185377Ssam#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 439185377Ssam#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 440185377Ssam#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 441185377Ssam#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 442185377Ssam#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 443185377Ssam#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 444185377Ssam#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 445185377Ssam 446219978Sadrian#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 447219978Sadrian#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 448221617Sadrian/* 449221617Sadrian * This bit enables the Multicast search based on both MAC Address and Key ID. 450221617Sadrian * If bit is 0, then Multicast search is based on MAC address only. 451221617Sadrian * For Merlin and above only. 452221617Sadrian */ 453221617Sadrian#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 454208711Srpaulo#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 455219217Sadrian#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 456208711Srpaulo 457185377Ssam/* GPIO Interrupt */ 458185377Ssam#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 459185377Ssam#define AR_INTR_GPIO_S 20 460185377Ssam 461185377Ssam#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 462185377Ssam#define AR_GPIO_OUT_VAL 0x000FFC00 463185377Ssam#define AR_GPIO_OUT_VAL_S 10 464185377Ssam#define AR_GPIO_INTR_CTRL 0x3FF00000 465185377Ssam#define AR_GPIO_INTR_CTRL_S 20 466185377Ssam 467188976Ssam#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 468188976Ssam#define AR_GPIO_IN_VAL_S 14 469188976Ssam#define AR928X_GPIO_IN_VAL 0x000FFC00 470188976Ssam#define AR928X_GPIO_IN_VAL_S 10 471188976Ssam#define AR9285_GPIO_IN_VAL 0x00FFF000 472188976Ssam#define AR9285_GPIO_IN_VAL_S 12 473188976Ssam 474188976Ssam#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 475188976Ssam#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 476188976Ssam#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 477188976Ssam#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 478188976Ssam#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 479188976Ssam 480188976Ssam#define AR_GPIO_INTR_POL_VAL 0x1FFF 481188976Ssam#define AR_GPIO_INTR_POL_VAL_S 0 482188976Ssam 483208711Srpaulo#define AR_GPIO_JTAG_DISABLE 0x00020000 484208711Srpaulo 485185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 486185377Ssam 487185377Ssam#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 488185377Ssam#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 489203159Srpaulo#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 490185377Ssam 491185377Ssam/* Eeprom defines */ 492185377Ssam#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 493185377Ssam#define AR_EEPROM_STATUS_DATA_VAL_S 0 494185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 495185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 496185377Ssam#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 497185377Ssam#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 498185377Ssam 499221573Sadrian/* 500221573Sadrian * AR5212 defines the MAC revision mask as 0xF, but both ath9k and 501221573Sadrian * the Atheros HAL define it as 0x7. 502221573Sadrian * 503221573Sadrian * What this means however is AR5416 silicon revisions have 504221573Sadrian * changed. The below macros are for what is contained in the 505221573Sadrian * lower four bits; if the lower three bits are taken into account 506221573Sadrian * the revisions become 1.0 => 0x0, 2.0 => 0x1, 2.2 => 0x2. 507221573Sadrian */ 508221573Sadrian 509221573Sadrian/* These are the legacy revisions, with a four bit AR_SREV_REVISION mask */ 510185377Ssam#define AR_SREV_REVISION_OWL_10 0x08 511185377Ssam#define AR_SREV_REVISION_OWL_20 0x09 512185377Ssam#define AR_SREV_REVISION_OWL_22 0x0a 513185377Ssam 514185377Ssam#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 515185377Ssam#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 516185377Ssam#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 517185377Ssam#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 518185377Ssam 519185377Ssam/* Test macro for owl 1.0 */ 520221608Sadrian#define IS_5416V1(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_10) 521221608Sadrian#define IS_5416V2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) 522221608Sadrian#define IS_5416V2_2(_ah) (AR_SREV_OWL((_ah)) && AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_OWL_22) 523185377Ssam 524221573Sadrian/* Misc; compatibility with Atheros HAL */ 525221573Sadrian#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) 526221573Sadrian#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) 527221573Sadrian 528185377Ssam/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 529185377Ssam#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 530185377Ssam#define AR_XSREV_ID_S 0 531185377Ssam#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 532185377Ssam#define AR_XSREV_VERSION_S 18 533185377Ssam#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 534185377Ssam#define AR_XSREV_TYPE_S 12 535185377Ssam#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 536185377Ssam * 0:2 chains) */ 537185377Ssam#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 538185377Ssam#define AR_XSREV_REVISION 0x00000F00 539185377Ssam#define AR_XSREV_REVISION_S 8 540185377Ssam 541185377Ssam#define AR_XSREV_VERSION_OWL_PCI 0x0D 542185377Ssam#define AR_XSREV_VERSION_OWL_PCIE 0x0C 543221573Sadrian 544221573Sadrian 545221573Sadrian/* 546221573Sadrian * These are from ath9k/Atheros and assume an AR_SREV version mask 547221573Sadrian * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. 548221573Sadrian * Thus, don't use these values as they're incorrect here; use 549221573Sadrian * AR_SREV_REVISION_OWL_{10,20,22}. 550221573Sadrian */ 551221573Sadrian#if 0 552185377Ssam#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 553185377Ssam#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 554185377Ssam#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 555221573Sadrian#endif 556221573Sadrian 557219217Sadrian#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 558221163Sadrian#define AR_XSREV_VERSION_SOWL 0x40 /* Sowl (AR9160) */ 559185377Ssam#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 560185377Ssam#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 561185377Ssam#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 562185377Ssam#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 563185377Ssam#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 564185377Ssam#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 565185377Ssam#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 566185377Ssam#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 567203159Srpaulo#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 568203159Srpaulo#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 569185377Ssam 570221480Sadrian/* Owl (AR5416) */ 571217881Sadrian#define AR_SREV_OWL(_ah) \ 572217881Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 573217881Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 574217881Sadrian 575185377Ssam#define AR_SREV_OWL_20_OR_LATER(_ah) \ 576221480Sadrian ((AR_SREV_OWL(_ah) && \ 577221573Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20) || \ 578221480Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 579221480Sadrian 580185377Ssam#define AR_SREV_OWL_22_OR_LATER(_ah) \ 581221480Sadrian ((AR_SREV_OWL(_ah) && \ 582221573Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22) || \ 583221480Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 584185377Ssam 585221480Sadrian/* Howl (AR9130) */ 586221480Sadrian 587221163Sadrian#define AR_SREV_HOWL(_ah) \ 588221163Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_HOWL) 589221480Sadrian 590221163Sadrian#define AR_SREV_9100(_ah) AR_SREV_HOWL(_ah) 591221163Sadrian 592221480Sadrian/* Sowl (AR9160) */ 593221480Sadrian 594185377Ssam#define AR_SREV_SOWL(_ah) \ 595185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 596221480Sadrian 597185377Ssam#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 598185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 599221480Sadrian 600185377Ssam#define AR_SREV_SOWL_11(_ah) \ 601185377Ssam (AR_SREV_SOWL(_ah) && \ 602185377Ssam AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 603185377Ssam 604221480Sadrian/* Merlin (AR9280) */ 605221480Sadrian 606185377Ssam#define AR_SREV_MERLIN(_ah) \ 607185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 608221480Sadrian 609185377Ssam#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 610185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 611221480Sadrian 612185377Ssam#define AR_SREV_MERLIN_20(_ah) \ 613185377Ssam (AR_SREV_MERLIN(_ah) && \ 614221666Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 615221480Sadrian 616185377Ssam#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 617221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) || \ 618221480Sadrian (AR_SREV_MERLIN((_ah)) && \ 619221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)) 620185377Ssam 621221480Sadrian/* Kite (AR9285) */ 622221480Sadrian 623185377Ssam#define AR_SREV_KITE(_ah) \ 624185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 625221480Sadrian 626185377Ssam#define AR_SREV_KITE_10_OR_LATER(_ah) \ 627185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 628221480Sadrian 629203159Srpaulo#define AR_SREV_KITE_11(_ah) \ 630203159Srpaulo (AR_SREV_KITE(ah) && \ 631203159Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 632221480Sadrian 633203159Srpaulo#define AR_SREV_KITE_11_OR_LATER(_ah) \ 634221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 635221480Sadrian (AR_SREV_KITE((_ah)) && \ 636221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)) 637221480Sadrian 638203159Srpaulo#define AR_SREV_KITE_12(_ah) \ 639203159Srpaulo (AR_SREV_KITE(ah) && \ 640203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 641221480Sadrian 642203159Srpaulo#define AR_SREV_KITE_12_OR_LATER(_ah) \ 643221480Sadrian ((AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_KITE) || \ 644221480Sadrian (AR_SREV_KITE((_ah)) && \ 645221480Sadrian AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)) 646221480Sadrian 647218061Sadrian#define AR_SREV_9285E_20(_ah) \ 648218061Sadrian (AR_SREV_KITE_12_OR_LATER(_ah) && \ 649218061Sadrian ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 650218061Sadrian 651219217Sadrian/* Not yet implemented chips */ 652219217Sadrian#define AR_SREV_9271(_ah) 0 653219217Sadrian#define AR_SREV_9287_11_OR_LATER(_ah) 0 654221666Sadrian#define AR_SREV_KIWI_10_OR_LATER(_ah) 0 655219217Sadrian 656185377Ssam#endif /* _DEV_ATH_AR5416REG_H */ 657