ar5416phy.h revision 185377
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185377Ssam * $Id: ar5416phy.h,v 1.8 2008/11/06 22:08:01 sam Exp $ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416PHY_H_ 20185377Ssam#define _DEV_ATH_AR5416PHY_H_ 21185377Ssam 22185377Ssam#include "ar5212/ar5212phy.h" 23185377Ssam 24185377Ssam#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 25185377Ssam#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 26185377Ssam 27185377Ssam#define RFSILENT_BB 0x00002000 /* shush bb */ 28185377Ssam#define AR_PHY_RESTART 0x9970 /* restart */ 29185377Ssam#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 30185377Ssam#define AR_PHY_RESTART_DIV_GC_S 18 31185377Ssam 32185377Ssam/* PLL settling times */ 33185377Ssam#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 34185377Ssam#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */ 35185377Ssam 36185377Ssam#define AR_PHY_RFBUS_REQ 0x997C 37185377Ssam#define AR_PHY_RFBUS_REQ_EN 0x00000001 38185377Ssam 39185377Ssam#define AR_2040_MODE 0x8318 40185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 41185377Ssam 42185377Ssam#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 43185377Ssam#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ 44185377Ssam#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 45185377Ssam#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 46185377Ssam#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 47185377Ssam#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ 48185377Ssam#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 49185377Ssam#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 50185377Ssam#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 51185377Ssam 52185377Ssam#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ 53185377Ssam#define AR_PHY_TIMING2_USE_FORCE 0x00001000 54185377Ssam#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff 55185377Ssam 56185377Ssam#define AR_PHY_TIMING_CTRL4_CHAIN(_i) \ 57185377Ssam (AR_PHY_TIMING_CTRL4 + ((_i) << 12)) 58185377Ssam#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */ 59185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ 60185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 61185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ 62185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 63185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ 64185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 65185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 66185377Ssam 67185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 68185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */ 69185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 70185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 71185377Ssam 72185377Ssam#define AR_PHY_ADC_SERIAL_CTL 0x9830 73185377Ssam#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 74185377Ssam#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 75185377Ssam 76185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 77185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 78185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 79185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 80185377Ssam 81185377Ssam#define AR_PHY_EXT_CCA 0x99bc 82185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 83185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 84185377Ssam#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 85185377Ssam#define AR_PHY_EXT_MINCCA_PWR_S 23 86185377Ssam#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 87185377Ssam#define AR_PHY_EXT_CCA_THRESH62_S 16 88185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 89185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR_S 16 90185377Ssam 91185377Ssam#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */ 92185377Ssam#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 93185377Ssam#define AR_PHY_HALFGI_DSC_MAN_S 4 94185377Ssam#define AR_PHY_HALFGI_DSC_EXP 0x0000000F 95185377Ssam#define AR_PHY_HALFGI_DSC_EXP_S 0 96185377Ssam 97185377Ssam#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 98185377Ssam 99185377Ssam#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 100185377Ssam#define AR_PHY_REFCLKDLY 0x99f4 101185377Ssam#define AR_PHY_REFCLKPD 0x99f8 102185377Ssam 103185377Ssam#define AR_PHY_CALMODE 0x99f0 104185377Ssam/* Calibration Types */ 105185377Ssam#define AR_PHY_CALMODE_IQ 0x00000000 106185377Ssam#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 107185377Ssam#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 108185377Ssam#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 109185377Ssam/* Calibration results */ 110185377Ssam#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 111185377Ssam#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 112185377Ssam#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 113185377Ssam#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 114185377Ssam 115185377Ssam 116185377Ssam#define AR_PHY_CCA 0x9864 117185377Ssam#define AR_PHY_MINCCA_PWR 0x0FF80000 118185377Ssam#define AR_PHY_MINCCA_PWR_S 19 119185377Ssam#define AR9280_PHY_MINCCA_PWR 0x1FF00000 120185377Ssam#define AR9280_PHY_MINCCA_PWR_S 20 121185377Ssam#define AR9280_PHY_CCA_THRESH62 0x000FF000 122185377Ssam#define AR9280_PHY_CCA_THRESH62_S 12 123185377Ssam 124185377Ssam#define AR_PHY_CH1_CCA 0xa864 125185377Ssam#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 126185377Ssam#define AR_PHY_CH1_MINCCA_PWR_S 19 127185377Ssam#define AR_PHY_CCA_THRESH62 0x0007F000 128185377Ssam#define AR_PHY_CCA_THRESH62_S 12 129185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 130185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR_S 20 131185377Ssam 132185377Ssam#define AR_PHY_CH2_CCA 0xb864 133185377Ssam#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 134185377Ssam#define AR_PHY_CH2_MINCCA_PWR_S 19 135185377Ssam 136185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 137185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 138185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 139185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 140185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 141185377Ssam 142185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 143185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 144185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 145185377Ssam 146185377Ssam#define AR_PHY_RX_CHAINMASK 0x99a4 147185377Ssam 148185377Ssam#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 149185377Ssam#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 150185377Ssam#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 151185377Ssam#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 152185377Ssam 153185377Ssam#define AR_PHY_EXT_CCA0 0x99b8 154185377Ssam#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 155185377Ssam#define AR_PHY_EXT_CCA0_THRESH62_S 0 156185377Ssam 157185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 158185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 159185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 160185377Ssam 161185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 162185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 163185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 164185377Ssam#define AR_PHY_ANALOG_SWAP 0xa268 165185377Ssam#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 166185377Ssam#define AR_PHY_CAL_CHAINMASK 0xa39c 167185377Ssam 168185377Ssam#define AR_PHY_SWITCH_CHAIN_0 0x9960 169185377Ssam#define AR_PHY_SWITCH_COM 0x9964 170185377Ssam 171185377Ssam#define AR_PHY_RF_CTL2 0x9824 172185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF 173185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START_S 0 174185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00 175185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON_S 8 176185377Ssam 177185377Ssam#define AR_PHY_RF_CTL3 0x9828 178185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 179185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 180185377Ssam 181185377Ssam#define AR_PHY_RF_CTL4 0x9834 182185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 183185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 184185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 185185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 186185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 187185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 188185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 189185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 190185377Ssam 191185377Ssam#define AR_PHY_SYNTH_CONTROL 0x9874 192185377Ssam 193185377Ssam#define AR_PHY_FORCE_CLKEN_CCK 0xA22C 194185377Ssam#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 195185377Ssam 196185377Ssam#define AR_PHY_POWER_TX_SUB 0xA3C8 197185377Ssam#define AR_PHY_POWER_TX_RATE5 0xA38C 198185377Ssam#define AR_PHY_POWER_TX_RATE6 0xA390 199185377Ssam#define AR_PHY_POWER_TX_RATE7 0xA3CC 200185377Ssam#define AR_PHY_POWER_TX_RATE8 0xA3D0 201185377Ssam#define AR_PHY_POWER_TX_RATE9 0xA3D4 202185377Ssam 203185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 204185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 205185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 206185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 207185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 208185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 209185377Ssam 210185377Ssam#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 211185377Ssam#define AR_PHY_MASK2_M_31_45 0xa3a4 212185377Ssam#define AR_PHY_MASK2_M_16_30 0xa3a8 213185377Ssam#define AR_PHY_MASK2_M_00_15 0xa3ac 214185377Ssam#define AR_PHY_MASK2_P_15_01 0xa3b8 215185377Ssam#define AR_PHY_MASK2_P_30_16 0xa3bc 216185377Ssam#define AR_PHY_MASK2_P_45_31 0xa3c0 217185377Ssam#define AR_PHY_MASK2_P_61_45 0xa3c4 218185377Ssam 219185377Ssam#define AR_PHY_SPUR_REG 0x994c 220185377Ssam#define AR_PHY_SFCORR_EXT 0x99c0 221185377Ssam#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 222185377Ssam 223185377Ssam/* enable vit puncture per rate, 8 bits, lsb is low rate */ 224185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 225185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 226185377Ssam 227185377Ssam#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 228185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 229185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 230185377Ssam#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 231185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 232185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 233185377Ssam 234185377Ssam#define AR_PHY_PILOT_MASK_01_30 0xa3b0 235185377Ssam#define AR_PHY_PILOT_MASK_31_60 0xa3b4 236185377Ssam 237185377Ssam#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 238185377Ssam#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 239185377Ssam 240185377Ssam#endif /* _DEV_ATH_AR5416PHY_H_ */ 241