1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203159Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416PHY_H_ 20185377Ssam#define _DEV_ATH_AR5416PHY_H_ 21185377Ssam 22185377Ssam#include "ar5212/ar5212phy.h" 23185377Ssam 24234692Sadrian#define AR_BT_COEX_MODE 0x8170 25234692Sadrian#define AR_BT_TIME_EXTEND 0x000000ff 26234692Sadrian#define AR_BT_TIME_EXTEND_S 0 27234692Sadrian#define AR_BT_TXSTATE_EXTEND 0x00000100 28234692Sadrian#define AR_BT_TXSTATE_EXTEND_S 8 29234692Sadrian#define AR_BT_TX_FRAME_EXTEND 0x00000200 30234692Sadrian#define AR_BT_TX_FRAME_EXTEND_S 9 31234692Sadrian#define AR_BT_MODE 0x00000c00 32234692Sadrian#define AR_BT_MODE_S 10 33234692Sadrian#define AR_BT_QUIET 0x00001000 34234692Sadrian#define AR_BT_QUIET_S 12 35234692Sadrian#define AR_BT_QCU_THRESH 0x0001e000 36234692Sadrian#define AR_BT_QCU_THRESH_S 13 37234692Sadrian#define AR_BT_RX_CLEAR_POLARITY 0x00020000 38234692Sadrian#define AR_BT_RX_CLEAR_POLARITY_S 17 39234692Sadrian#define AR_BT_PRIORITY_TIME 0x00fc0000 40234692Sadrian#define AR_BT_PRIORITY_TIME_S 18 41234692Sadrian#define AR_BT_FIRST_SLOT_TIME 0xff000000 42234692Sadrian#define AR_BT_FIRST_SLOT_TIME_S 24 43234692Sadrian 44234692Sadrian#define AR_BT_COEX_WEIGHT 0x8174 45234692Sadrian#define AR_BT_BT_WGHT 0x0000ffff 46234692Sadrian#define AR_BT_BT_WGHT_S 0 47234692Sadrian#define AR_BT_WL_WGHT 0xffff0000 48234692Sadrian#define AR_BT_WL_WGHT_S 16 49234692Sadrian 50234692Sadrian#define AR_BT_COEX_MODE2 0x817c 51234692Sadrian#define AR_BT_BCN_MISS_THRESH 0x000000ff 52234692Sadrian#define AR_BT_BCN_MISS_THRESH_S 0 53234692Sadrian#define AR_BT_BCN_MISS_CNT 0x0000ff00 54234692Sadrian#define AR_BT_BCN_MISS_CNT_S 8 55234692Sadrian#define AR_BT_HOLD_RX_CLEAR 0x00010000 56234692Sadrian#define AR_BT_HOLD_RX_CLEAR_S 16 57234692Sadrian#define AR_BT_DISABLE_BT_ANT 0x00100000 58234692Sadrian#define AR_BT_DISABLE_BT_ANT_S 20 59234692Sadrian 60244768Sadrian#define AR_PHY_SPECTRAL_SCAN 0x9910 61244768Sadrian#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 62244768Sadrian#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 63244768Sadrian#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 64244768Sadrian#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 65244768Sadrian#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 66244768Sadrian#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 67244768Sadrian#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 68244768Sadrian#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 69244943Sadrian 70244943Sadrian/* Scan count and Short repeat flags are different for Kiwi and Merlin */ 71244768Sadrian#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 72244768Sadrian#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 73244943Sadrian#define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI 0x0FFF0000 74244943Sadrian#define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI_S 16 75244943Sadrian 76244768Sadrian#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 77244768Sadrian#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 78244943Sadrian#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI 0x10000000 79244943Sadrian#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI_S 28 80244768Sadrian 81244943Sadrian/* 82244943Sadrian * Kiwi only, bit 30 is used to set the error type, if set it is 0x5 (HAL_PHYERR_RADAR) 83244943Sadrian * Else it is 38 (new error type) 84244943Sadrian */ 85244943Sadrian#define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI 0x40000000 /* Spectral Error select bit mask */ 86244943Sadrian#define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI_S 30 /* Spectral Error select bit 30 */ 87244943Sadrian 88244943Sadrian#define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_KIWI 0x20000000 /* Spectral Error select bit mask */ 89244943Sadrian#define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_SELECT_KIWI_S 29 /* Spectral Error select bit 30 */ 90244943Sadrian 91222584Sadrian/* For AR_PHY_RADAR0 */ 92222584Sadrian#define AR_PHY_RADAR_0_FFT_ENA 0x80000000 93222584Sadrian 94222584Sadrian#define AR_PHY_RADAR_EXT 0x9940 95222584Sadrian#define AR_PHY_RADAR_EXT_ENA 0x00004000 96222584Sadrian 97222584Sadrian#define AR_PHY_RADAR_1 0x9958 98244943Sadrian#define AR_PHY_RADAR_1_BIN_THRESH_SELECT 0x07000000 99244943Sadrian#define AR_PHY_RADAR_1_BIN_THRESH_SELECT_S 24 100222584Sadrian#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 101222584Sadrian#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 102222584Sadrian#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 103222584Sadrian#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 104222584Sadrian#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 105222584Sadrian#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 106222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 107222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 108222584Sadrian#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 109222584Sadrian#define AR_PHY_RADAR_1_MAXLEN 0x000000FF 110222584Sadrian#define AR_PHY_RADAR_1_MAXLEN_S 0 111222584Sadrian 112185377Ssam#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ 113185377Ssam#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ 114185377Ssam 115185377Ssam#define RFSILENT_BB 0x00002000 /* shush bb */ 116185377Ssam#define AR_PHY_RESTART 0x9970 /* restart */ 117185377Ssam#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ 118185377Ssam#define AR_PHY_RESTART_DIV_GC_S 18 119185377Ssam 120185377Ssam/* PLL settling times */ 121185377Ssam#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 122185377Ssam#define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */ 123185377Ssam 124185377Ssam#define AR_PHY_RFBUS_REQ 0x997C 125185377Ssam#define AR_PHY_RFBUS_REQ_EN 0x00000001 126185377Ssam 127185377Ssam#define AR_2040_MODE 0x8318 128185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca 129185377Ssam 130185377Ssam#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 131185377Ssam#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ 132185377Ssam#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 133185377Ssam#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 134185377Ssam#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 135185377Ssam#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ 136185377Ssam#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 137185377Ssam#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 138185377Ssam#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 139203682Srpaulo#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 140185377Ssam 141185377Ssam#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ 142185377Ssam#define AR_PHY_TIMING2_USE_FORCE 0x00001000 143185377Ssam#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff 144185377Ssam 145185377Ssam#define AR_PHY_TIMING_CTRL4_CHAIN(_i) \ 146185377Ssam (AR_PHY_TIMING_CTRL4 + ((_i) << 12)) 147185377Ssam#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */ 148185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ 149185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ 150185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ 151185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 152185377Ssam#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ 153185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ 154185377Ssam#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 155185377Ssam 156185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 157185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */ 158185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 159185377Ssam#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 160185377Ssam 161185377Ssam#define AR_PHY_ADC_SERIAL_CTL 0x9830 162185377Ssam#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 163185377Ssam#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 164185377Ssam 165185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 166185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 167185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 168185377Ssam#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 169185377Ssam 170203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 171203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 172203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 173203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 174203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 175203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 176203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 177203682Srpaulo#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 178203682Srpaulo 179203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 180203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 181203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 182203682Srpaulo#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 183203682Srpaulo 184221878Sadrian#define AR_PHY_SEARCH_START_DELAY 0x9918 /* search start delay */ 185221878Sadrian 186185377Ssam#define AR_PHY_EXT_CCA 0x99bc 187185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 188185377Ssam#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 189185377Ssam#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 190185377Ssam#define AR_PHY_EXT_MINCCA_PWR_S 23 191185377Ssam#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 192185377Ssam#define AR_PHY_EXT_CCA_THRESH62_S 16 193221600Sadrian 194185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 195185377Ssam#define AR9280_PHY_EXT_MINCCA_PWR_S 16 196185377Ssam 197185377Ssam#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */ 198185377Ssam#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 199185377Ssam#define AR_PHY_HALFGI_DSC_MAN_S 4 200185377Ssam#define AR_PHY_HALFGI_DSC_EXP 0x0000000F 201185377Ssam#define AR_PHY_HALFGI_DSC_EXP_S 0 202185377Ssam 203185377Ssam#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 204185377Ssam 205208711Srpaulo#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec 206208711Srpaulo#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 207208711Srpaulo 208185377Ssam#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ 209185377Ssam#define AR_PHY_REFCLKDLY 0x99f4 210185377Ssam#define AR_PHY_REFCLKPD 0x99f8 211185377Ssam 212185377Ssam#define AR_PHY_CALMODE 0x99f0 213185377Ssam/* Calibration Types */ 214185377Ssam#define AR_PHY_CALMODE_IQ 0x00000000 215185377Ssam#define AR_PHY_CALMODE_ADC_GAIN 0x00000001 216185377Ssam#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 217185377Ssam#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 218185377Ssam/* Calibration results */ 219185377Ssam#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 220185377Ssam#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 221185377Ssam#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 222225957Sadrian/* This is AR9130 and later */ 223185377Ssam#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 224185377Ssam 225225957Sadrian/* 226225957Sadrian * AR5416 still uses AR_PHY(263) for current RSSI; 227225957Sadrian * AR9130 and later uses AR_PHY(271). 228225957Sadrian */ 229225957Sadrian#define AR9130_PHY_CURRENT_RSSI 0x9c3c /* rssi of current frame rx'd */ 230185377Ssam 231185377Ssam#define AR_PHY_CCA 0x9864 232185377Ssam#define AR_PHY_MINCCA_PWR 0x0FF80000 233185377Ssam#define AR_PHY_MINCCA_PWR_S 19 234185377Ssam#define AR9280_PHY_MINCCA_PWR 0x1FF00000 235185377Ssam#define AR9280_PHY_MINCCA_PWR_S 20 236185377Ssam#define AR9280_PHY_CCA_THRESH62 0x000FF000 237185377Ssam#define AR9280_PHY_CCA_THRESH62_S 12 238185377Ssam 239185377Ssam#define AR_PHY_CH1_CCA 0xa864 240185377Ssam#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 241185377Ssam#define AR_PHY_CH1_MINCCA_PWR_S 19 242185377Ssam#define AR_PHY_CCA_THRESH62 0x0007F000 243185377Ssam#define AR_PHY_CCA_THRESH62_S 12 244185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 245185377Ssam#define AR9280_PHY_CH1_MINCCA_PWR_S 20 246185377Ssam 247185377Ssam#define AR_PHY_CH2_CCA 0xb864 248185377Ssam#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 249185377Ssam#define AR_PHY_CH2_MINCCA_PWR_S 19 250185377Ssam 251185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 252185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 253185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 254185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 255185377Ssam#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 256185377Ssam 257185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 258185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 259185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 260185377Ssam 261185377Ssam#define AR_PHY_RX_CHAINMASK 0x99a4 262185377Ssam 263185377Ssam#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 264185377Ssam#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 265185377Ssam#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 266185377Ssam#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 267185377Ssam 268185377Ssam#define AR_PHY_EXT_CCA0 0x99b8 269185377Ssam#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 270185377Ssam#define AR_PHY_EXT_CCA0_THRESH62_S 0 271185377Ssam 272185377Ssam#define AR_PHY_CH1_EXT_CCA 0xa9bc 273185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 274185377Ssam#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 275185377Ssam 276185377Ssam#define AR_PHY_CH2_EXT_CCA 0xb9bc 277185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 278185377Ssam#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 279185377Ssam#define AR_PHY_ANALOG_SWAP 0xa268 280185377Ssam#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 281185377Ssam#define AR_PHY_CAL_CHAINMASK 0xa39c 282185377Ssam 283185377Ssam#define AR_PHY_SWITCH_CHAIN_0 0x9960 284185377Ssam#define AR_PHY_SWITCH_COM 0x9964 285185377Ssam 286185377Ssam#define AR_PHY_RF_CTL2 0x9824 287185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF 288185377Ssam#define AR_PHY_TX_FRAME_TO_DATA_START_S 0 289185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00 290185377Ssam#define AR_PHY_TX_FRAME_TO_PA_ON_S 8 291185377Ssam 292185377Ssam#define AR_PHY_RF_CTL3 0x9828 293185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 294185377Ssam#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 295185377Ssam 296185377Ssam#define AR_PHY_RF_CTL4 0x9834 297185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 298185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 299185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 300185377Ssam#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 301185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 302185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 303185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 304185377Ssam#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 305185377Ssam 306185377Ssam#define AR_PHY_SYNTH_CONTROL 0x9874 307185377Ssam 308185377Ssam#define AR_PHY_FORCE_CLKEN_CCK 0xA22C 309185377Ssam#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 310185377Ssam 311185377Ssam#define AR_PHY_POWER_TX_SUB 0xA3C8 312185377Ssam#define AR_PHY_POWER_TX_RATE5 0xA38C 313185377Ssam#define AR_PHY_POWER_TX_RATE6 0xA390 314185377Ssam#define AR_PHY_POWER_TX_RATE7 0xA3CC 315185377Ssam#define AR_PHY_POWER_TX_RATE8 0xA3D0 316185377Ssam#define AR_PHY_POWER_TX_RATE9 0xA3D4 317185377Ssam 318185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 319185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 320185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 321185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 322185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 323185377Ssam#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 324185377Ssam 325203159Srpaulo#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 326203159Srpaulo#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 327203159Srpaulo 328185377Ssam#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 329185377Ssam#define AR_PHY_MASK2_M_31_45 0xa3a4 330185377Ssam#define AR_PHY_MASK2_M_16_30 0xa3a8 331185377Ssam#define AR_PHY_MASK2_M_00_15 0xa3ac 332185377Ssam#define AR_PHY_MASK2_P_15_01 0xa3b8 333185377Ssam#define AR_PHY_MASK2_P_30_16 0xa3bc 334185377Ssam#define AR_PHY_MASK2_P_45_31 0xa3c0 335185377Ssam#define AR_PHY_MASK2_P_61_45 0xa3c4 336185377Ssam 337185377Ssam#define AR_PHY_SPUR_REG 0x994c 338185377Ssam#define AR_PHY_SFCORR_EXT 0x99c0 339185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 340185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 341185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 342185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 343185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 344185380Ssam#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 345185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 346185380Ssam#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 347185377Ssam#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 348185377Ssam 349185377Ssam/* enable vit puncture per rate, 8 bits, lsb is low rate */ 350185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 351185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 352185377Ssam 353185377Ssam#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 354185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */ 355185377Ssam#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 356185377Ssam#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 357185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 358185377Ssam#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 359185377Ssam 360185377Ssam#define AR_PHY_PILOT_MASK_01_30 0xa3b0 361185377Ssam#define AR_PHY_PILOT_MASK_31_60 0xa3b4 362185377Ssam 363185377Ssam#define AR_PHY_CHANNEL_MASK_01_30 0x99d4 364185377Ssam#define AR_PHY_CHANNEL_MASK_31_60 0x99d8 365185377Ssam 366185380Ssam#define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */ 367185380Ssam#define AR_PHY_CL_CAL_ENABLE 0x00000002 368203159Srpaulo#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 369218068Sadrian 370218068Sadrian/* empirically determined "good" CCA value ranges from atheros */ 371218068Sadrian#define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90 372218068Sadrian#define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100 373218068Sadrian#define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100 374218068Sadrian#define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110 375218068Sadrian#define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80 376218068Sadrian#define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90 377218068Sadrian 378218420Sadrian/* ar9280 specific? */ 379218420Sadrian#define AR_PHY_XPA_CFG 0xA3D8 380218420Sadrian#define AR_PHY_FORCE_XPA_CFG 0x000000001 381218420Sadrian#define AR_PHY_FORCE_XPA_CFG_S 0 382218420Sadrian 383218420Sadrian#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 384218420Sadrian#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 385218420Sadrian 386218420Sadrian#define AR_PHY_TX_PWRCTRL9 0xa27C 387218420Sadrian#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 388218420Sadrian#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 389218420Sadrian#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 390218420Sadrian#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 391218420Sadrian 392222301Sadrian#define AR_PHY_MODE_ASYNCFIFO 0x80 /* Enable async fifo */ 393222301Sadrian 394185377Ssam#endif /* _DEV_ATH_AR5416PHY_H_ */ 395