ar5416_recv.c revision 234747
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_recv.c 234747 2012-04-28 03:07:36Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_desc.h" 23#include "ah_internal.h" 24 25#include "ar5416/ar5416.h" 26#include "ar5416/ar5416reg.h" 27#include "ar5416/ar5416desc.h" 28 29/* 30 * Get the receive filter. 31 */ 32uint32_t 33ar5416GetRxFilter(struct ath_hal *ah) 34{ 35 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER); 36 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR); 37 38 if (phybits & AR_PHY_ERR_RADAR) 39 bits |= HAL_RX_FILTER_PHYRADAR; 40 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 41 bits |= HAL_RX_FILTER_PHYERR; 42 return bits; 43} 44 45/* 46 * Set the receive filter. 47 */ 48void 49ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits) 50{ 51 uint32_t phybits; 52 53 OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff)); 54 phybits = 0; 55 if (bits & HAL_RX_FILTER_PHYRADAR) 56 phybits |= AR_PHY_ERR_RADAR; 57 if (bits & HAL_RX_FILTER_PHYERR) 58 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 59 OS_REG_WRITE(ah, AR_PHY_ERR, phybits); 60 if (phybits) { 61 OS_REG_WRITE(ah, AR_RXCFG, 62 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 63 } else { 64 OS_REG_WRITE(ah, AR_RXCFG, 65 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA); 66 } 67} 68 69/* 70 * Stop Receive at the DMA engine 71 */ 72HAL_BOOL 73ar5416StopDmaReceive(struct ath_hal *ah) 74{ 75 HAL_BOOL status; 76 77 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP); 78 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 79 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 80 OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR); 81#ifdef AH_DEBUG 82 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n" 83 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 84 __func__, 85 OS_REG_READ(ah, AR_CR), 86 OS_REG_READ(ah, AR_DIAG_SW)); 87#endif 88 status = AH_FALSE; 89 } else { 90 status = AH_TRUE; 91 } 92 93 /* 94 * XXX Is this to flush whatever is in a FIFO somewhere? 95 * XXX If so, what should the correct behaviour should be? 96 */ 97 if (AR_SREV_9100(ah)) 98 OS_DELAY(3000); 99 100 return (status); 101} 102 103/* 104 * Start receive at the PCU engine 105 */ 106void 107ar5416StartPcuReceive(struct ath_hal *ah) 108{ 109 struct ath_hal_private *ahp = AH_PRIVATE(ah); 110 111 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__); 112 ar5212EnableMibCounters(ah); 113 /* NB: restore current settings */ 114 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 115 /* 116 * NB: must do after enabling phy errors to avoid rx 117 * frames w/ corrupted descriptor status. 118 */ 119 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 120} 121 122/* 123 * Stop receive at the PCU engine 124 * and abort current frame in PCU 125 */ 126void 127ar5416StopPcuReceive(struct ath_hal *ah) 128{ 129 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 130 131 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__); 132 ar5212DisableMibCounters(ah); 133} 134 135/* 136 * Initialize RX descriptor, by clearing the status and setting 137 * the size (and any other flags). 138 */ 139HAL_BOOL 140ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 141 uint32_t size, u_int flags) 142{ 143 struct ar5416_desc *ads = AR5416DESC(ds); 144 145 HALASSERT((size &~ AR_BufLen) == 0); 146 147 ads->ds_ctl1 = size & AR_BufLen; 148 if (flags & HAL_RXDESC_INTREQ) 149 ads->ds_ctl1 |= AR_RxIntrReq; 150 151 /* this should be enough */ 152 ads->ds_rxstatus8 &= ~AR_RxDone; 153 154 /* clear the rest of the status fields */ 155 OS_MEMZERO(&(ads->u), sizeof(ads->u)); 156 157 return AH_TRUE; 158} 159 160/* 161 * Process an RX descriptor, and return the status to the caller. 162 * Copy some hardware specific items into the software portion 163 * of the descriptor. 164 * 165 * NB: the caller is responsible for validating the memory contents 166 * of the descriptor (e.g. flushing any cached copy). 167 */ 168HAL_STATUS 169ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 170 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 171 struct ath_rx_status *rs) 172{ 173 struct ar5416_desc *ads = AR5416DESC(ds); 174 175 if ((ads->ds_rxstatus8 & AR_RxDone) == 0) 176 return HAL_EINPROGRESS; 177 178 rs->rs_status = 0; 179 rs->rs_flags = 0; 180 181 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen; 182 rs->rs_tstamp = ads->AR_RcvTimestamp; 183 184 /* XXX what about KeyCacheMiss? */ 185 186 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined); 187 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00); 188 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01); 189 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02); 190 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10); 191 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11); 192 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12); 193 194 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid) 195 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx); 196 else 197 rs->rs_keyix = HAL_RXKEYIX_INVALID; 198 199 /* NB: caller expected to do rate table mapping */ 200 rs->rs_rate = RXSTATUS_RATE(ah, ads); 201 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0; 202 203 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 204 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 205 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna); 206 207 if (ads->ds_rxstatus3 & AR_GI) 208 rs->rs_flags |= HAL_RX_GI; 209 if (ads->ds_rxstatus3 & AR_2040) 210 rs->rs_flags |= HAL_RX_2040; 211 212 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr) 213 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE; 214 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr) 215 rs->rs_flags |= HAL_RX_DELIM_CRC_POST; 216 if (ads->ds_rxstatus8 & AR_DecryptBusyErr) 217 rs->rs_flags |= HAL_RX_DECRYPT_BUSY; 218 if (ads->ds_rxstatus8 & AR_HiRxChain) 219 rs->rs_flags |= HAL_RX_HI_RX_CHAIN; 220 221 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) { 222 /* 223 * These four bits should not be set together. The 224 * 5416 spec states a Michael error can only occur if 225 * DecryptCRCErr not set (and TKIP is used). Experience 226 * indicates however that you can also get Michael errors 227 * when a CRC error is detected, but these are specious. 228 * Consequently we filter them out here so we don't 229 * confuse and/or complicate drivers. 230 */ 231 if (ads->ds_rxstatus8 & AR_CRCErr) 232 rs->rs_status |= HAL_RXERR_CRC; 233 else if (ads->ds_rxstatus8 & AR_PHYErr) { 234 u_int phyerr; 235 236 rs->rs_status |= HAL_RXERR_PHY; 237 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode); 238 rs->rs_phyerr = phyerr; 239 } else if (ads->ds_rxstatus8 & AR_DecryptCRCErr) 240 rs->rs_status |= HAL_RXERR_DECRYPT; 241 else if (ads->ds_rxstatus8 & AR_MichaelErr) 242 rs->rs_status |= HAL_RXERR_MIC; 243 } 244 245 return HAL_OK; 246} 247