ar5416_recv.c revision 220324
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_recv.c 220324 2011-04-04 14:52:31Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_desc.h" 23#include "ah_internal.h" 24 25#include "ar5416/ar5416.h" 26#include "ar5416/ar5416reg.h" 27#include "ar5416/ar5416desc.h" 28 29/* 30 * Start receive at the PCU engine 31 */ 32void 33ar5416StartPcuReceive(struct ath_hal *ah) 34{ 35 struct ath_hal_private *ahp = AH_PRIVATE(ah); 36 37 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__); 38 ar5212EnableMibCounters(ah); 39 /* NB: restore current settings */ 40 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 41 /* 42 * NB: must do after enabling phy errors to avoid rx 43 * frames w/ corrupted descriptor status. 44 */ 45 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 46} 47 48/* 49 * Stop receive at the PCU engine 50 * and abort current frame in PCU 51 */ 52void 53ar5416StopPcuReceive(struct ath_hal *ah) 54{ 55 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 56 57 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__); 58 ar5212DisableMibCounters(ah); 59} 60 61/* 62 * Initialize RX descriptor, by clearing the status and setting 63 * the size (and any other flags). 64 */ 65HAL_BOOL 66ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 67 uint32_t size, u_int flags) 68{ 69 struct ar5416_desc *ads = AR5416DESC(ds); 70 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 71 72 HALASSERT((size &~ AR_BufLen) == 0); 73 74 ads->ds_ctl1 = size & AR_BufLen; 75 if (flags & HAL_RXDESC_INTREQ) 76 ads->ds_ctl1 |= AR_RxIntrReq; 77 78 /* this should be enough */ 79 ads->ds_rxstatus8 &= ~AR_RxDone; 80 81 /* clear the rest of the status fields */ 82 if (! pCap->halAutoSleepSupport) 83 OS_MEMZERO(&(ads->u), sizeof(ads->u)); 84 85 return AH_TRUE; 86} 87 88/* 89 * Process an RX descriptor, and return the status to the caller. 90 * Copy some hardware specific items into the software portion 91 * of the descriptor. 92 * 93 * NB: the caller is responsible for validating the memory contents 94 * of the descriptor (e.g. flushing any cached copy). 95 */ 96HAL_STATUS 97ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 98 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 99 struct ath_rx_status *rs) 100{ 101 struct ar5416_desc *ads = AR5416DESC(ds); 102 103 if ((ads->ds_rxstatus8 & AR_RxDone) == 0) 104 return HAL_EINPROGRESS; 105 106 rs->rs_status = 0; 107 rs->rs_flags = 0; 108 109 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen; 110 rs->rs_tstamp = ads->AR_RcvTimestamp; 111 112 /* XXX what about KeyCacheMiss? */ 113 114 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined); 115 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00); 116 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01); 117 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02); 118 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10); 119 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11); 120 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12); 121 122 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid) 123 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx); 124 else 125 rs->rs_keyix = HAL_RXKEYIX_INVALID; 126 127 /* NB: caller expected to do rate table mapping */ 128 rs->rs_rate = RXSTATUS_RATE(ah, ads); 129 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0; 130 131 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 132 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 133 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna); 134 135 if (ads->ds_rxstatus3 & AR_GI) 136 rs->rs_flags |= HAL_RX_GI; 137 if (ads->ds_rxstatus3 & AR_2040) 138 rs->rs_flags |= HAL_RX_2040; 139 140 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr) 141 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE; 142 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr) 143 rs->rs_flags |= HAL_RX_DELIM_CRC_POST; 144 if (ads->ds_rxstatus8 & AR_DecryptBusyErr) 145 rs->rs_flags |= HAL_RX_DECRYPT_BUSY; 146 if (ads->ds_rxstatus8 & AR_HiRxChain) 147 rs->rs_flags |= HAL_RX_HI_RX_CHAIN; 148 149 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) { 150 /* 151 * These four bits should not be set together. The 152 * 5416 spec states a Michael error can only occur if 153 * DecryptCRCErr not set (and TKIP is used). Experience 154 * indicates however that you can also get Michael errors 155 * when a CRC error is detected, but these are specious. 156 * Consequently we filter them out here so we don't 157 * confuse and/or complicate drivers. 158 */ 159 if (ads->ds_rxstatus8 & AR_CRCErr) 160 rs->rs_status |= HAL_RXERR_CRC; 161 else if (ads->ds_rxstatus8 & AR_PHYErr) { 162 u_int phyerr; 163 164 rs->rs_status |= HAL_RXERR_PHY; 165 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode); 166 rs->rs_phyerr = phyerr; 167 } else if (ads->ds_rxstatus8 & AR_DecryptCRCErr) 168 rs->rs_status |= HAL_RXERR_DECRYPT; 169 else if (ads->ds_rxstatus8 & AR_MichaelErr) 170 rs->rs_status |= HAL_RXERR_MIC; 171 } 172 173 return HAL_OK; 174} 175