ar5416_recv.c revision 185380
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5416_recv.c,v 1.7 2008/11/11 20:46:06 sam Exp $ 18 */ 19#include "opt_ah.h" 20 21#ifdef AH_SUPPORT_AR5416 22 23#include "ah.h" 24#include "ah_desc.h" 25#include "ah_internal.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416desc.h" 30 31/* 32 * Start receive at the PCU engine 33 */ 34void 35ar5416StartPcuReceive(struct ath_hal *ah) 36{ 37 struct ath_hal_private *ahp = AH_PRIVATE(ah); 38 39 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__); 40 ar5212EnableMibCounters(ah); 41 /* NB: restore current settings */ 42 ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE); 43 /* 44 * NB: must do after enabling phy errors to avoid rx 45 * frames w/ corrupted descriptor status. 46 */ 47 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 48} 49 50/* 51 * Stop receive at the PCU engine 52 * and abort current frame in PCU 53 */ 54void 55ar5416StopPcuReceive(struct ath_hal *ah) 56{ 57 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT); 58 59 HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__); 60 ar5212DisableMibCounters(ah); 61} 62 63/* 64 * Initialize RX descriptor, by clearing the status and setting 65 * the size (and any other flags). 66 */ 67HAL_BOOL 68ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 69 uint32_t size, u_int flags) 70{ 71 struct ar5416_desc *ads = AR5416DESC(ds); 72 73 HALASSERT((size &~ AR_BufLen) == 0); 74 75 ads->ds_ctl1 = size & AR_BufLen; 76 if (flags & HAL_RXDESC_INTREQ) 77 ads->ds_ctl1 |= AR_RxIntrReq; 78 79 /* this should be enough */ 80 ads->ds_rxstatus8 &= ~AR_RxDone; 81 82 return AH_TRUE; 83} 84 85/* 86 * Process an RX descriptor, and return the status to the caller. 87 * Copy some hardware specific items into the software portion 88 * of the descriptor. 89 * 90 * NB: the caller is responsible for validating the memory contents 91 * of the descriptor (e.g. flushing any cached copy). 92 */ 93HAL_STATUS 94ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 95 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 96 struct ath_rx_status *rs) 97{ 98 struct ar5416_desc *ads = AR5416DESC(ds); 99 struct ar5416_desc *ands = AR5416DESC(nds); 100 101 if ((ads->ds_rxstatus8 & AR_RxDone) == 0) 102 return HAL_EINPROGRESS; 103 /* 104 * Given the use of a self-linked tail be very sure that the hw is 105 * done with this descriptor; the hw may have done this descriptor 106 * once and picked it up again...make sure the hw has moved on. 107 */ 108 if ((ands->ds_rxstatus8 & AR_RxDone) == 0 109 && OS_REG_READ(ah, AR_RXDP) == pa) 110 return HAL_EINPROGRESS; 111 112 rs->rs_status = 0; 113 rs->rs_flags = 0; 114 115 rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen; 116 rs->rs_tstamp = ads->AR_RcvTimestamp; 117 118 /* XXX what about KeyCacheMiss? */ 119 120 rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined); 121 rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00); 122 rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01); 123 rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02); 124 rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10); 125 rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11); 126 rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12); 127 128 if (ads->ds_rxstatus8 & AR_RxKeyIdxValid) 129 rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx); 130 else 131 rs->rs_keyix = HAL_RXKEYIX_INVALID; 132 133 /* NB: caller expected to do rate table mapping */ 134 rs->rs_rate = RXSTATUS_RATE(ah, ads); 135 rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0; 136 137 rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 138 rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 139 rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna); 140 141 if (ads->ds_rxstatus3 & AR_GI) 142 rs->rs_flags |= HAL_RX_GI; 143 if (ads->ds_rxstatus3 & AR_2040) 144 rs->rs_flags |= HAL_RX_2040; 145 146 if (ads->ds_rxstatus8 & AR_PreDelimCRCErr) 147 rs->rs_flags |= HAL_RX_DELIM_CRC_PRE; 148 if (ads->ds_rxstatus8 & AR_PostDelimCRCErr) 149 rs->rs_flags |= HAL_RX_DELIM_CRC_POST; 150 if (ads->ds_rxstatus8 & AR_DecryptBusyErr) 151 rs->rs_flags |= HAL_RX_DECRYPT_BUSY; 152 if (ads->ds_rxstatus8 & AR_HiRxChain) 153 rs->rs_flags |= HAL_RX_HI_RX_CHAIN; 154 155 if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) { 156 /* 157 * These four bits should not be set together. The 158 * 5416 spec states a Michael error can only occur if 159 * DecryptCRCErr not set (and TKIP is used). Experience 160 * indicates however that you can also get Michael errors 161 * when a CRC error is detected, but these are specious. 162 * Consequently we filter them out here so we don't 163 * confuse and/or complicate drivers. 164 */ 165 if (ads->ds_rxstatus8 & AR_CRCErr) 166 rs->rs_status |= HAL_RXERR_CRC; 167 else if (ads->ds_rxstatus8 & AR_PHYErr) { 168 u_int phyerr; 169 170 rs->rs_status |= HAL_RXERR_PHY; 171 phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode); 172 rs->rs_phyerr = phyerr; 173 } else if (ads->ds_rxstatus8 & AR_DecryptCRCErr) 174 rs->rs_status |= HAL_RXERR_DECRYPT; 175 else if (ads->ds_rxstatus8 & AR_MichaelErr) 176 rs->rs_status |= HAL_RXERR_MIC; 177 } 178 179 return HAL_OK; 180} 181#endif /* AH_SUPPORT_AR5416 */ 182