ar5416_beacon.c revision 203158
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17203158Srpaulo * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c 203158 2010-01-29 10:07:17Z rpaulo $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam 24185377Ssam#include "ar5416/ar5416.h" 25185377Ssam#include "ar5416/ar5416reg.h" 26185377Ssam#include "ar5416/ar5416phy.h" 27185377Ssam 28185377Ssam#define TU_TO_USEC(_tu) ((_tu) << 10) 29185377Ssam 30185377Ssam/* 31185377Ssam * Initialize all of the hardware registers used to 32185377Ssam * send beacons. Note that for station operation the 33185380Ssam * driver calls ar5416SetStaBeaconTimers instead. 34185377Ssam */ 35185377Ssamvoid 36185377Ssamar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 37185377Ssam{ 38185377Ssam uint32_t bperiod; 39185377Ssam 40185377Ssam OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt)); 41185377Ssam OS_REG_WRITE(ah, AR_NEXT_DBA, TU_TO_USEC(bt->bt_nextdba) >> 3); 42185377Ssam OS_REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(bt->bt_nextswba) >> 3); 43185377Ssam OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim)); 44185377Ssam 45185377Ssam bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD); 46185377Ssam OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod); 47185377Ssam OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod); 48185377Ssam OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod); 49185377Ssam OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod); 50185377Ssam 51185377Ssam /* 52185377Ssam * Reset TSF if required. 53185377Ssam */ 54185377Ssam if (bt->bt_intval & AR_BEACON_RESET_TSF) 55185377Ssam ar5416ResetTsf(ah); 56185377Ssam 57185377Ssam /* enable timers */ 58185377Ssam /* NB: flags == 0 handled specially for backwards compatibility */ 59185377Ssam OS_REG_SET_BIT(ah, AR_TIMER_MODE, 60185377Ssam bt->bt_flags != 0 ? bt->bt_flags : 61185377Ssam AR_TIMER_MODE_TBTT | AR_TIMER_MODE_DBA | AR_TIMER_MODE_SWBA); 62185377Ssam} 63185377Ssam 64185377Ssam/* 65185377Ssam * Initializes all of the hardware registers used to 66185377Ssam * send beacons. Note that for station operation the 67185377Ssam * driver calls ar5212SetStaBeaconTimers instead. 68185377Ssam */ 69185377Ssamvoid 70185377Ssamar5416BeaconInit(struct ath_hal *ah, 71185377Ssam uint32_t next_beacon, uint32_t beacon_period) 72185377Ssam{ 73185377Ssam HAL_BEACON_TIMERS bt; 74185377Ssam 75185377Ssam bt.bt_nexttbtt = next_beacon; 76185377Ssam /* 77185377Ssam * TIMER1: in AP/adhoc mode this controls the DMA beacon 78185377Ssam * alert timer; otherwise it controls the next wakeup time. 79185377Ssam * TIMER2: in AP mode, it controls the SBA beacon alert 80185377Ssam * interrupt; otherwise it sets the start of the next CFP. 81185377Ssam */ 82185377Ssam bt.bt_flags = 0; 83185377Ssam switch (AH_PRIVATE(ah)->ah_opmode) { 84185377Ssam case HAL_M_STA: 85185377Ssam case HAL_M_MONITOR: 86185377Ssam bt.bt_nextdba = 0xffff; 87185377Ssam bt.bt_nextswba = 0x7ffff; 88185377Ssam bt.bt_flags |= AR_TIMER_MODE_TBTT; 89185377Ssam break; 90185377Ssam case HAL_M_IBSS: 91185377Ssam OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY); 92185377Ssam bt.bt_flags |= AR_TIMER_MODE_NDP; 93185377Ssam /* fall thru... */ 94185377Ssam case HAL_M_HOSTAP: 95185377Ssam bt.bt_nextdba = (next_beacon - 96185377Ssam ath_hal_dma_beacon_response_time) << 3; /* 1/8 TU */ 97185377Ssam bt.bt_nextswba = (next_beacon - 98185377Ssam ath_hal_sw_beacon_response_time) << 3; /* 1/8 TU */ 99185377Ssam bt.bt_flags |= AR_TIMER_MODE_TBTT 100185377Ssam | AR_TIMER_MODE_DBA 101185377Ssam | AR_TIMER_MODE_SWBA; 102185377Ssam break; 103185377Ssam } 104185377Ssam /* 105185377Ssam * Set the ATIM window 106185377Ssam * Our hardware does not support an ATIM window of 0 107185377Ssam * (beacons will not work). If the ATIM windows is 0, 108185377Ssam * force it to 1. 109185377Ssam */ 110185377Ssam bt.bt_nextatim = next_beacon + 1; 111185377Ssam bt.bt_intval = beacon_period & 112185377Ssam (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 113185377Ssam ar5416SetBeaconTimers(ah, &bt); 114185377Ssam} 115185377Ssam 116185377Ssam#define AR_BEACON_PERIOD_MAX 0xffff 117185377Ssam 118185377Ssamvoid 119185377Ssamar5416ResetStaBeaconTimers(struct ath_hal *ah) 120185377Ssam{ 121185377Ssam uint32_t val; 122185377Ssam 123185377Ssam OS_REG_WRITE(ah, AR_NEXT_TBTT, 0); /* no beacons */ 124185377Ssam val = OS_REG_READ(ah, AR_STA_ID1); 125185377Ssam val |= AR_STA_ID1_PWR_SAV; /* XXX */ 126185377Ssam /* tell the h/w that the associated AP is not PCF capable */ 127185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 128185377Ssam val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF)); 129185377Ssam OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX); 130185377Ssam OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX); 131185377Ssam} 132185377Ssam 133185377Ssam/* 134185377Ssam * Set all the beacon related bits on the h/w for stations 135185377Ssam * i.e. initializes the corresponding h/w timers; 136185377Ssam * also tells the h/w whether to anticipate PCF beacons 137185377Ssam */ 138185377Ssamvoid 139185377Ssamar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 140185377Ssam{ 141185377Ssam uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod; 142185377Ssam 143185377Ssam HALASSERT(bs->bs_intval != 0); 144185377Ssam 145185377Ssam /* NB: no cfp setting since h/w automatically takes care */ 146185377Ssam 147185377Ssam OS_REG_WRITE(ah, AR_NEXT_TBTT, bs->bs_nexttbtt); 148185377Ssam 149185377Ssam /* 150185377Ssam * Start the beacon timers by setting the BEACON register 151185377Ssam * to the beacon interval; no need to write tim offset since 152185377Ssam * h/w parses IEs. 153185377Ssam */ 154185377Ssam OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, 155185377Ssam TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); 156185377Ssam OS_REG_WRITE(ah, AR_DBA_PERIOD, 157185377Ssam TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD)); 158185377Ssam 159185377Ssam /* 160185377Ssam * Configure the BMISS interrupt. Note that we 161185377Ssam * assume the caller blocks interrupts while enabling 162185377Ssam * the threshold. 163185377Ssam */ 164185377Ssam HALASSERT(bs->bs_bmissthreshold <= 165185377Ssam (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)); 166185377Ssam OS_REG_RMW_FIELD(ah, AR_RSSI_THR, 167185377Ssam AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 168185377Ssam 169185377Ssam /* 170185377Ssam * Program the sleep registers to correlate with the beacon setup. 171185377Ssam */ 172185377Ssam 173185377Ssam /* 174185377Ssam * Oahu beacons timers on the station were used for power 175185377Ssam * save operation (waking up in anticipation of a beacon) 176185377Ssam * and any CFP function; Venice does sleep/power-save timers 177185377Ssam * differently - so this is the right place to set them up; 178185377Ssam * don't think the beacon timers are used by venice sta hw 179185377Ssam * for any useful purpose anymore 180185377Ssam * Setup venice's sleep related timers 181185377Ssam * Current implementation assumes sw processing of beacons - 182185377Ssam * assuming an interrupt is generated every beacon which 183185377Ssam * causes the hardware to become awake until the sw tells 184185377Ssam * it to go to sleep again; beacon timeout is to allow for 185185377Ssam * beacon jitter; cab timeout is max time to wait for cab 186185377Ssam * after seeing the last DTIM or MORE CAB bit 187185377Ssam */ 188185377Ssam#define CAB_TIMEOUT_VAL 10 /* in TU */ 189185377Ssam#define BEACON_TIMEOUT_VAL 10 /* in TU */ 190185377Ssam#define SLEEP_SLOP 3 /* in TU */ 191185377Ssam 192185377Ssam /* 193185377Ssam * For max powersave mode we may want to sleep for longer than a 194185377Ssam * beacon period and not want to receive all beacons; modify the 195185377Ssam * timers accordingly; make sure to align the next TIM to the 196185377Ssam * next DTIM if we decide to wake for DTIMs only 197185377Ssam */ 198185377Ssam beaconintval = bs->bs_intval & HAL_BEACON_PERIOD; 199185377Ssam HALASSERT(beaconintval != 0); 200185377Ssam if (bs->bs_sleepduration > beaconintval) { 201185377Ssam HALASSERT(roundup(bs->bs_sleepduration, beaconintval) == 202185377Ssam bs->bs_sleepduration); 203185377Ssam beaconintval = bs->bs_sleepduration; 204185377Ssam } 205185377Ssam dtimperiod = bs->bs_dtimperiod; 206185377Ssam if (bs->bs_sleepduration > dtimperiod) { 207185377Ssam HALASSERT(dtimperiod == 0 || 208185377Ssam roundup(bs->bs_sleepduration, dtimperiod) == 209185377Ssam bs->bs_sleepduration); 210185377Ssam dtimperiod = bs->bs_sleepduration; 211185377Ssam } 212185377Ssam HALASSERT(beaconintval <= dtimperiod); 213185377Ssam if (beaconintval == dtimperiod) 214185377Ssam nextTbtt = bs->bs_nextdtim; 215185377Ssam else 216185377Ssam nextTbtt = bs->bs_nexttbtt; 217185377Ssam nextdtim = bs->bs_nextdtim; 218185377Ssam 219185377Ssam OS_REG_WRITE(ah, AR_NEXT_DTIM, 220185377Ssam TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 221185377Ssam OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 222185377Ssam 223185377Ssam /* cab timeout is now in 1/8 TU */ 224185377Ssam OS_REG_WRITE(ah, AR_SLEEP1, 225185377Ssam SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT) 226185377Ssam | AR_SLEEP1_ASSUME_DTIM); 227185377Ssam /* beacon timeout is now in 1/8 TU */ 228185377Ssam OS_REG_WRITE(ah, AR_SLEEP2, 229185377Ssam SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT)); 230185377Ssam 231185377Ssam OS_REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 232185377Ssam OS_REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 233185377Ssam OS_REG_SET_BIT(ah, AR_TIMER_MODE, 234185377Ssam AR_TIMER_MODE_TBTT | AR_TIMER_MODE_TIM | AR_TIMER_MODE_DTIM); 235185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n", 236185377Ssam __func__, bs->bs_nextdtim); 237185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n", 238185377Ssam __func__, nextTbtt); 239185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n", 240185377Ssam __func__, beaconintval); 241185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n", 242185377Ssam __func__, dtimperiod); 243185377Ssam#undef CAB_TIMEOUT_VAL 244185377Ssam#undef BEACON_TIMEOUT_VAL 245185377Ssam#undef SLEEP_SLOP 246185377Ssam} 247