ar5416_beacon.c revision 185380
1185377Ssam/*
2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc.
4185377Ssam *
5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any
6185377Ssam * purpose with or without fee is hereby granted, provided that the above
7185377Ssam * copyright notice and this permission notice appear in all copies.
8185377Ssam *
9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16185377Ssam *
17185380Ssam * $Id: ar5416_beacon.c,v 1.8 2008/11/11 01:03:12 sam Exp $
18185377Ssam */
19185377Ssam#include "opt_ah.h"
20185377Ssam
21185377Ssam#ifdef AH_SUPPORT_AR5416
22185377Ssam
23185377Ssam#include "ah.h"
24185377Ssam#include "ah_internal.h"
25185377Ssam
26185377Ssam#include "ar5416/ar5416.h"
27185377Ssam#include "ar5416/ar5416reg.h"
28185377Ssam#include "ar5416/ar5416phy.h"
29185377Ssam
30185377Ssam#define TU_TO_USEC(_tu)		((_tu) << 10)
31185377Ssam
32185377Ssam/*
33185377Ssam * Initialize all of the hardware registers used to
34185377Ssam * send beacons.  Note that for station operation the
35185380Ssam * driver calls ar5416SetStaBeaconTimers instead.
36185377Ssam */
37185377Ssamvoid
38185377Ssamar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
39185377Ssam{
40185377Ssam	uint32_t bperiod;
41185377Ssam
42185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));
43185377Ssam	OS_REG_WRITE(ah, AR_NEXT_DBA, TU_TO_USEC(bt->bt_nextdba) >> 3);
44185377Ssam	OS_REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(bt->bt_nextswba) >> 3);
45185377Ssam	OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));
46185377Ssam
47185377Ssam	bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD);
48185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);
49185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);
50185377Ssam	OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);
51185377Ssam	OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);
52185377Ssam
53185377Ssam	/*
54185377Ssam	 * Reset TSF if required.
55185377Ssam	 */
56185377Ssam	if (bt->bt_intval & AR_BEACON_RESET_TSF)
57185377Ssam		ar5416ResetTsf(ah);
58185377Ssam
59185377Ssam	/* enable timers */
60185377Ssam	/* NB: flags == 0 handled specially for backwards compatibility */
61185377Ssam	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
62185377Ssam	    bt->bt_flags != 0 ? bt->bt_flags :
63185377Ssam		AR_TIMER_MODE_TBTT | AR_TIMER_MODE_DBA | AR_TIMER_MODE_SWBA);
64185377Ssam}
65185377Ssam
66185377Ssam/*
67185377Ssam * Initializes all of the hardware registers used to
68185377Ssam * send beacons.  Note that for station operation the
69185377Ssam * driver calls ar5212SetStaBeaconTimers instead.
70185377Ssam */
71185377Ssamvoid
72185377Ssamar5416BeaconInit(struct ath_hal *ah,
73185377Ssam	uint32_t next_beacon, uint32_t beacon_period)
74185377Ssam{
75185377Ssam	HAL_BEACON_TIMERS bt;
76185377Ssam
77185377Ssam	bt.bt_nexttbtt = next_beacon;
78185377Ssam	/*
79185377Ssam	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
80185377Ssam	 * alert timer; otherwise it controls the next wakeup time.
81185377Ssam	 * TIMER2: in AP mode, it controls the SBA beacon alert
82185377Ssam	 * interrupt; otherwise it sets the start of the next CFP.
83185377Ssam	 */
84185377Ssam	bt.bt_flags = 0;
85185377Ssam	switch (AH_PRIVATE(ah)->ah_opmode) {
86185377Ssam	case HAL_M_STA:
87185377Ssam	case HAL_M_MONITOR:
88185377Ssam		bt.bt_nextdba = 0xffff;
89185377Ssam		bt.bt_nextswba = 0x7ffff;
90185377Ssam		bt.bt_flags |= AR_TIMER_MODE_TBTT;
91185377Ssam		break;
92185377Ssam	case HAL_M_IBSS:
93185377Ssam		OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);
94185377Ssam		bt.bt_flags |= AR_TIMER_MODE_NDP;
95185377Ssam		/* fall thru... */
96185377Ssam	case HAL_M_HOSTAP:
97185377Ssam		bt.bt_nextdba = (next_beacon -
98185377Ssam			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
99185377Ssam		bt.bt_nextswba = (next_beacon -
100185377Ssam			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
101185377Ssam		bt.bt_flags |= AR_TIMER_MODE_TBTT
102185377Ssam			    |  AR_TIMER_MODE_DBA
103185377Ssam			    |  AR_TIMER_MODE_SWBA;
104185377Ssam		break;
105185377Ssam	}
106185377Ssam	/*
107185377Ssam	 * Set the ATIM window
108185377Ssam	 * Our hardware does not support an ATIM window of 0
109185377Ssam	 * (beacons will not work).  If the ATIM windows is 0,
110185377Ssam	 * force it to 1.
111185377Ssam	 */
112185377Ssam	bt.bt_nextatim = next_beacon + 1;
113185377Ssam	bt.bt_intval = beacon_period &
114185377Ssam		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
115185377Ssam	ar5416SetBeaconTimers(ah, &bt);
116185377Ssam}
117185377Ssam
118185377Ssam#define AR_BEACON_PERIOD_MAX	0xffff
119185377Ssam
120185377Ssamvoid
121185377Ssamar5416ResetStaBeaconTimers(struct ath_hal *ah)
122185377Ssam{
123185377Ssam	uint32_t val;
124185377Ssam
125185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TBTT, 0);		/* no beacons */
126185377Ssam	val = OS_REG_READ(ah, AR_STA_ID1);
127185377Ssam	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
128185377Ssam	/* tell the h/w that the associated AP is not PCF capable */
129185377Ssam	OS_REG_WRITE(ah, AR_STA_ID1,
130185377Ssam		val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
131185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX);
132185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX);
133185377Ssam}
134185377Ssam
135185377Ssam/*
136185377Ssam * Set all the beacon related bits on the h/w for stations
137185377Ssam * i.e. initializes the corresponding h/w timers;
138185377Ssam * also tells the h/w whether to anticipate PCF beacons
139185377Ssam */
140185377Ssamvoid
141185377Ssamar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
142185377Ssam{
143185377Ssam	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
144185377Ssam
145185377Ssam	HALASSERT(bs->bs_intval != 0);
146185377Ssam
147185377Ssam	/* NB: no cfp setting since h/w automatically takes care */
148185377Ssam
149185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TBTT, bs->bs_nexttbtt);
150185377Ssam
151185377Ssam	/*
152185377Ssam	 * Start the beacon timers by setting the BEACON register
153185377Ssam	 * to the beacon interval; no need to write tim offset since
154185377Ssam	 * h/w parses IEs.
155185377Ssam	 */
156185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD,
157185377Ssam			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
158185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD,
159185377Ssam			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
160185377Ssam
161185377Ssam	/*
162185377Ssam	 * Configure the BMISS interrupt.  Note that we
163185377Ssam	 * assume the caller blocks interrupts while enabling
164185377Ssam	 * the threshold.
165185377Ssam	 */
166185377Ssam	HALASSERT(bs->bs_bmissthreshold <=
167185377Ssam		(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S));
168185377Ssam	OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
169185377Ssam		AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
170185377Ssam
171185377Ssam	/*
172185377Ssam	 * Program the sleep registers to correlate with the beacon setup.
173185377Ssam	 */
174185377Ssam
175185377Ssam	/*
176185377Ssam	 * Oahu beacons timers on the station were used for power
177185377Ssam	 * save operation (waking up in anticipation of a beacon)
178185377Ssam	 * and any CFP function; Venice does sleep/power-save timers
179185377Ssam	 * differently - so this is the right place to set them up;
180185377Ssam	 * don't think the beacon timers are used by venice sta hw
181185377Ssam	 * for any useful purpose anymore
182185377Ssam	 * Setup venice's sleep related timers
183185377Ssam	 * Current implementation assumes sw processing of beacons -
184185377Ssam	 *   assuming an interrupt is generated every beacon which
185185377Ssam	 *   causes the hardware to become awake until the sw tells
186185377Ssam	 *   it to go to sleep again; beacon timeout is to allow for
187185377Ssam	 *   beacon jitter; cab timeout is max time to wait for cab
188185377Ssam	 *   after seeing the last DTIM or MORE CAB bit
189185377Ssam	 */
190185377Ssam#define CAB_TIMEOUT_VAL     10 /* in TU */
191185377Ssam#define BEACON_TIMEOUT_VAL  10 /* in TU */
192185377Ssam#define SLEEP_SLOP          3  /* in TU */
193185377Ssam
194185377Ssam	/*
195185377Ssam	 * For max powersave mode we may want to sleep for longer than a
196185377Ssam	 * beacon period and not want to receive all beacons; modify the
197185377Ssam	 * timers accordingly; make sure to align the next TIM to the
198185377Ssam	 * next DTIM if we decide to wake for DTIMs only
199185377Ssam	 */
200185377Ssam	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
201185377Ssam	HALASSERT(beaconintval != 0);
202185377Ssam	if (bs->bs_sleepduration > beaconintval) {
203185377Ssam		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
204185377Ssam				bs->bs_sleepduration);
205185377Ssam		beaconintval = bs->bs_sleepduration;
206185377Ssam	}
207185377Ssam	dtimperiod = bs->bs_dtimperiod;
208185377Ssam	if (bs->bs_sleepduration > dtimperiod) {
209185377Ssam		HALASSERT(dtimperiod == 0 ||
210185377Ssam			roundup(bs->bs_sleepduration, dtimperiod) ==
211185377Ssam				bs->bs_sleepduration);
212185377Ssam		dtimperiod = bs->bs_sleepduration;
213185377Ssam	}
214185377Ssam	HALASSERT(beaconintval <= dtimperiod);
215185377Ssam	if (beaconintval == dtimperiod)
216185377Ssam		nextTbtt = bs->bs_nextdtim;
217185377Ssam	else
218185377Ssam		nextTbtt = bs->bs_nexttbtt;
219185377Ssam	nextdtim = bs->bs_nextdtim;
220185377Ssam
221185377Ssam	OS_REG_WRITE(ah, AR_NEXT_DTIM,
222185377Ssam		TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
223185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
224185377Ssam
225185377Ssam	/* cab timeout is now in 1/8 TU */
226185377Ssam	OS_REG_WRITE(ah, AR_SLEEP1,
227185377Ssam		SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT)
228185377Ssam		| AR_SLEEP1_ASSUME_DTIM);
229185377Ssam	/* beacon timeout is now in 1/8 TU */
230185377Ssam	OS_REG_WRITE(ah, AR_SLEEP2,
231185377Ssam		SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT));
232185377Ssam
233185377Ssam	OS_REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
234185377Ssam	OS_REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
235185377Ssam	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
236185377Ssam	     AR_TIMER_MODE_TBTT | AR_TIMER_MODE_TIM | AR_TIMER_MODE_DTIM);
237185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
238185377Ssam	    __func__, bs->bs_nextdtim);
239185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
240185377Ssam	    __func__, nextTbtt);
241185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
242185377Ssam	    __func__, beaconintval);
243185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
244185377Ssam	    __func__, dtimperiod);
245185377Ssam#undef CAB_TIMEOUT_VAL
246185377Ssam#undef BEACON_TIMEOUT_VAL
247185377Ssam#undef SLEEP_SLOP
248185377Ssam}
249185377Ssam#endif /* AH_SUPPORT_AR5416 */
250