1185377Ssam/*
2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc.
4185377Ssam *
5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any
6185377Ssam * purpose with or without fee is hereby granted, provided that the above
7185377Ssam * copyright notice and this permission notice appear in all copies.
8185377Ssam *
9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16185377Ssam *
17203158Srpaulo * $FreeBSD$
18185377Ssam */
19185377Ssam#include "opt_ah.h"
20185377Ssam
21185377Ssam#include "ah.h"
22185377Ssam#include "ah_internal.h"
23185377Ssam
24185377Ssam#include "ar5416/ar5416.h"
25185377Ssam#include "ar5416/ar5416reg.h"
26185377Ssam#include "ar5416/ar5416phy.h"
27185377Ssam
28185377Ssam#define TU_TO_USEC(_tu)		((_tu) << 10)
29225111Sadrian#define	ONE_EIGHTH_TU_TO_USEC(_tu8)	((_tu8) << 7)
30185377Ssam
31185377Ssam/*
32225444Sadrian * Return the hardware NextTBTT in TSF
33225444Sadrian */
34225444Sadrianuint64_t
35225444Sadrianar5416GetNextTBTT(struct ath_hal *ah)
36225444Sadrian{
37225444Sadrian	return OS_REG_READ(ah, AR_NEXT_TBTT);
38225444Sadrian}
39225444Sadrian
40225444Sadrian/*
41185377Ssam * Initialize all of the hardware registers used to
42185377Ssam * send beacons.  Note that for station operation the
43185380Ssam * driver calls ar5416SetStaBeaconTimers instead.
44185377Ssam */
45185377Ssamvoid
46185377Ssamar5416SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
47185377Ssam{
48185377Ssam	uint32_t bperiod;
49225819Sadrian	struct ath_hal_5212 *ahp = AH5212(ah);
50185377Ssam
51185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bt->bt_nexttbtt));
52225111Sadrian	OS_REG_WRITE(ah, AR_NEXT_DBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextdba));
53225111Sadrian	OS_REG_WRITE(ah, AR_NEXT_SWBA, ONE_EIGHTH_TU_TO_USEC(bt->bt_nextswba));
54185377Ssam	OS_REG_WRITE(ah, AR_NEXT_NDP, TU_TO_USEC(bt->bt_nextatim));
55185377Ssam
56185377Ssam	bperiod = TU_TO_USEC(bt->bt_intval & HAL_BEACON_PERIOD);
57225819Sadrian	ahp->ah_beaconInterval = bt->bt_intval & HAL_BEACON_PERIOD;
58185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, bperiod);
59185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD, bperiod);
60185377Ssam	OS_REG_WRITE(ah, AR_SWBA_PERIOD, bperiod);
61185377Ssam	OS_REG_WRITE(ah, AR_NDP_PERIOD, bperiod);
62185377Ssam
63185377Ssam	/*
64185377Ssam	 * Reset TSF if required.
65185377Ssam	 */
66185377Ssam	if (bt->bt_intval & AR_BEACON_RESET_TSF)
67185377Ssam		ar5416ResetTsf(ah);
68185377Ssam
69185377Ssam	/* enable timers */
70185377Ssam	/* NB: flags == 0 handled specially for backwards compatibility */
71185377Ssam	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
72185377Ssam	    bt->bt_flags != 0 ? bt->bt_flags :
73185377Ssam		AR_TIMER_MODE_TBTT | AR_TIMER_MODE_DBA | AR_TIMER_MODE_SWBA);
74185377Ssam}
75185377Ssam
76185377Ssam/*
77185377Ssam * Initializes all of the hardware registers used to
78185377Ssam * send beacons.  Note that for station operation the
79185377Ssam * driver calls ar5212SetStaBeaconTimers instead.
80185377Ssam */
81185377Ssamvoid
82185377Ssamar5416BeaconInit(struct ath_hal *ah,
83185377Ssam	uint32_t next_beacon, uint32_t beacon_period)
84185377Ssam{
85185377Ssam	HAL_BEACON_TIMERS bt;
86185377Ssam
87185377Ssam	bt.bt_nexttbtt = next_beacon;
88185377Ssam	/*
89185377Ssam	 * TIMER1: in AP/adhoc mode this controls the DMA beacon
90185377Ssam	 * alert timer; otherwise it controls the next wakeup time.
91185377Ssam	 * TIMER2: in AP mode, it controls the SBA beacon alert
92185377Ssam	 * interrupt; otherwise it sets the start of the next CFP.
93185377Ssam	 */
94185377Ssam	bt.bt_flags = 0;
95185377Ssam	switch (AH_PRIVATE(ah)->ah_opmode) {
96185377Ssam	case HAL_M_STA:
97185377Ssam	case HAL_M_MONITOR:
98185377Ssam		bt.bt_nextdba = 0xffff;
99185377Ssam		bt.bt_nextswba = 0x7ffff;
100185377Ssam		bt.bt_flags |= AR_TIMER_MODE_TBTT;
101185377Ssam		break;
102185377Ssam	case HAL_M_IBSS:
103185377Ssam		OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ATIM_TXPOLICY);
104185377Ssam		bt.bt_flags |= AR_TIMER_MODE_NDP;
105185377Ssam		/* fall thru... */
106185377Ssam	case HAL_M_HOSTAP:
107185377Ssam		bt.bt_nextdba = (next_beacon -
108223465Sadrian		    ah->ah_config.ah_dma_beacon_response_time) << 3;	/* 1/8 TU */
109185377Ssam		bt.bt_nextswba = (next_beacon -
110223465Sadrian		    ah->ah_config.ah_sw_beacon_response_time) << 3;	/* 1/8 TU */
111185377Ssam		bt.bt_flags |= AR_TIMER_MODE_TBTT
112185377Ssam			    |  AR_TIMER_MODE_DBA
113185377Ssam			    |  AR_TIMER_MODE_SWBA;
114185377Ssam		break;
115185377Ssam	}
116185377Ssam	/*
117185377Ssam	 * Set the ATIM window
118185377Ssam	 * Our hardware does not support an ATIM window of 0
119185377Ssam	 * (beacons will not work).  If the ATIM windows is 0,
120185377Ssam	 * force it to 1.
121185377Ssam	 */
122185377Ssam	bt.bt_nextatim = next_beacon + 1;
123185377Ssam	bt.bt_intval = beacon_period &
124185377Ssam		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
125185377Ssam	ar5416SetBeaconTimers(ah, &bt);
126185377Ssam}
127185377Ssam
128185377Ssam#define AR_BEACON_PERIOD_MAX	0xffff
129185377Ssam
130185377Ssamvoid
131185377Ssamar5416ResetStaBeaconTimers(struct ath_hal *ah)
132185377Ssam{
133185377Ssam	uint32_t val;
134185377Ssam
135185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TBTT, 0);		/* no beacons */
136185377Ssam	val = OS_REG_READ(ah, AR_STA_ID1);
137185377Ssam	val |= AR_STA_ID1_PWR_SAV;		/* XXX */
138185377Ssam	/* tell the h/w that the associated AP is not PCF capable */
139185377Ssam	OS_REG_WRITE(ah, AR_STA_ID1,
140185377Ssam		val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
141185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD, AR_BEACON_PERIOD_MAX);
142185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD, AR_BEACON_PERIOD_MAX);
143185377Ssam}
144185377Ssam
145185377Ssam/*
146185377Ssam * Set all the beacon related bits on the h/w for stations
147185377Ssam * i.e. initializes the corresponding h/w timers;
148185377Ssam * also tells the h/w whether to anticipate PCF beacons
149185377Ssam */
150185377Ssamvoid
151185377Ssamar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
152185377Ssam{
153185377Ssam	uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
154185377Ssam
155185377Ssam	HALASSERT(bs->bs_intval != 0);
156185377Ssam
157185377Ssam	/* NB: no cfp setting since h/w automatically takes care */
158185377Ssam
159225111Sadrian	OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bs->bs_nexttbtt));
160185377Ssam
161185377Ssam	/*
162185377Ssam	 * Start the beacon timers by setting the BEACON register
163185377Ssam	 * to the beacon interval; no need to write tim offset since
164185377Ssam	 * h/w parses IEs.
165185377Ssam	 */
166185377Ssam	OS_REG_WRITE(ah, AR5416_BEACON_PERIOD,
167185377Ssam			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
168185377Ssam	OS_REG_WRITE(ah, AR_DBA_PERIOD,
169185377Ssam			 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
170185377Ssam
171185377Ssam	/*
172185377Ssam	 * Configure the BMISS interrupt.  Note that we
173185377Ssam	 * assume the caller blocks interrupts while enabling
174185377Ssam	 * the threshold.
175185377Ssam	 */
176185377Ssam	HALASSERT(bs->bs_bmissthreshold <=
177185377Ssam		(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S));
178185377Ssam	OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
179185377Ssam		AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
180185377Ssam
181185377Ssam	/*
182185377Ssam	 * Program the sleep registers to correlate with the beacon setup.
183185377Ssam	 */
184185377Ssam
185185377Ssam	/*
186185377Ssam	 * Oahu beacons timers on the station were used for power
187185377Ssam	 * save operation (waking up in anticipation of a beacon)
188185377Ssam	 * and any CFP function; Venice does sleep/power-save timers
189185377Ssam	 * differently - so this is the right place to set them up;
190185377Ssam	 * don't think the beacon timers are used by venice sta hw
191185377Ssam	 * for any useful purpose anymore
192185377Ssam	 * Setup venice's sleep related timers
193185377Ssam	 * Current implementation assumes sw processing of beacons -
194185377Ssam	 *   assuming an interrupt is generated every beacon which
195185377Ssam	 *   causes the hardware to become awake until the sw tells
196185377Ssam	 *   it to go to sleep again; beacon timeout is to allow for
197185377Ssam	 *   beacon jitter; cab timeout is max time to wait for cab
198185377Ssam	 *   after seeing the last DTIM or MORE CAB bit
199185377Ssam	 */
200265031Sadrian
201265031Sadrian/*
202265031Sadrian * I've bumped these to 30TU for now.
203265031Sadrian *
204265031Sadrian * Some APs (AR933x/AR934x?) in 2GHz especially seem to not always
205265031Sadrian * transmit beacon frames at exactly the right times and with it set
206265031Sadrian * to 10TU, the NIC starts not waking up at the right times to hear
207265031Sadrian * these slightly-larger-jitering beacons.  It also never recovers
208265031Sadrian * from that (it doesn't resync? I'm not sure.)
209265031Sadrian *
210265031Sadrian * So for now bump this to 30TU.  Ideally we'd cap this based on
211265031Sadrian * the beacon interval so the sum of CAB+BEACON timeouts never
212265031Sadrian * exceeded the beacon interval.
213265031Sadrian *
214265031Sadrian * Now, since we're doing all the math in the ath(4) driver in TU
215265031Sadrian * rather than TSF, we may be seeing the result of dumb rounding
216265031Sadrian * errors causing the jitter to actually be a much bigger problem.
217265031Sadrian * I'll have to investigate that with a fine tooth comb.
218265031Sadrian */
219185377Ssam#define CAB_TIMEOUT_VAL     10 /* in TU */
220185377Ssam#define BEACON_TIMEOUT_VAL  10 /* in TU */
221185377Ssam#define SLEEP_SLOP          3  /* in TU */
222185377Ssam
223185377Ssam	/*
224185377Ssam	 * For max powersave mode we may want to sleep for longer than a
225185377Ssam	 * beacon period and not want to receive all beacons; modify the
226185377Ssam	 * timers accordingly; make sure to align the next TIM to the
227185377Ssam	 * next DTIM if we decide to wake for DTIMs only
228185377Ssam	 */
229185377Ssam	beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
230185377Ssam	HALASSERT(beaconintval != 0);
231185377Ssam	if (bs->bs_sleepduration > beaconintval) {
232185377Ssam		HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
233185377Ssam				bs->bs_sleepduration);
234185377Ssam		beaconintval = bs->bs_sleepduration;
235185377Ssam	}
236185377Ssam	dtimperiod = bs->bs_dtimperiod;
237185377Ssam	if (bs->bs_sleepduration > dtimperiod) {
238185377Ssam		HALASSERT(dtimperiod == 0 ||
239185377Ssam			roundup(bs->bs_sleepduration, dtimperiod) ==
240185377Ssam				bs->bs_sleepduration);
241185377Ssam		dtimperiod = bs->bs_sleepduration;
242185377Ssam	}
243185377Ssam	HALASSERT(beaconintval <= dtimperiod);
244185377Ssam	if (beaconintval == dtimperiod)
245185377Ssam		nextTbtt = bs->bs_nextdtim;
246185377Ssam	else
247185377Ssam		nextTbtt = bs->bs_nexttbtt;
248185377Ssam	nextdtim = bs->bs_nextdtim;
249185377Ssam
250185377Ssam	OS_REG_WRITE(ah, AR_NEXT_DTIM,
251185377Ssam		TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
252185377Ssam	OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
253185377Ssam
254185377Ssam	/* cab timeout is now in 1/8 TU */
255225125Sadrian	OS_REG_WRITE(ah, AR5416_SLEEP1,
256185377Ssam		SM((CAB_TIMEOUT_VAL << 3), AR5416_SLEEP1_CAB_TIMEOUT)
257225125Sadrian		| AR5416_SLEEP1_ASSUME_DTIM);
258225125Sadrian
259225125Sadrian	/* XXX autosleep? Use min beacon timeout; check ath9k -adrian */
260185377Ssam	/* beacon timeout is now in 1/8 TU */
261225125Sadrian	OS_REG_WRITE(ah, AR5416_SLEEP2,
262185377Ssam		SM((BEACON_TIMEOUT_VAL << 3), AR5416_SLEEP2_BEACON_TIMEOUT));
263185377Ssam
264225125Sadrian	/* TIM_PERIOD and DTIM_PERIOD are now in uS. */
265225125Sadrian	OS_REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
266225125Sadrian	OS_REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
267225125Sadrian
268185377Ssam	OS_REG_SET_BIT(ah, AR_TIMER_MODE,
269185377Ssam	     AR_TIMER_MODE_TBTT | AR_TIMER_MODE_TIM | AR_TIMER_MODE_DTIM);
270265031Sadrian
271265031Sadrian#define	HAL_TSFOOR_THRESHOLD	0x00004240 /* TSF OOR threshold (16k us) */
272265031Sadrian
273265031Sadrian	/* TSF out of range threshold */
274265031Sadrian//	OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
275265031Sadrian	OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, HAL_TSFOOR_THRESHOLD);
276265031Sadrian
277185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
278185377Ssam	    __func__, bs->bs_nextdtim);
279185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
280185377Ssam	    __func__, nextTbtt);
281185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
282185377Ssam	    __func__, beaconintval);
283185377Ssam	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
284185377Ssam	    __func__, dtimperiod);
285185377Ssam#undef CAB_TIMEOUT_VAL
286185377Ssam#undef BEACON_TIMEOUT_VAL
287185377Ssam#undef SLEEP_SLOP
288185377Ssam}
289