1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#ifdef AH_SUPPORT_AR5312 22185377Ssam 23185377Ssam#include "ah.h" 24185377Ssam#include "ah_internal.h" 25185377Ssam#include "ah_devid.h" 26185377Ssam 27185377Ssam#include "ar5312/ar5312.h" 28185377Ssam#include "ar5312/ar5312reg.h" 29185377Ssam#include "ar5312/ar5312phy.h" 30185377Ssam 31185377Ssam#define AR_NUM_GPIO 6 /* 6 GPIO pins */ 32185377Ssam#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 33185377Ssam 34185377Ssam/* 35185377Ssam * Change the LED blinking pattern to correspond to the connectivity 36185377Ssam */ 37185377Ssamvoid 38185377Ssamar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 39185377Ssam{ 40185377Ssam uint32_t val; 41185377Ssam uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)); 42185377Ssam if(IS_2316(ah)) return; /* not yet */ 43185377Ssam val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) | 44185377Ssam SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) | 45185377Ssam 2; 46185377Ssam OS_REG_WRITE(ah, resOffset+AR5312_PCICFG, 47185377Ssam (OS_REG_READ(ah, AR5312_PCICFG) &~ 48185377Ssam (AR5312_PCICFG_LEDSEL | AR5312_PCICFG_LEDMODE | 49185377Ssam AR5312_PCICFG_LEDSBR)) 50185377Ssam | val); 51185377Ssam} 52185377Ssam 53185377Ssam/* 54185377Ssam * Detect if our wireless mac is present. 55185377Ssam */ 56185377SsamHAL_BOOL 57185377Ssamar5312DetectCardPresent(struct ath_hal *ah) 58185377Ssam{ 59185377Ssam uint16_t macVersion, macRev; 60185377Ssam uint32_t v; 61185377Ssam 62185377Ssam /* 63185377Ssam * Read the Silicon Revision register and compare that 64185377Ssam * to what we read at attach time. If the same, we say 65185377Ssam * a card/device is present. 66185377Ssam */ 67185377Ssam#if (AH_SUPPORT_2316 || AH_SUPPORT_2317) 68185377Ssam if(IS_5315(ah)) 69185377Ssam { 70185377Ssam v = (OS_REG_READ(ah, 71185377Ssam (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV)) 72185377Ssam & AR_SREV_ID; 73185377Ssam macVersion = v >> AR_SREV_ID_S; 74185377Ssam macRev = v & AR_SREV_REVISION; 75185377Ssam return (AH_PRIVATE(ah)->ah_macVersion == macVersion && 76185377Ssam AH_PRIVATE(ah)->ah_macRev == macRev); 77185377Ssam } 78185377Ssam else 79185377Ssam#endif 80185377Ssam { 81185377Ssam v = (OS_REG_READ(ah, 82185377Ssam (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV)) 83185377Ssam & AR_SREV_ID; 84185377Ssam macVersion = v >> AR_SREV_ID_S; 85185377Ssam macRev = v & AR_SREV_REVISION; 86185377Ssam return (AH_PRIVATE(ah)->ah_macVersion == macVersion && 87185377Ssam AH_PRIVATE(ah)->ah_macRev == macRev); 88185377Ssam } 89185377Ssam} 90185377Ssam 91185377Ssam/* 92185377Ssam * If 32KHz clock exists, use it to lower power consumption during sleep 93185377Ssam * 94185377Ssam * Note: If clock is set to 32 KHz, delays on accessing certain 95185377Ssam * baseband registers (27-31, 124-127) are required. 96185377Ssam */ 97185377Ssamvoid 98185377Ssamar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode) 99185377Ssam{ 100185377Ssam if (ar5212Use32KHzclock(ah, opmode)) { 101185377Ssam /* 102185377Ssam * Enable clocks to be turned OFF in BB during sleep 103185377Ssam * and also enable turning OFF 32MHz/40MHz Refclk 104185377Ssam * from A2. 105185377Ssam */ 106185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 107185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d); 108185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c); 109185377Ssam OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03); 110185377Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05); 111185380Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 112185380Ssam IS_RAD5112_ANY(ah) ? 0x14 : 0x18); 113185377Ssam 114185377Ssam OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1); 115185377Ssam OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ 116185377Ssam 117185377Ssam } else { 118185377Ssam OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ 119185377Ssam OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 120185380Ssam IS_RAD5112_ANY(ah) ? 39 : 31); 121185377Ssam 122185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 123185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); 124185377Ssam 125185377Ssam if (IS_5312_2_X(ah)) { 126185377Ssam /* Set ADC/DAC select values */ 127185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); 128185377Ssam } else { 129185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 130185377Ssam OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); 131185377Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); 132185380Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 133185380Ssam IS_RAD5112_ANY(ah) ? 0x14 : 0x18); 134185377Ssam } 135185377Ssam } 136185377Ssam} 137185377Ssam 138185377Ssam/* 139185377Ssam * If 32KHz clock exists, turn it off and turn back on the 32Mhz 140185377Ssam */ 141185377Ssamvoid 142185377Ssamar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode) 143185377Ssam{ 144185377Ssam if (ar5212Use32KHzclock(ah, opmode)) { 145185377Ssam /* # Set sleep clock rate back to 32 MHz. */ 146185377Ssam OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ 147185377Ssam OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 148185380Ssam IS_RAD5112_ANY(ah) ? 39 : 31); 149185377Ssam 150185377Ssam /* 151185377Ssam * Restore BB registers to power-on defaults 152185377Ssam */ 153185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); 154185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); 155185377Ssam if (IS_5312_2_X(ah)) { 156185377Ssam /* Set ADC/DAC select values */ 157185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); 158185377Ssam } else { 159185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 160185377Ssam OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); 161185377Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); 162185380Ssam OS_REG_WRITE(ah, AR_PHY_REFCLKPD, 163185380Ssam IS_RAD5112_ANY(ah) ? 0x14 : 0x18); 164185377Ssam } 165185377Ssam } 166185377Ssam} 167185377Ssam 168185377Ssam#endif /* AH_SUPPORT_AR5312 */ 169