ar5211_reset.c revision 185377
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185377Ssam * $Id: ar5211_reset.c,v 1.6 2008/11/10 04:08:03 sam Exp $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#ifdef AH_SUPPORT_AR5211 22185377Ssam/* 23185377Ssam * Chips specific device attachment and device info collection 24185377Ssam * Connects Init Reg Vectors, EEPROM Data, and device Functions. 25185377Ssam */ 26185377Ssam#include "ah.h" 27185377Ssam#include "ah_internal.h" 28185377Ssam#include "ah_devid.h" 29185377Ssam 30185377Ssam#include "ar5211/ar5211.h" 31185377Ssam#include "ar5211/ar5211reg.h" 32185377Ssam#include "ar5211/ar5211phy.h" 33185377Ssam 34185377Ssam#include "ah_eeprom_v3.h" 35185377Ssam 36185377Ssam/* Add static register initialization vectors */ 37185377Ssam#include "ar5211/boss.ini" 38185377Ssam 39185377Ssam/* 40185377Ssam * Structure to hold 11b tuning information for Beanie/Sombrero 41185377Ssam * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12 42185377Ssam */ 43185377Ssamtypedef struct { 44185377Ssam uint32_t refClkSel; /* reference clock, 1 for 16 MHz */ 45185377Ssam uint32_t channelSelect; /* P[7:4]S[3:0] bits */ 46185377Ssam uint16_t channel5111; /* 11a channel for 5111 */ 47185377Ssam} CHAN_INFO_2GHZ; 48185377Ssam 49185377Ssam#define CI_2GHZ_INDEX_CORRECTION 19 50185377Ssamconst static CHAN_INFO_2GHZ chan2GHzData[] = { 51185377Ssam { 1, 0x46, 96 }, /* 2312 -19 */ 52185377Ssam { 1, 0x46, 97 }, /* 2317 -18 */ 53185377Ssam { 1, 0x46, 98 }, /* 2322 -17 */ 54185377Ssam { 1, 0x46, 99 }, /* 2327 -16 */ 55185377Ssam { 1, 0x46, 100 }, /* 2332 -15 */ 56185377Ssam { 1, 0x46, 101 }, /* 2337 -14 */ 57185377Ssam { 1, 0x46, 102 }, /* 2342 -13 */ 58185377Ssam { 1, 0x46, 103 }, /* 2347 -12 */ 59185377Ssam { 1, 0x46, 104 }, /* 2352 -11 */ 60185377Ssam { 1, 0x46, 105 }, /* 2357 -10 */ 61185377Ssam { 1, 0x46, 106 }, /* 2362 -9 */ 62185377Ssam { 1, 0x46, 107 }, /* 2367 -8 */ 63185377Ssam { 1, 0x46, 108 }, /* 2372 -7 */ 64185377Ssam /* index -6 to 0 are pad to make this a nolookup table */ 65185377Ssam { 1, 0x46, 116 }, /* -6 */ 66185377Ssam { 1, 0x46, 116 }, /* -5 */ 67185377Ssam { 1, 0x46, 116 }, /* -4 */ 68185377Ssam { 1, 0x46, 116 }, /* -3 */ 69185377Ssam { 1, 0x46, 116 }, /* -2 */ 70185377Ssam { 1, 0x46, 116 }, /* -1 */ 71185377Ssam { 1, 0x46, 116 }, /* 0 */ 72185377Ssam { 1, 0x46, 116 }, /* 2412 1 */ 73185377Ssam { 1, 0x46, 117 }, /* 2417 2 */ 74185377Ssam { 1, 0x46, 118 }, /* 2422 3 */ 75185377Ssam { 1, 0x46, 119 }, /* 2427 4 */ 76185377Ssam { 1, 0x46, 120 }, /* 2432 5 */ 77185377Ssam { 1, 0x46, 121 }, /* 2437 6 */ 78185377Ssam { 1, 0x46, 122 }, /* 2442 7 */ 79185377Ssam { 1, 0x46, 123 }, /* 2447 8 */ 80185377Ssam { 1, 0x46, 124 }, /* 2452 9 */ 81185377Ssam { 1, 0x46, 125 }, /* 2457 10 */ 82185377Ssam { 1, 0x46, 126 }, /* 2462 11 */ 83185377Ssam { 1, 0x46, 127 }, /* 2467 12 */ 84185377Ssam { 1, 0x46, 128 }, /* 2472 13 */ 85185377Ssam { 1, 0x44, 124 }, /* 2484 14 */ 86185377Ssam { 1, 0x46, 136 }, /* 2512 15 */ 87185377Ssam { 1, 0x46, 140 }, /* 2532 16 */ 88185377Ssam { 1, 0x46, 144 }, /* 2552 17 */ 89185377Ssam { 1, 0x46, 148 }, /* 2572 18 */ 90185377Ssam { 1, 0x46, 152 }, /* 2592 19 */ 91185377Ssam { 1, 0x46, 156 }, /* 2612 20 */ 92185377Ssam { 1, 0x46, 160 }, /* 2632 21 */ 93185377Ssam { 1, 0x46, 164 }, /* 2652 22 */ 94185377Ssam { 1, 0x46, 168 }, /* 2672 23 */ 95185377Ssam { 1, 0x46, 172 }, /* 2692 24 */ 96185377Ssam { 1, 0x46, 176 }, /* 2712 25 */ 97185377Ssam { 1, 0x46, 180 } /* 2732 26 */ 98185377Ssam}; 99185377Ssam 100185377Ssam/* Power timeouts in usec to wait for chip to wake-up. */ 101185377Ssam#define POWER_UP_TIME 2000 102185377Ssam 103185377Ssam#define DELAY_PLL_SETTLE 300 /* 300 us */ 104185377Ssam#define DELAY_BASE_ACTIVATE 100 /* 100 us */ 105185377Ssam 106185377Ssam#define NUM_RATES 8 107185377Ssam 108185377Ssamstatic HAL_BOOL ar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask); 109185377Ssamstatic HAL_BOOL ar5211SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 110185377Ssamstatic int16_t ar5211RunNoiseFloor(struct ath_hal *, 111185377Ssam uint8_t runTime, int16_t startingNF); 112185377Ssamstatic HAL_BOOL ar5211IsNfGood(struct ath_hal *, HAL_CHANNEL_INTERNAL *chan); 113185377Ssamstatic HAL_BOOL ar5211SetRf6and7(struct ath_hal *, HAL_CHANNEL *chan); 114185377Ssamstatic HAL_BOOL ar5211SetBoardValues(struct ath_hal *, HAL_CHANNEL *chan); 115185377Ssamstatic void ar5211SetPowerTable(struct ath_hal *, 116185377Ssam PCDACS_EEPROM *pSrcStruct, uint16_t channel); 117185377Ssamstatic void ar5211SetRateTable(struct ath_hal *, 118185377Ssam RD_EDGES_POWER *pRdEdgesPower, TRGT_POWER_INFO *pPowerInfo, 119185377Ssam uint16_t numChannels, HAL_CHANNEL *chan); 120185377Ssamstatic uint16_t ar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, 121185377Ssam const PCDACS_EEPROM *pSrcStruct); 122185377Ssamstatic HAL_BOOL ar5211FindValueInList(uint16_t channel, uint16_t pcdacValue, 123185377Ssam const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue); 124185377Ssamstatic uint16_t ar5211GetInterpolatedValue(uint16_t target, 125185377Ssam uint16_t srcLeft, uint16_t srcRight, 126185377Ssam uint16_t targetLeft, uint16_t targetRight, HAL_BOOL scaleUp); 127185377Ssamstatic void ar5211GetLowerUpperValues(uint16_t value, 128185377Ssam const uint16_t *pList, uint16_t listSize, 129185377Ssam uint16_t *pLowerValue, uint16_t *pUpperValue); 130185377Ssamstatic void ar5211GetLowerUpperPcdacs(uint16_t pcdac, 131185377Ssam uint16_t channel, const PCDACS_EEPROM *pSrcStruct, 132185377Ssam uint16_t *pLowerPcdac, uint16_t *pUpperPcdac); 133185377Ssam 134185377Ssamstatic void ar5211SetRfgain(struct ath_hal *, const GAIN_VALUES *);; 135185377Ssamstatic void ar5211RequestRfgain(struct ath_hal *); 136185377Ssamstatic HAL_BOOL ar5211InvalidGainReadback(struct ath_hal *, GAIN_VALUES *); 137185377Ssamstatic HAL_BOOL ar5211IsGainAdjustNeeded(struct ath_hal *, const GAIN_VALUES *); 138185377Ssamstatic int32_t ar5211AdjustGain(struct ath_hal *, GAIN_VALUES *); 139185377Ssamstatic void ar5211SetOperatingMode(struct ath_hal *, int opmode); 140185377Ssam 141185377Ssam/* 142185377Ssam * Places the device in and out of reset and then places sane 143185377Ssam * values in the registers based on EEPROM config, initialization 144185377Ssam * vectors (as determined by the mode), and station configuration 145185377Ssam * 146185377Ssam * bChannelChange is used to preserve DMA/PCU registers across 147185377Ssam * a HW Reset during channel change. 148185377Ssam */ 149185377SsamHAL_BOOL 150185377Ssamar5211Reset(struct ath_hal *ah, HAL_OPMODE opmode, 151185377Ssam HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status) 152185377Ssam{ 153185377Ssamuint32_t softLedCfg, softLedState; 154185377Ssam#define N(a) (sizeof (a) /sizeof (a[0])) 155185377Ssam#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 156185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 157185377Ssam HAL_CHANNEL_INTERNAL *ichan; 158185377Ssam uint32_t i, ledstate; 159185377Ssam HAL_STATUS ecode; 160185377Ssam int q; 161185377Ssam 162185377Ssam uint32_t data, synthDelay; 163185377Ssam uint32_t macStaId1; 164185377Ssam uint16_t modesIndex = 0, freqIndex = 0; 165185377Ssam uint32_t saveFrameSeqCount[AR_NUM_DCU]; 166185377Ssam uint32_t saveTsfLow = 0, saveTsfHigh = 0; 167185377Ssam uint32_t saveDefAntenna; 168185377Ssam 169185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 170185377Ssam "%s: opmode %u channel %u/0x%x %s channel\n", 171185377Ssam __func__, opmode, chan->channel, chan->channelFlags, 172185377Ssam bChannelChange ? "change" : "same"); 173185377Ssam 174185377Ssam OS_MARK(ah, AH_MARK_RESET, bChannelChange); 175185377Ssam#define IS(_c,_f) (((_c)->channelFlags & _f) || 0) 176185377Ssam if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan,CHANNEL_5GHZ)) == 0) { 177185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 178185377Ssam "%s: invalid channel %u/0x%x; not marked as 2GHz or 5GHz\n", 179185377Ssam __func__, chan->channel, chan->channelFlags); 180185377Ssam FAIL(HAL_EINVAL); 181185377Ssam } 182185377Ssam if ((IS(chan, CHANNEL_OFDM) ^ IS(chan, CHANNEL_CCK)) == 0) { 183185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 184185377Ssam "%s: invalid channel %u/0x%x; not marked as OFDM or CCK\n", 185185377Ssam __func__, chan->channel, chan->channelFlags); 186185377Ssam FAIL(HAL_EINVAL); 187185377Ssam } 188185377Ssam#undef IS 189185377Ssam /* 190185377Ssam * Map public channel to private. 191185377Ssam */ 192185377Ssam ichan = ath_hal_checkchannel(ah, chan); 193185377Ssam if (ichan == AH_NULL) { 194185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 195185377Ssam "%s: invalid channel %u/0x%x; no mapping\n", 196185377Ssam __func__, chan->channel, chan->channelFlags); 197185377Ssam FAIL(HAL_EINVAL); 198185377Ssam } 199185377Ssam switch (opmode) { 200185377Ssam case HAL_M_STA: 201185377Ssam case HAL_M_IBSS: 202185377Ssam case HAL_M_HOSTAP: 203185377Ssam case HAL_M_MONITOR: 204185377Ssam break; 205185377Ssam default: 206185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 207185377Ssam "%s: invalid operating mode %u\n", __func__, opmode); 208185377Ssam FAIL(HAL_EINVAL); 209185377Ssam break; 210185377Ssam } 211185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 212185377Ssam 213185377Ssam /* Preserve certain DMA hardware registers on a channel change */ 214185377Ssam if (bChannelChange) { 215185377Ssam /* 216185377Ssam * Need to save/restore the TSF because of an issue 217185377Ssam * that accelerates the TSF during a chip reset. 218185377Ssam * 219185377Ssam * We could use system timer routines to more 220185377Ssam * accurately restore the TSF, but 221185377Ssam * 1. Timer routines on certain platforms are 222185377Ssam * not accurate enough (e.g. 1 ms resolution). 223185377Ssam * 2. It would still not be accurate. 224185377Ssam * 225185377Ssam * The most important aspect of this solution, 226185377Ssam * is that, after reset, the TSF is behind 227185377Ssam * other STAs TSFs. This will allow the STA to 228185377Ssam * properly resynchronize its TSF in adhoc mode. 229185377Ssam */ 230185377Ssam saveTsfLow = OS_REG_READ(ah, AR_TSF_L32); 231185377Ssam saveTsfHigh = OS_REG_READ(ah, AR_TSF_U32); 232185377Ssam 233185377Ssam /* Read frame sequence count */ 234185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 235185377Ssam saveFrameSeqCount[0] = OS_REG_READ(ah, AR_D0_SEQNUM); 236185377Ssam } else { 237185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 238185377Ssam saveFrameSeqCount[i] = OS_REG_READ(ah, AR_DSEQNUM(i)); 239185377Ssam } 240185377Ssam if (!(ichan->privFlags & CHANNEL_DFS)) 241185377Ssam ichan->privFlags &= ~CHANNEL_INTERFERENCE; 242185377Ssam chan->channelFlags = ichan->channelFlags; 243185377Ssam chan->privFlags = ichan->privFlags; 244185377Ssam } 245185377Ssam 246185377Ssam /* 247185377Ssam * Preserve the antenna on a channel change 248185377Ssam */ 249185377Ssam saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 250185377Ssam if (saveDefAntenna == 0) 251185377Ssam saveDefAntenna = 1; 252185377Ssam 253185377Ssam /* Save hardware flag before chip reset clears the register */ 254185377Ssam macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 255185377Ssam 256185377Ssam /* Save led state from pci config register */ 257185377Ssam ledstate = OS_REG_READ(ah, AR_PCICFG) & 258185377Ssam (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 259185377Ssam AR_PCICFG_LEDSLOW); 260185377Ssam softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 261185377Ssam softLedState = OS_REG_READ(ah, AR_GPIODO); 262185377Ssam 263185377Ssam if (!ar5211ChipReset(ah, chan->channelFlags)) { 264185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 265185377Ssam FAIL(HAL_EIO); 266185377Ssam } 267185377Ssam 268185377Ssam /* Setup the indices for the next set of register array writes */ 269185377Ssam switch (chan->channelFlags & CHANNEL_ALL) { 270185377Ssam case CHANNEL_A: 271185377Ssam modesIndex = 1; 272185377Ssam freqIndex = 1; 273185377Ssam break; 274185377Ssam case CHANNEL_T: 275185377Ssam modesIndex = 2; 276185377Ssam freqIndex = 1; 277185377Ssam break; 278185377Ssam case CHANNEL_B: 279185377Ssam modesIndex = 3; 280185377Ssam freqIndex = 2; 281185377Ssam break; 282185377Ssam case CHANNEL_PUREG: 283185377Ssam modesIndex = 4; 284185377Ssam freqIndex = 2; 285185377Ssam break; 286185377Ssam default: 287185377Ssam /* Ah, a new wireless mode */ 288185377Ssam HALASSERT(0); 289185377Ssam break; 290185377Ssam } 291185377Ssam 292185377Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 293185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 294185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); 295185377Ssam } else { 296185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); 297185377Ssam } 298185377Ssam 299185377Ssam /* Write parameters specific to AR5211 */ 300185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 301185377Ssam if (IS_CHAN_2GHZ(chan) && 302185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) { 303185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 304185377Ssam uint32_t ob2GHz, db2GHz; 305185377Ssam 306185377Ssam if (IS_CHAN_CCK(chan)) { 307185377Ssam ob2GHz = ee->ee_ob2GHz[0]; 308185377Ssam db2GHz = ee->ee_db2GHz[0]; 309185377Ssam } else { 310185377Ssam ob2GHz = ee->ee_ob2GHz[1]; 311185377Ssam db2GHz = ee->ee_db2GHz[1]; 312185377Ssam } 313185377Ssam ob2GHz = ath_hal_reverseBits(ob2GHz, 3); 314185377Ssam db2GHz = ath_hal_reverseBits(db2GHz, 3); 315185377Ssam ar5211Mode2_4[25][freqIndex] = 316185377Ssam (ar5211Mode2_4[25][freqIndex] & ~0xC0) | 317185377Ssam ((ob2GHz << 6) & 0xC0); 318185377Ssam ar5211Mode2_4[26][freqIndex] = 319185377Ssam (ar5211Mode2_4[26][freqIndex] & ~0x0F) | 320185377Ssam (((ob2GHz >> 2) & 0x1) | 321185377Ssam ((db2GHz << 1) & 0x0E)); 322185377Ssam } 323185377Ssam for (i = 0; i < N(ar5211Mode2_4); i++) 324185377Ssam OS_REG_WRITE(ah, ar5211Mode2_4[i][0], 325185377Ssam ar5211Mode2_4[i][freqIndex]); 326185377Ssam } 327185377Ssam 328185377Ssam /* Write the analog registers 6 and 7 before other config */ 329185377Ssam ar5211SetRf6and7(ah, chan); 330185377Ssam 331185377Ssam /* Write registers that vary across all modes */ 332185377Ssam for (i = 0; i < N(ar5211Modes); i++) 333185377Ssam OS_REG_WRITE(ah, ar5211Modes[i][0], ar5211Modes[i][modesIndex]); 334185377Ssam 335185377Ssam /* Write RFGain Parameters that differ between 2.4 and 5 GHz */ 336185377Ssam for (i = 0; i < N(ar5211BB_RfGain); i++) 337185377Ssam OS_REG_WRITE(ah, ar5211BB_RfGain[i][0], ar5211BB_RfGain[i][freqIndex]); 338185377Ssam 339185377Ssam /* Write Common Array Parameters */ 340185377Ssam for (i = 0; i < N(ar5211Common); i++) { 341185377Ssam uint32_t reg = ar5211Common[i][0]; 342185377Ssam /* On channel change, don't reset the PCU registers */ 343185377Ssam if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000))) 344185377Ssam OS_REG_WRITE(ah, reg, ar5211Common[i][1]); 345185377Ssam } 346185377Ssam 347185377Ssam /* Fix pre-AR5211 register values, this includes AR5311s. */ 348185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) { 349185377Ssam /* 350185377Ssam * The TX and RX latency values have changed locations 351185377Ssam * within the USEC register in AR5211. Since they're 352185377Ssam * set via the .ini, for both AR5211 and AR5311, they 353185377Ssam * are written properly here for AR5311. 354185377Ssam */ 355185377Ssam data = OS_REG_READ(ah, AR_USEC); 356185377Ssam /* Must be 0 for proper write in AR5311 */ 357185377Ssam HALASSERT((data & 0x00700000) == 0); 358185377Ssam OS_REG_WRITE(ah, AR_USEC, 359185377Ssam (data & (AR_USEC_M | AR_USEC_32_M | AR5311_USEC_TX_LAT_M)) | 360185377Ssam ((29 << AR5311_USEC_RX_LAT_S) & AR5311_USEC_RX_LAT_M)); 361185377Ssam /* The following registers exist only on AR5311. */ 362185377Ssam OS_REG_WRITE(ah, AR5311_QDCLKGATE, 0); 363185377Ssam 364185377Ssam /* Set proper ADC & DAC delays for AR5311. */ 365185377Ssam OS_REG_WRITE(ah, 0x00009878, 0x00000008); 366185377Ssam 367185377Ssam /* Enable the PCU FIFO corruption ECO on AR5311. */ 368185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, 369185377Ssam OS_REG_READ(ah, AR_DIAG_SW) | AR5311_DIAG_SW_USE_ECO); 370185377Ssam } 371185377Ssam 372185377Ssam /* Restore certain DMA hardware registers on a channel change */ 373185377Ssam if (bChannelChange) { 374185377Ssam /* Restore TSF */ 375185377Ssam OS_REG_WRITE(ah, AR_TSF_L32, saveTsfLow); 376185377Ssam OS_REG_WRITE(ah, AR_TSF_U32, saveTsfHigh); 377185377Ssam 378185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_OAHU) { 379185377Ssam OS_REG_WRITE(ah, AR_D0_SEQNUM, saveFrameSeqCount[0]); 380185377Ssam } else { 381185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 382185377Ssam OS_REG_WRITE(ah, AR_DSEQNUM(i), saveFrameSeqCount[i]); 383185377Ssam } 384185377Ssam } 385185377Ssam 386185377Ssam OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 387185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 388185377Ssam | macStaId1 389185377Ssam ); 390185377Ssam ar5211SetOperatingMode(ah, opmode); 391185377Ssam 392185377Ssam /* Restore previous led state */ 393185377Ssam OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate); 394185377Ssam OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 395185377Ssam OS_REG_WRITE(ah, AR_GPIODO, softLedState); 396185377Ssam 397185377Ssam /* Restore previous antenna */ 398185377Ssam OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 399185377Ssam 400185377Ssam OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 401185377Ssam OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 402185377Ssam 403185377Ssam /* Restore bmiss rssi & count thresholds */ 404185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 405185377Ssam 406185377Ssam OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 407185377Ssam 408185377Ssam /* 409185377Ssam * for pre-Production Oahu only. 410185377Ssam * Disable clock gating in all DMA blocks. Helps when using 411185377Ssam * 11B and AES. This will result in higher power consumption. 412185377Ssam */ 413185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_OAHU && 414185377Ssam AH_PRIVATE(ah)->ah_macRev < AR_SREV_OAHU_PROD) { 415185377Ssam OS_REG_WRITE(ah, AR_CFG, 416185377Ssam OS_REG_READ(ah, AR_CFG) | AR_CFG_CLK_GATE_DIS); 417185377Ssam } 418185377Ssam 419185377Ssam /* Setup the transmit power values. */ 420185377Ssam if (!ar5211SetTransmitPower(ah, chan)) { 421185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 422185377Ssam "%s: error init'ing transmit power\n", __func__); 423185377Ssam FAIL(HAL_EIO); 424185377Ssam } 425185377Ssam 426185377Ssam /* 427185377Ssam * Configurable OFDM spoofing for 11n compatibility; used 428185377Ssam * only when operating in station mode. 429185377Ssam */ 430185377Ssam if (opmode != HAL_M_HOSTAP && 431185377Ssam (AH_PRIVATE(ah)->ah_11nCompat & HAL_DIAG_11N_SERVICES) != 0) { 432185377Ssam /* NB: override the .ini setting */ 433185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 434185377Ssam AR_PHY_FRAME_CTL_ERR_SERV, 435185377Ssam MS(AH_PRIVATE(ah)->ah_11nCompat, HAL_DIAG_11N_SERVICES)&1); 436185377Ssam } 437185377Ssam 438185377Ssam /* Setup board specific options for EEPROM version 3 */ 439185377Ssam ar5211SetBoardValues(ah, chan); 440185377Ssam 441185377Ssam if (!ar5211SetChannel(ah, ichan)) { 442185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n", 443185377Ssam __func__); 444185377Ssam FAIL(HAL_EIO); 445185377Ssam } 446185377Ssam 447185377Ssam /* Activate the PHY */ 448185377Ssam if (AH_PRIVATE(ah)->ah_devid == AR5211_FPGA11B && IS_CHAN_2GHZ(chan)) 449185377Ssam OS_REG_WRITE(ah, 0xd808, 0x502); /* required for FPGA */ 450185377Ssam OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 451185377Ssam 452185377Ssam /* 453185377Ssam * Wait for the frequency synth to settle (synth goes on 454185377Ssam * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 455185377Ssam * Value is in 100ns increments. 456185377Ssam */ 457185377Ssam data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_M; 458185377Ssam if (IS_CHAN_CCK(chan)) { 459185377Ssam synthDelay = (4 * data) / 22; 460185377Ssam } else { 461185377Ssam synthDelay = data / 10; 462185377Ssam } 463185377Ssam /* 464185377Ssam * There is an issue if the AP starts the calibration before 465185377Ssam * the baseband timeout completes. This could result in the 466185377Ssam * rxclear false triggering. Add an extra delay to ensure this 467185377Ssam * this does not happen. 468185377Ssam */ 469185377Ssam OS_DELAY(synthDelay + DELAY_BASE_ACTIVATE); 470185377Ssam 471185377Ssam /* Calibrate the AGC and wait for completion. */ 472185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 473185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); 474185377Ssam (void) ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0); 475185377Ssam 476185377Ssam /* Perform noise floor and set status */ 477185377Ssam if (!ar5211CalNoiseFloor(ah, ichan)) { 478185377Ssam if (!IS_CHAN_CCK(chan)) 479185377Ssam chan->channelFlags |= CHANNEL_CW_INT; 480185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 481185377Ssam "%s: noise floor calibration failed\n", __func__); 482185377Ssam FAIL(HAL_EIO); 483185377Ssam } 484185377Ssam 485185377Ssam /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 486185377Ssam if (ahp->ah_calibrationTime != 0) { 487185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, 488185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL | (INIT_IQCAL_LOG_COUNT_MAX << AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S)); 489185377Ssam ahp->ah_bIQCalibration = AH_TRUE; 490185377Ssam } 491185377Ssam 492185377Ssam /* set 1:1 QCU to DCU mapping for all queues */ 493185377Ssam for (q = 0; q < AR_NUM_DCU; q++) 494185377Ssam OS_REG_WRITE(ah, AR_DQCUMASK(q), 1<<q); 495185377Ssam 496185377Ssam for (q = 0; q < HAL_NUM_TX_QUEUES; q++) 497185377Ssam ar5211ResetTxQueue(ah, q); 498185377Ssam 499185377Ssam /* Setup QCU0 transmit interrupt masks (TX_ERR, TX_OK, TX_DESC, TX_URN) */ 500185377Ssam OS_REG_WRITE(ah, AR_IMR_S0, 501185377Ssam (AR_IMR_S0_QCU_TXOK & AR_QCU_0) | 502185377Ssam (AR_IMR_S0_QCU_TXDESC & (AR_QCU_0<<AR_IMR_S0_QCU_TXDESC_S))); 503185377Ssam OS_REG_WRITE(ah, AR_IMR_S1, (AR_IMR_S1_QCU_TXERR & AR_QCU_0)); 504185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, (AR_IMR_S2_QCU_TXURN & AR_QCU_0)); 505185377Ssam 506185377Ssam /* 507185377Ssam * GBL_EIFS must always be written after writing 508185377Ssam * to any QCUMASK register. 509185377Ssam */ 510185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, OS_REG_READ(ah, AR_D_GBL_IFS_EIFS)); 511185377Ssam 512185377Ssam /* Now set up the Interrupt Mask Register and save it for future use */ 513185377Ssam OS_REG_WRITE(ah, AR_IMR, INIT_INTERRUPT_MASK); 514185377Ssam ahp->ah_maskReg = INIT_INTERRUPT_MASK; 515185377Ssam 516185377Ssam /* Enable bus error interrupts */ 517185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | 518185377Ssam AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 519185377Ssam 520185377Ssam /* Enable interrupts specific to AP */ 521185377Ssam if (opmode == HAL_M_HOSTAP) { 522185377Ssam OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_MIB); 523185377Ssam ahp->ah_maskReg |= AR_IMR_MIB; 524185377Ssam } 525185377Ssam 526185377Ssam if (AH_PRIVATE(ah)->ah_rfkillEnabled) 527185377Ssam ar5211EnableRfKill(ah); 528185377Ssam 529185377Ssam /* 530185377Ssam * Writing to AR_BEACON will start timers. Hence it should 531185377Ssam * be the last register to be written. Do not reset tsf, do 532185377Ssam * not enable beacons at this point, but preserve other values 533185377Ssam * like beaconInterval. 534185377Ssam */ 535185377Ssam OS_REG_WRITE(ah, AR_BEACON, 536185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 537185377Ssam 538185377Ssam /* Restore user-specified slot time and timeouts */ 539185377Ssam if (ahp->ah_sifstime != (u_int) -1) 540185377Ssam ar5211SetSifsTime(ah, ahp->ah_sifstime); 541185377Ssam if (ahp->ah_slottime != (u_int) -1) 542185377Ssam ar5211SetSlotTime(ah, ahp->ah_slottime); 543185377Ssam if (ahp->ah_acktimeout != (u_int) -1) 544185377Ssam ar5211SetAckTimeout(ah, ahp->ah_acktimeout); 545185377Ssam if (ahp->ah_ctstimeout != (u_int) -1) 546185377Ssam ar5211SetCTSTimeout(ah, ahp->ah_ctstimeout); 547185377Ssam if (AH_PRIVATE(ah)->ah_diagreg != 0) 548185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 549185377Ssam 550185377Ssam AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 551185377Ssam 552185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 553185377Ssam 554185377Ssam return AH_TRUE; 555185377Ssambad: 556185377Ssam if (*status) 557185377Ssam *status = ecode; 558185377Ssam return AH_FALSE; 559185377Ssam#undef FAIL 560185377Ssam#undef N 561185377Ssam} 562185377Ssam 563185377Ssam/* 564185377Ssam * Places the PHY and Radio chips into reset. A full reset 565185377Ssam * must be called to leave this state. The PCI/MAC/PCU are 566185377Ssam * not placed into reset as we must receive interrupt to 567185377Ssam * re-enable the hardware. 568185377Ssam */ 569185377SsamHAL_BOOL 570185377Ssamar5211PhyDisable(struct ath_hal *ah) 571185377Ssam{ 572185377Ssam return ar5211SetResetReg(ah, AR_RC_BB); 573185377Ssam} 574185377Ssam 575185377Ssam/* 576185377Ssam * Places all of hardware into reset 577185377Ssam */ 578185377SsamHAL_BOOL 579185377Ssamar5211Disable(struct ath_hal *ah) 580185377Ssam{ 581185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 582185377Ssam return AH_FALSE; 583185377Ssam /* 584185377Ssam * Reset the HW - PCI must be reset after the rest of the 585185377Ssam * device has been reset. 586185377Ssam */ 587185377Ssam if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 588185377Ssam return AH_FALSE; 589185377Ssam OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 590185377Ssam 591185377Ssam return AH_TRUE; 592185377Ssam} 593185377Ssam 594185377Ssam/* 595185377Ssam * Places the hardware into reset and then pulls it out of reset 596185377Ssam * 597185377Ssam * Only write the PLL if we're changing to or from CCK mode 598185377Ssam * 599185377Ssam * Attach calls with channelFlags = 0, as the coldreset should have 600185377Ssam * us in the correct mode and we cannot check the hwchannel flags. 601185377Ssam */ 602185377SsamHAL_BOOL 603185377Ssamar5211ChipReset(struct ath_hal *ah, uint16_t channelFlags) 604185377Ssam{ 605185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 606185377Ssam return AH_FALSE; 607185377Ssam 608185377Ssam /* Set CCK and Turbo modes correctly */ 609185377Ssam switch (channelFlags & CHANNEL_ALL) { 610185377Ssam case CHANNEL_2GHZ|CHANNEL_CCK: 611185377Ssam case CHANNEL_2GHZ|CHANNEL_CCK|CHANNEL_TURBO: 612185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, 0); 613185377Ssam OS_REG_WRITE(ah, AR5211_PHY_MODE, 614185377Ssam AR5211_PHY_MODE_CCK | AR5211_PHY_MODE_RF2GHZ); 615185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_44); 616185377Ssam /* Wait for the PLL to settle */ 617185377Ssam OS_DELAY(DELAY_PLL_SETTLE); 618185377Ssam break; 619185377Ssam case CHANNEL_2GHZ|CHANNEL_OFDM: 620185377Ssam case CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO: 621185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, 0); 622185377Ssam if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) { 623185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40); 624185377Ssam OS_DELAY(DELAY_PLL_SETTLE); 625185377Ssam OS_REG_WRITE(ah, AR5211_PHY_MODE, 626185377Ssam AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF2GHZ); 627185377Ssam } 628185377Ssam break; 629185377Ssam case CHANNEL_A: 630185377Ssam case CHANNEL_T: 631185377Ssam if (channelFlags & CHANNEL_TURBO) { 632185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, 633185377Ssam AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT); 634185377Ssam } else { /* 5 GHZ OFDM Mode */ 635185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, 0); 636185377Ssam } 637185377Ssam if (AH_PRIVATE(ah)->ah_devid == AR5211_DEVID) { 638185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, AR_PHY_PLL_CTL_40); 639185377Ssam OS_DELAY(DELAY_PLL_SETTLE); 640185377Ssam OS_REG_WRITE(ah, AR5211_PHY_MODE, 641185377Ssam AR5211_PHY_MODE_OFDM | AR5211_PHY_MODE_RF5GHZ); 642185377Ssam } 643185377Ssam break; 644185377Ssam } 645185377Ssam /* NB: else no flags set - must be attach calling - do nothing */ 646185377Ssam 647185377Ssam /* 648185377Ssam * Reset the HW - PCI must be reset after the rest of the 649185377Ssam * device has been reset 650185377Ssam */ 651185377Ssam if (!ar5211SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 652185377Ssam return AH_FALSE; 653185377Ssam OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */ 654185377Ssam 655185377Ssam /* Bring out of sleep mode (AGAIN) */ 656185377Ssam if (!ar5211SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 657185377Ssam return AH_FALSE; 658185377Ssam 659185377Ssam /* Clear warm reset register */ 660185377Ssam return ar5211SetResetReg(ah, 0); 661185377Ssam} 662185377Ssam 663185377Ssam/* 664185377Ssam * Recalibrate the lower PHY chips to account for temperature/environment 665185377Ssam * changes. 666185377Ssam */ 667185377SsamHAL_BOOL 668185377Ssamar5211PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, HAL_BOOL *isIQdone) 669185377Ssam{ 670185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 671185377Ssam HAL_CHANNEL_INTERNAL *ichan; 672185377Ssam int32_t qCoff, qCoffDenom; 673185377Ssam uint32_t data; 674185377Ssam int32_t iqCorrMeas; 675185377Ssam int32_t iCoff, iCoffDenom; 676185377Ssam uint32_t powerMeasQ, powerMeasI; 677185377Ssam 678185377Ssam ichan = ath_hal_checkchannel(ah, chan); 679185377Ssam if (ichan == AH_NULL) { 680185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 681185377Ssam "%s: invalid channel %u/0x%x; no mapping\n", 682185377Ssam __func__, chan->channel, chan->channelFlags); 683185377Ssam return AH_FALSE; 684185377Ssam } 685185377Ssam /* IQ calibration in progress. Check to see if it has finished. */ 686185377Ssam if (ahp->ah_bIQCalibration && 687185377Ssam !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 688185377Ssam /* IQ Calibration has finished. */ 689185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 690185377Ssam 691185377Ssam /* Read calibration results. */ 692185377Ssam powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 693185377Ssam powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 694185377Ssam iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 695185377Ssam 696185377Ssam /* 697185377Ssam * Prescale these values to remove 64-bit operation requirement at the loss 698185377Ssam * of a little precision. 699185377Ssam */ 700185377Ssam iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 701185377Ssam qCoffDenom = powerMeasQ / 64; 702185377Ssam 703185377Ssam /* Protect against divide-by-0. */ 704185377Ssam if (iCoffDenom != 0 && qCoffDenom != 0) { 705185377Ssam iCoff = (-iqCorrMeas) / iCoffDenom; 706185377Ssam /* IQCORR_Q_I_COFF is a signed 6 bit number */ 707185377Ssam iCoff = iCoff & 0x3f; 708185377Ssam 709185377Ssam qCoff = ((int32_t)powerMeasI / qCoffDenom) - 64; 710185377Ssam /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 711185377Ssam qCoff = qCoff & 0x1f; 712185377Ssam 713185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasI = 0x%08x\n", 714185377Ssam powerMeasI); 715185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "powerMeasQ = 0x%08x\n", 716185377Ssam powerMeasQ); 717185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "iqCorrMeas = 0x%08x\n", 718185377Ssam iqCorrMeas); 719185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "iCoff = %d\n", 720185377Ssam iCoff); 721185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, "qCoff = %d\n", 722185377Ssam qCoff); 723185377Ssam 724185377Ssam /* Write IQ */ 725185377Ssam data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | 726185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE | 727185377Ssam (((uint32_t)iCoff) << AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S) | 728185377Ssam ((uint32_t)qCoff); 729185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data); 730185377Ssam } 731185377Ssam } 732185377Ssam 733185377Ssam /* Perform noise floor and set status */ 734185377Ssam if (!ar5211IsNfGood(ah, ichan)) { 735185377Ssam /* report up and clear internal state */ 736185377Ssam chan->channelFlags |= CHANNEL_CW_INT; 737185377Ssam ichan->channelFlags &= ~CHANNEL_CW_INT; 738185377Ssam return AH_FALSE; 739185377Ssam } 740185377Ssam if (!ar5211CalNoiseFloor(ah, ichan)) { 741185377Ssam /* 742185377Ssam * Delay 5ms before retrying the noise floor 743185377Ssam * just to make sure, as we are in an error 744185377Ssam * condition here. 745185377Ssam */ 746185377Ssam OS_DELAY(5000); 747185377Ssam if (!ar5211CalNoiseFloor(ah, ichan)) { 748185377Ssam if (!IS_CHAN_CCK(chan)) 749185377Ssam chan->channelFlags |= CHANNEL_CW_INT; 750185377Ssam return AH_FALSE; 751185377Ssam } 752185377Ssam } 753185377Ssam 754185377Ssam ar5211RequestRfgain(ah); 755185377Ssam *isIQdone = !ahp->ah_bIQCalibration; 756185377Ssam 757185377Ssam return AH_TRUE; 758185377Ssam} 759185377Ssam 760185377Ssam/* 761185377Ssam * Writes the given reset bit mask into the reset register 762185377Ssam */ 763185377Ssamstatic HAL_BOOL 764185377Ssamar5211SetResetReg(struct ath_hal *ah, uint32_t resetMask) 765185377Ssam{ 766185377Ssam uint32_t mask = resetMask ? resetMask : ~0; 767185377Ssam HAL_BOOL rt; 768185377Ssam 769185377Ssam (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 770185377Ssam OS_REG_WRITE(ah, AR_RC, resetMask); 771185377Ssam 772185377Ssam /* need to wait at least 128 clocks when reseting PCI before read */ 773185377Ssam OS_DELAY(15); 774185377Ssam 775185377Ssam resetMask &= AR_RC_MAC | AR_RC_BB; 776185377Ssam mask &= AR_RC_MAC | AR_RC_BB; 777185377Ssam rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 778185377Ssam if ((resetMask & AR_RC_MAC) == 0) { 779185377Ssam if (isBigEndian()) { 780185377Ssam /* 781185377Ssam * Set CFG, little-endian for register 782185377Ssam * and descriptor accesses. 783185377Ssam */ 784185377Ssam mask = INIT_CONFIG_STATUS | 785185377Ssam AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG; 786185377Ssam OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 787185377Ssam } else 788185377Ssam OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 789185377Ssam } 790185377Ssam return rt; 791185377Ssam} 792185377Ssam 793185377Ssam/* 794185377Ssam * Takes the MHz channel value and sets the Channel value 795185377Ssam * 796185377Ssam * ASSUMES: Writes enabled to analog bus before AGC is active 797185377Ssam * or by disabling the AGC. 798185377Ssam */ 799185377Ssamstatic HAL_BOOL 800185377Ssamar5211SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 801185377Ssam{ 802185377Ssam uint32_t refClk, reg32, data2111; 803185377Ssam int16_t chan5111, chanIEEE; 804185377Ssam 805185377Ssam chanIEEE = ath_hal_mhz2ieee(ah, chan->channel, chan->channelFlags); 806185377Ssam if (IS_CHAN_2GHZ(chan)) { 807185377Ssam const CHAN_INFO_2GHZ* ci = 808185377Ssam &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION]; 809185377Ssam 810185377Ssam data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff) 811185377Ssam << 5) 812185377Ssam | (ci->refClkSel << 4); 813185377Ssam chan5111 = ci->channel5111; 814185377Ssam } else { 815185377Ssam data2111 = 0; 816185377Ssam chan5111 = chanIEEE; 817185377Ssam } 818185377Ssam 819185377Ssam /* Rest of the code is common for 5 GHz and 2.4 GHz. */ 820185377Ssam if (chan5111 >= 145 || (chan5111 & 0x1)) { 821185377Ssam reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xFF; 822185377Ssam refClk = 1; 823185377Ssam } else { 824185377Ssam reg32 = ath_hal_reverseBits(((chan5111 - 24) / 2), 8) & 0xFF; 825185377Ssam refClk = 0; 826185377Ssam } 827185377Ssam 828185377Ssam reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1; 829185377Ssam OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff)); 830185377Ssam reg32 >>= 8; 831185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff)); 832185377Ssam 833185377Ssam AH_PRIVATE(ah)->ah_curchan = chan; 834185377Ssam return AH_TRUE; 835185377Ssam} 836185377Ssam 837185377Ssamstatic int16_t 838185377Ssamar5211GetNoiseFloor(struct ath_hal *ah) 839185377Ssam{ 840185377Ssam int16_t nf; 841185377Ssam 842185377Ssam nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 843185377Ssam if (nf & 0x100) 844185377Ssam nf = 0 - ((nf ^ 0x1ff) + 1); 845185377Ssam return nf; 846185377Ssam} 847185377Ssam 848185377Ssam/* 849185377Ssam * Peform the noisefloor calibration for the length of time set 850185377Ssam * in runTime (valid values 1 to 7) 851185377Ssam * 852185377Ssam * Returns: The NF value at the end of the given time (or 0 for failure) 853185377Ssam */ 854185377Ssamint16_t 855185377Ssamar5211RunNoiseFloor(struct ath_hal *ah, uint8_t runTime, int16_t startingNF) 856185377Ssam{ 857185377Ssam int i, searchTime; 858185377Ssam 859185377Ssam HALASSERT(runTime <= 7); 860185377Ssam 861185377Ssam /* Setup noise floor run time and starting value */ 862185377Ssam OS_REG_WRITE(ah, AR_PHY(25), 863185377Ssam (OS_REG_READ(ah, AR_PHY(25)) & ~0xFFF) | 864185377Ssam ((runTime << 9) & 0xE00) | (startingNF & 0x1FF)); 865185377Ssam /* Calibrate the noise floor */ 866185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 867185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); 868185377Ssam 869185377Ssam /* Compute the required amount of searchTime needed to finish NF */ 870185377Ssam if (runTime == 0) { 871185377Ssam /* 8 search windows * 6.4us each */ 872185377Ssam searchTime = 8 * 7; 873185377Ssam } else { 874185377Ssam /* 512 * runtime search windows * 6.4us each */ 875185377Ssam searchTime = (runTime * 512) * 7; 876185377Ssam } 877185377Ssam 878185377Ssam /* 879185377Ssam * Do not read noise floor until it has been updated 880185377Ssam * 881185377Ssam * As a guesstimate - we may only get 1/60th the time on 882185377Ssam * the air to see search windows in a heavily congested 883185377Ssam * network (40 us every 2400 us of time) 884185377Ssam */ 885185377Ssam for (i = 0; i < 60; i++) { 886185377Ssam if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) 887185377Ssam break; 888185377Ssam OS_DELAY(searchTime); 889185377Ssam } 890185377Ssam if (i >= 60) { 891185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 892185377Ssam "NF with runTime %d failed to end on channel %d\n", 893185377Ssam runTime, AH_PRIVATE(ah)->ah_curchan->channel); 894185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 895185377Ssam " PHY NF Reg state: 0x%x\n", 896185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 897185377Ssam HALDEBUG(ah, HAL_DEBUG_NFCAL, 898185377Ssam " PHY Active Reg state: 0x%x\n", 899185377Ssam OS_REG_READ(ah, AR_PHY_ACTIVE)); 900185377Ssam return 0; 901185377Ssam } 902185377Ssam 903185377Ssam return ar5211GetNoiseFloor(ah); 904185377Ssam} 905185377Ssam 906185377Ssamstatic HAL_BOOL 907185377SsamgetNoiseFloorThresh(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, int16_t *nft) 908185377Ssam{ 909185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 910185377Ssam 911185377Ssam switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) { 912185377Ssam case CHANNEL_A: 913185377Ssam *nft = ee->ee_noiseFloorThresh[0]; 914185377Ssam break; 915185377Ssam case CHANNEL_CCK|CHANNEL_2GHZ: 916185377Ssam *nft = ee->ee_noiseFloorThresh[1]; 917185377Ssam break; 918185377Ssam case CHANNEL_OFDM|CHANNEL_2GHZ: 919185377Ssam *nft = ee->ee_noiseFloorThresh[2]; 920185377Ssam break; 921185377Ssam default: 922185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 923185377Ssam __func__, chan->channelFlags); 924185377Ssam return AH_FALSE; 925185377Ssam } 926185377Ssam return AH_TRUE; 927185377Ssam} 928185377Ssam 929185377Ssam/* 930185377Ssam * Read the NF and check it against the noise floor threshhold 931185377Ssam * 932185377Ssam * Returns: TRUE if the NF is good 933185377Ssam */ 934185377Ssamstatic HAL_BOOL 935185377Ssamar5211IsNfGood(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 936185377Ssam{ 937185377Ssam int16_t nf, nfThresh; 938185377Ssam 939185377Ssam if (!getNoiseFloorThresh(ah, chan, &nfThresh)) 940185377Ssam return AH_FALSE; 941185377Ssam if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) 942185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 943185377Ssam "%s: NF did not complete in calibration window\n", __func__); 944185377Ssam nf = ar5211GetNoiseFloor(ah); 945185377Ssam if (nf > nfThresh) { 946185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 947185377Ssam "%s: noise floor failed; detected %u, threshold %u\n", 948185377Ssam __func__, nf, nfThresh); 949185377Ssam /* 950185377Ssam * NB: Don't discriminate 2.4 vs 5Ghz, if this 951185377Ssam * happens it indicates a problem regardless 952185377Ssam * of the band. 953185377Ssam */ 954185377Ssam chan->channelFlags |= CHANNEL_CW_INT; 955185377Ssam } 956185377Ssam chan->rawNoiseFloor = nf; 957185377Ssam return (nf <= nfThresh); 958185377Ssam} 959185377Ssam 960185377Ssam/* 961185377Ssam * Peform the noisefloor calibration and check for any constant channel 962185377Ssam * interference. 963185377Ssam * 964185377Ssam * NOTE: preAR5211 have a lengthy carrier wave detection process - hence 965185377Ssam * it is if'ed for MKK regulatory domain only. 966185377Ssam * 967185377Ssam * Returns: TRUE for a successful noise floor calibration; else FALSE 968185377Ssam */ 969185377SsamHAL_BOOL 970185377Ssamar5211CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 971185377Ssam{ 972185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 973185377Ssam /* Check for Carrier Wave interference in MKK regulatory zone */ 974185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU && 975185377Ssam ath_hal_getnfcheckrequired(ah, (HAL_CHANNEL *) chan)) { 976185377Ssam static const uint8_t runtime[3] = { 0, 2, 7 }; 977185377Ssam int16_t nf, nfThresh; 978185377Ssam int i; 979185377Ssam 980185377Ssam if (!getNoiseFloorThresh(ah, chan, &nfThresh)) 981185377Ssam return AH_FALSE; 982185377Ssam /* 983185377Ssam * Run a quick noise floor that will hopefully 984185377Ssam * complete (decrease delay time). 985185377Ssam */ 986185377Ssam for (i = 0; i < N(runtime); i++) { 987185377Ssam nf = ar5211RunNoiseFloor(ah, runtime[i], 0); 988185377Ssam if (nf > nfThresh) { 989185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 990185377Ssam "%s: run failed with %u > threshold %u " 991185377Ssam "(runtime %u)\n", __func__, 992185377Ssam nf, nfThresh, runtime[i]); 993185377Ssam chan->rawNoiseFloor = 0; 994185377Ssam } else 995185377Ssam chan->rawNoiseFloor = nf; 996185377Ssam } 997185377Ssam return (i <= N(runtime)); 998185377Ssam } else { 999185377Ssam /* Calibrate the noise floor */ 1000185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 1001185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | 1002185377Ssam AR_PHY_AGC_CONTROL_NF); 1003185377Ssam } 1004185377Ssam return AH_TRUE; 1005185377Ssam#undef N 1006185377Ssam} 1007185377Ssam 1008185377Ssam/* 1009185377Ssam * Adjust NF based on statistical values for 5GHz frequencies. 1010185377Ssam */ 1011185377Ssamint16_t 1012185377Ssamar5211GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 1013185377Ssam{ 1014185377Ssam static const struct { 1015185377Ssam uint16_t freqLow; 1016185377Ssam int16_t adjust; 1017185377Ssam } adjust5111[] = { 1018185377Ssam { 5790, 11 }, /* NB: ordered high -> low */ 1019185377Ssam { 5730, 10 }, 1020185377Ssam { 5690, 9 }, 1021185377Ssam { 5660, 8 }, 1022185377Ssam { 5610, 7 }, 1023185377Ssam { 5530, 5 }, 1024185377Ssam { 5450, 4 }, 1025185377Ssam { 5379, 2 }, 1026185377Ssam { 5209, 0 }, /* XXX? bogus but doesn't matter */ 1027185377Ssam { 0, 1 }, 1028185377Ssam }; 1029185377Ssam int i; 1030185377Ssam 1031185377Ssam for (i = 0; c->channel <= adjust5111[i].freqLow; i++) 1032185377Ssam ; 1033185377Ssam /* NB: placeholder for 5111's less severe requirement */ 1034185377Ssam return adjust5111[i].adjust / 3; 1035185377Ssam} 1036185377Ssam 1037185377Ssam/* 1038185377Ssam * Reads EEPROM header info from device structure and programs 1039185377Ssam * analog registers 6 and 7 1040185377Ssam * 1041185377Ssam * REQUIRES: Access to the analog device 1042185377Ssam */ 1043185377Ssamstatic HAL_BOOL 1044185377Ssamar5211SetRf6and7(struct ath_hal *ah, HAL_CHANNEL *chan) 1045185377Ssam{ 1046185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 1047185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1048185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1049185377Ssam uint16_t rfXpdGain, rfPloSel, rfPwdXpd; 1050185377Ssam uint16_t tempOB, tempDB; 1051185377Ssam uint16_t freqIndex; 1052185377Ssam int i; 1053185377Ssam 1054185377Ssam freqIndex = (chan->channelFlags & CHANNEL_2GHZ) ? 2 : 1; 1055185377Ssam 1056185377Ssam /* 1057185377Ssam * TODO: This array mode correspondes with the index used 1058185377Ssam * during the read. 1059185377Ssam * For readability, this should be changed to an enum or #define 1060185377Ssam */ 1061185377Ssam switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) { 1062185377Ssam case CHANNEL_A: 1063185377Ssam if (chan->channel > 4000 && chan->channel < 5260) { 1064185377Ssam tempOB = ee->ee_ob1; 1065185377Ssam tempDB = ee->ee_db1; 1066185377Ssam } else if (chan->channel >= 5260 && chan->channel < 5500) { 1067185377Ssam tempOB = ee->ee_ob2; 1068185377Ssam tempDB = ee->ee_db2; 1069185377Ssam } else if (chan->channel >= 5500 && chan->channel < 5725) { 1070185377Ssam tempOB = ee->ee_ob3; 1071185377Ssam tempDB = ee->ee_db3; 1072185377Ssam } else if (chan->channel >= 5725) { 1073185377Ssam tempOB = ee->ee_ob4; 1074185377Ssam tempDB = ee->ee_db4; 1075185377Ssam } else { 1076185377Ssam /* XXX panic?? */ 1077185377Ssam tempOB = tempDB = 0; 1078185377Ssam } 1079185377Ssam 1080185377Ssam rfXpdGain = ee->ee_xgain[0]; 1081185377Ssam rfPloSel = ee->ee_xpd[0]; 1082185377Ssam rfPwdXpd = !ee->ee_xpd[0]; 1083185377Ssam 1084185377Ssam ar5211Rf6n7[5][freqIndex] = 1085185377Ssam (ar5211Rf6n7[5][freqIndex] & ~0x10000000) | 1086185377Ssam (ee->ee_cornerCal.pd84<< 28); 1087185377Ssam ar5211Rf6n7[6][freqIndex] = 1088185377Ssam (ar5211Rf6n7[6][freqIndex] & ~0x04000000) | 1089185377Ssam (ee->ee_cornerCal.pd90 << 26); 1090185377Ssam ar5211Rf6n7[21][freqIndex] = 1091185377Ssam (ar5211Rf6n7[21][freqIndex] & ~0x08) | 1092185377Ssam (ee->ee_cornerCal.gSel << 3); 1093185377Ssam break; 1094185377Ssam case CHANNEL_CCK|CHANNEL_2GHZ: 1095185377Ssam tempOB = ee->ee_obFor24; 1096185377Ssam tempDB = ee->ee_dbFor24; 1097185377Ssam rfXpdGain = ee->ee_xgain[1]; 1098185377Ssam rfPloSel = ee->ee_xpd[1]; 1099185377Ssam rfPwdXpd = !ee->ee_xpd[1]; 1100185377Ssam break; 1101185377Ssam case CHANNEL_OFDM|CHANNEL_2GHZ: 1102185377Ssam tempOB = ee->ee_obFor24g; 1103185377Ssam tempDB = ee->ee_dbFor24g; 1104185377Ssam rfXpdGain = ee->ee_xgain[2]; 1105185377Ssam rfPloSel = ee->ee_xpd[2]; 1106185377Ssam rfPwdXpd = !ee->ee_xpd[2]; 1107185377Ssam break; 1108185377Ssam default: 1109185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1110185377Ssam __func__, chan->channelFlags); 1111185377Ssam return AH_FALSE; 1112185377Ssam } 1113185377Ssam 1114185377Ssam HALASSERT(1 <= tempOB && tempOB <= 5); 1115185377Ssam HALASSERT(1 <= tempDB && tempDB <= 5); 1116185377Ssam 1117185377Ssam /* Set rfXpdGain and rfPwdXpd */ 1118185377Ssam ar5211Rf6n7[11][freqIndex] = (ar5211Rf6n7[11][freqIndex] & ~0xC0) | 1119185377Ssam (((ath_hal_reverseBits(rfXpdGain, 4) << 7) | (rfPwdXpd << 6)) & 0xC0); 1120185377Ssam ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x07) | 1121185377Ssam ((ath_hal_reverseBits(rfXpdGain, 4) >> 1) & 0x07); 1122185377Ssam 1123185377Ssam /* Set OB */ 1124185377Ssam ar5211Rf6n7[12][freqIndex] = (ar5211Rf6n7[12][freqIndex] & ~0x80) | 1125185377Ssam ((ath_hal_reverseBits(tempOB, 3) << 7) & 0x80); 1126185377Ssam ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x03) | 1127185377Ssam ((ath_hal_reverseBits(tempOB, 3) >> 1) & 0x03); 1128185377Ssam 1129185377Ssam /* Set DB */ 1130185377Ssam ar5211Rf6n7[13][freqIndex] = (ar5211Rf6n7[13][freqIndex] & ~0x1C) | 1131185377Ssam ((ath_hal_reverseBits(tempDB, 3) << 2) & 0x1C); 1132185377Ssam 1133185377Ssam /* Set rfPloSel */ 1134185377Ssam ar5211Rf6n7[17][freqIndex] = (ar5211Rf6n7[17][freqIndex] & ~0x08) | 1135185377Ssam ((rfPloSel << 3) & 0x08); 1136185377Ssam 1137185377Ssam /* Write the Rf registers 6 & 7 */ 1138185377Ssam for (i = 0; i < N(ar5211Rf6n7); i++) 1139185377Ssam OS_REG_WRITE(ah, ar5211Rf6n7[i][0], ar5211Rf6n7[i][freqIndex]); 1140185377Ssam 1141185377Ssam /* Now that we have reprogrammed rfgain value, clear the flag. */ 1142185377Ssam ahp->ah_rfgainState = RFGAIN_INACTIVE; 1143185377Ssam 1144185377Ssam return AH_TRUE; 1145185377Ssam#undef N 1146185377Ssam} 1147185377Ssam 1148185377SsamHAL_BOOL 1149185377Ssamar5211SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1150185377Ssam const HAL_CHANNEL *chan) 1151185377Ssam{ 1152185377Ssam#define ANT_SWITCH_TABLE1 0x9960 1153185377Ssam#define ANT_SWITCH_TABLE2 0x9964 1154185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1155185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1156185377Ssam uint32_t antSwitchA, antSwitchB; 1157185377Ssam int ix; 1158185377Ssam 1159185377Ssam switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) { 1160185377Ssam case CHANNEL_A: ix = 0; break; 1161185377Ssam case CHANNEL_B: ix = 1; break; 1162185377Ssam case CHANNEL_PUREG: ix = 2; break; 1163185377Ssam default: 1164185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1165185377Ssam __func__, chan->channelFlags); 1166185377Ssam return AH_FALSE; 1167185377Ssam } 1168185377Ssam 1169185377Ssam antSwitchA = ee->ee_antennaControl[1][ix] 1170185377Ssam | (ee->ee_antennaControl[2][ix] << 6) 1171185377Ssam | (ee->ee_antennaControl[3][ix] << 12) 1172185377Ssam | (ee->ee_antennaControl[4][ix] << 18) 1173185377Ssam | (ee->ee_antennaControl[5][ix] << 24) 1174185377Ssam ; 1175185377Ssam antSwitchB = ee->ee_antennaControl[6][ix] 1176185377Ssam | (ee->ee_antennaControl[7][ix] << 6) 1177185377Ssam | (ee->ee_antennaControl[8][ix] << 12) 1178185377Ssam | (ee->ee_antennaControl[9][ix] << 18) 1179185377Ssam | (ee->ee_antennaControl[10][ix] << 24) 1180185377Ssam ; 1181185377Ssam /* 1182185377Ssam * For fixed antenna, give the same setting for both switch banks 1183185377Ssam */ 1184185377Ssam switch (settings) { 1185185377Ssam case HAL_ANT_FIXED_A: 1186185377Ssam antSwitchB = antSwitchA; 1187185377Ssam break; 1188185377Ssam case HAL_ANT_FIXED_B: 1189185377Ssam antSwitchA = antSwitchB; 1190185377Ssam break; 1191185377Ssam case HAL_ANT_VARIABLE: 1192185377Ssam break; 1193185377Ssam default: 1194185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1195185377Ssam __func__, settings); 1196185377Ssam return AH_FALSE; 1197185377Ssam } 1198185377Ssam ahp->ah_diversityControl = settings; 1199185377Ssam 1200185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1201185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1202185377Ssam 1203185377Ssam return AH_TRUE; 1204185377Ssam#undef ANT_SWITCH_TABLE1 1205185377Ssam#undef ANT_SWITCH_TABLE2 1206185377Ssam} 1207185377Ssam 1208185377Ssam/* 1209185377Ssam * Reads EEPROM header info and programs the device for correct operation 1210185377Ssam * given the channel value 1211185377Ssam */ 1212185377Ssamstatic HAL_BOOL 1213185377Ssamar5211SetBoardValues(struct ath_hal *ah, HAL_CHANNEL *chan) 1214185377Ssam{ 1215185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1216185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1217185377Ssam int arrayMode, falseDectectBackoff; 1218185377Ssam 1219185377Ssam switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) { 1220185377Ssam case CHANNEL_A: 1221185377Ssam arrayMode = 0; 1222185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1223185377Ssam AR_PHY_FRAME_CTL_TX_CLIP, ee->ee_cornerCal.clip); 1224185377Ssam break; 1225185377Ssam case CHANNEL_CCK|CHANNEL_2GHZ: 1226185377Ssam arrayMode = 1; 1227185377Ssam break; 1228185377Ssam case CHANNEL_OFDM|CHANNEL_2GHZ: 1229185377Ssam arrayMode = 2; 1230185377Ssam break; 1231185377Ssam default: 1232185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1233185377Ssam __func__, chan->channelFlags); 1234185377Ssam return AH_FALSE; 1235185377Ssam } 1236185377Ssam 1237185377Ssam /* Set the antenna register(s) correctly for the chip revision */ 1238185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) { 1239185377Ssam OS_REG_WRITE(ah, AR_PHY(68), 1240185377Ssam (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) | 0x3); 1241185377Ssam } else { 1242185377Ssam OS_REG_WRITE(ah, AR_PHY(68), 1243185377Ssam (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFC06) | 1244185377Ssam (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1245185377Ssam 1246185377Ssam ar5211SetAntennaSwitchInternal(ah, 1247185377Ssam ahp->ah_diversityControl, chan); 1248185377Ssam 1249185377Ssam /* Set the Noise Floor Thresh on ar5211 devices */ 1250185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2), 1251185377Ssam (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) | (1<<9)); 1252185377Ssam } 1253185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2), 1254185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) | 1255185377Ssam ((ee->ee_switchSettling[arrayMode] << 7) & 0x3F80)); 1256185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2), 1257185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) | 1258185377Ssam ((ee->ee_txrxAtten[arrayMode] << 12) & 0x3F000)); 1259185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2), 1260185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) | 1261185377Ssam ((ee->ee_pgaDesiredSize[arrayMode] << 8) & 0xFF00) | 1262185377Ssam (ee->ee_adcDesiredSize[arrayMode] & 0x00FF)); 1263185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2), 1264185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 24) | 1265185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 16) | 1266185377Ssam (ee->ee_txFrameToXPAOn[arrayMode] << 8) | 1267185377Ssam ee->ee_txFrameToXPAOn[arrayMode]); 1268185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (10 << 2), 1269185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (10 << 2)) & 0xFFFF00FF) | 1270185377Ssam (ee->ee_txEndToXLNAOn[arrayMode] << 8)); 1271185377Ssam OS_REG_WRITE(ah, AR_PHY_BASE + (25 << 2), 1272185377Ssam (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) & 0xFFF80FFF) | 1273185377Ssam ((ee->ee_thresh62[arrayMode] << 12) & 0x7F000)); 1274185377Ssam 1275185377Ssam#define NO_FALSE_DETECT_BACKOFF 2 1276185377Ssam#define CB22_FALSE_DETECT_BACKOFF 6 1277185377Ssam /* 1278185377Ssam * False detect backoff - suspected 32 MHz spur causes 1279185377Ssam * false detects in OFDM, causing Tx Hangs. Decrease 1280185377Ssam * weak signal sensitivity for this card. 1281185377Ssam */ 1282185377Ssam falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1283185377Ssam if (AH_PRIVATE(ah)->ah_eeversion < AR_EEPROM_VER3_3) { 1284185377Ssam if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1285185377Ssam IS_CHAN_OFDM(chan)) 1286185377Ssam falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1287185377Ssam } else { 1288185377Ssam uint32_t remainder = chan->channel % 32; 1289185377Ssam 1290185377Ssam if (remainder && (remainder < 10 || remainder > 22)) 1291185377Ssam falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1292185377Ssam } 1293185377Ssam OS_REG_WRITE(ah, 0x9924, 1294185377Ssam (OS_REG_READ(ah, 0x9924) & 0xFFFFFF01) 1295185377Ssam | ((falseDectectBackoff << 1) & 0xF7)); 1296185377Ssam 1297185377Ssam return AH_TRUE; 1298185377Ssam#undef NO_FALSE_DETECT_BACKOFF 1299185377Ssam#undef CB22_FALSE_DETECT_BACKOFF 1300185377Ssam} 1301185377Ssam 1302185377Ssam/* 1303185377Ssam * Set the limit on the overall output power. Used for dynamic 1304185377Ssam * transmit power control and the like. 1305185377Ssam * 1306185377Ssam * NOTE: The power is passed in is in units of 0.5 dBm. 1307185377Ssam */ 1308185377SsamHAL_BOOL 1309185377Ssamar5211SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1310185377Ssam{ 1311185377Ssam 1312185377Ssam AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1313185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, limit); 1314185377Ssam return AH_TRUE; 1315185377Ssam} 1316185377Ssam 1317185377Ssam/* 1318185377Ssam * Sets the transmit power in the baseband for the given 1319185377Ssam * operating channel and mode. 1320185377Ssam */ 1321185377SsamHAL_BOOL 1322185377Ssamar5211SetTransmitPower(struct ath_hal *ah, HAL_CHANNEL *chan) 1323185377Ssam{ 1324185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1325185377Ssam TRGT_POWER_INFO *pi; 1326185377Ssam RD_EDGES_POWER *rep; 1327185377Ssam PCDACS_EEPROM eepromPcdacs; 1328185377Ssam u_int nchan, cfgCtl; 1329185377Ssam int i; 1330185377Ssam 1331185377Ssam /* setup the pcdac struct to point to the correct info, based on mode */ 1332185377Ssam switch (chan->channelFlags & CHANNEL_ALL_NOTURBO) { 1333185377Ssam case CHANNEL_A: 1334185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels11a; 1335185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11a; 1336185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a; 1337185377Ssam nchan = ee->ee_numTargetPwr_11a; 1338185377Ssam pi = ee->ee_trgtPwr_11a; 1339185377Ssam break; 1340185377Ssam case CHANNEL_OFDM|CHANNEL_2GHZ: 1341185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels2_4; 1342185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11g; 1343185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g; 1344185377Ssam nchan = ee->ee_numTargetPwr_11g; 1345185377Ssam pi = ee->ee_trgtPwr_11g; 1346185377Ssam break; 1347185377Ssam case CHANNEL_CCK|CHANNEL_2GHZ: 1348185377Ssam eepromPcdacs.numChannels = ee->ee_numChannels2_4; 1349185377Ssam eepromPcdacs.pChannelList= ee->ee_channels11b; 1350185377Ssam eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b; 1351185377Ssam nchan = ee->ee_numTargetPwr_11b; 1352185377Ssam pi = ee->ee_trgtPwr_11b; 1353185377Ssam break; 1354185377Ssam default: 1355185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1356185377Ssam __func__, chan->channelFlags); 1357185377Ssam return AH_FALSE; 1358185377Ssam } 1359185377Ssam 1360185377Ssam ar5211SetPowerTable(ah, &eepromPcdacs, chan->channel); 1361185377Ssam 1362185377Ssam rep = AH_NULL; 1363185377Ssam /* Match CTL to EEPROM value */ 1364185377Ssam cfgCtl = ath_hal_getctl(ah, chan); 1365185377Ssam for (i = 0; i < ee->ee_numCtls; i++) 1366185377Ssam if (ee->ee_ctl[i] != 0 && ee->ee_ctl[i] == cfgCtl) { 1367185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 1368185377Ssam break; 1369185377Ssam } 1370185377Ssam ar5211SetRateTable(ah, rep, pi, nchan, chan); 1371185377Ssam 1372185377Ssam return AH_TRUE; 1373185377Ssam} 1374185377Ssam 1375185377Ssam/* 1376185377Ssam * Read the transmit power levels from the structures taken 1377185377Ssam * from EEPROM. Interpolate read transmit power values for 1378185377Ssam * this channel. Organize the transmit power values into a 1379185377Ssam * table for writing into the hardware. 1380185377Ssam */ 1381185377Ssamvoid 1382185377Ssamar5211SetPowerTable(struct ath_hal *ah, PCDACS_EEPROM *pSrcStruct, uint16_t channel) 1383185377Ssam{ 1384185377Ssam static FULL_PCDAC_STRUCT pcdacStruct; 1385185377Ssam static uint16_t pcdacTable[PWR_TABLE_SIZE]; 1386185377Ssam 1387185377Ssam uint16_t i, j; 1388185377Ssam uint16_t *pPcdacValues; 1389185377Ssam int16_t *pScaledUpDbm; 1390185377Ssam int16_t minScaledPwr; 1391185377Ssam int16_t maxScaledPwr; 1392185377Ssam int16_t pwr; 1393185377Ssam uint16_t pcdacMin = 0; 1394185377Ssam uint16_t pcdacMax = 63; 1395185377Ssam uint16_t pcdacTableIndex; 1396185377Ssam uint16_t scaledPcdac; 1397185377Ssam uint32_t addr; 1398185377Ssam uint32_t temp32; 1399185377Ssam 1400185377Ssam OS_MEMZERO(&pcdacStruct, sizeof(FULL_PCDAC_STRUCT)); 1401185377Ssam OS_MEMZERO(pcdacTable, sizeof(uint16_t) * PWR_TABLE_SIZE); 1402185377Ssam pPcdacValues = pcdacStruct.PcdacValues; 1403185377Ssam pScaledUpDbm = pcdacStruct.PwrValues; 1404185377Ssam 1405185377Ssam /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */ 1406185377Ssam for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++) 1407185377Ssam pPcdacValues[j] = i; 1408185377Ssam 1409185377Ssam pcdacStruct.numPcdacValues = j; 1410185377Ssam pcdacStruct.pcdacMin = PCDAC_START; 1411185377Ssam pcdacStruct.pcdacMax = PCDAC_STOP; 1412185377Ssam 1413185377Ssam /* Fill out the power values for this channel */ 1414185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++ ) 1415185377Ssam pScaledUpDbm[j] = ar5211GetScaledPower(channel, pPcdacValues[j], pSrcStruct); 1416185377Ssam 1417185377Ssam /* Now scale the pcdac values to fit in the 64 entry power table */ 1418185377Ssam minScaledPwr = pScaledUpDbm[0]; 1419185377Ssam maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1]; 1420185377Ssam 1421185377Ssam /* find minimum and make monotonic */ 1422185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++) { 1423185377Ssam if (minScaledPwr >= pScaledUpDbm[j]) { 1424185377Ssam minScaledPwr = pScaledUpDbm[j]; 1425185377Ssam pcdacMin = j; 1426185377Ssam } 1427185377Ssam /* 1428185377Ssam * Make the full_hsh monotonically increasing otherwise 1429185377Ssam * interpolation algorithm will get fooled gotta start 1430185377Ssam * working from the top, hence i = 63 - j. 1431185377Ssam */ 1432185377Ssam i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j); 1433185377Ssam if (i == 0) 1434185377Ssam break; 1435185377Ssam if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) { 1436185377Ssam /* 1437185377Ssam * It could be a glitch, so make the power for 1438185377Ssam * this pcdac the same as the power from the 1439185377Ssam * next highest pcdac. 1440185377Ssam */ 1441185377Ssam pScaledUpDbm[i - 1] = pScaledUpDbm[i]; 1442185377Ssam } 1443185377Ssam } 1444185377Ssam 1445185377Ssam for (j = 0; j < pcdacStruct.numPcdacValues; j++) 1446185377Ssam if (maxScaledPwr < pScaledUpDbm[j]) { 1447185377Ssam maxScaledPwr = pScaledUpDbm[j]; 1448185377Ssam pcdacMax = j; 1449185377Ssam } 1450185377Ssam 1451185377Ssam /* Find the first power level with a pcdac */ 1452185377Ssam pwr = (uint16_t)(PWR_STEP * ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN); 1453185377Ssam 1454185377Ssam /* Write all the first pcdac entries based off the pcdacMin */ 1455185377Ssam pcdacTableIndex = 0; 1456185377Ssam for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) 1457185377Ssam pcdacTable[pcdacTableIndex++] = pcdacMin; 1458185377Ssam 1459185377Ssam i = 0; 1460185377Ssam while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) { 1461185377Ssam pwr += PWR_STEP; 1462185377Ssam /* stop if dbM > max_power_possible */ 1463185377Ssam while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] && 1464185377Ssam (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0) 1465185377Ssam i++; 1466185377Ssam /* scale by 2 and add 1 to enable round up or down as needed */ 1467185377Ssam scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr, 1468185377Ssam pScaledUpDbm[i], pScaledUpDbm[i+1], 1469185377Ssam (uint16_t)(pPcdacValues[i] * 2), 1470185377Ssam (uint16_t)(pPcdacValues[i+1] * 2), 0) + 1); 1471185377Ssam 1472185377Ssam pcdacTable[pcdacTableIndex] = scaledPcdac / 2; 1473185377Ssam if (pcdacTable[pcdacTableIndex] > pcdacMax) 1474185377Ssam pcdacTable[pcdacTableIndex] = pcdacMax; 1475185377Ssam pcdacTableIndex++; 1476185377Ssam } 1477185377Ssam 1478185377Ssam /* Write all the last pcdac entries based off the last valid pcdac */ 1479185377Ssam while (pcdacTableIndex < PWR_TABLE_SIZE) { 1480185377Ssam pcdacTable[pcdacTableIndex] = pcdacTable[pcdacTableIndex - 1]; 1481185377Ssam pcdacTableIndex++; 1482185377Ssam } 1483185377Ssam 1484185377Ssam /* Finally, write the power values into the baseband power table */ 1485185377Ssam addr = AR_PHY_BASE + (608 << 2); 1486185377Ssam for (i = 0; i < 32; i++) { 1487185377Ssam temp32 = 0xffff & ((pcdacTable[2 * i + 1] << 8) | 0xff); 1488185377Ssam temp32 = (temp32 << 16) | (0xffff & ((pcdacTable[2 * i] << 8) | 0xff)); 1489185377Ssam OS_REG_WRITE(ah, addr, temp32); 1490185377Ssam addr += 4; 1491185377Ssam } 1492185377Ssam 1493185377Ssam} 1494185377Ssam 1495185377Ssam/* 1496185377Ssam * Set the transmit power in the baseband for the given 1497185377Ssam * operating channel and mode. 1498185377Ssam */ 1499185377Ssamvoid 1500185377Ssamar5211SetRateTable(struct ath_hal *ah, RD_EDGES_POWER *pRdEdgesPower, 1501185377Ssam TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 1502185377Ssam HAL_CHANNEL *chan) 1503185377Ssam{ 1504185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1505185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1506185377Ssam static uint16_t ratesArray[NUM_RATES]; 1507185377Ssam static const uint16_t tpcScaleReductionTable[5] = 1508185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 1509185377Ssam 1510185377Ssam uint16_t *pRatesPower; 1511185377Ssam uint16_t lowerChannel, lowerIndex=0, lowerPower=0; 1512185377Ssam uint16_t upperChannel, upperIndex=0, upperPower=0; 1513185377Ssam uint16_t twiceMaxEdgePower=63; 1514185377Ssam uint16_t twicePower = 0; 1515185377Ssam uint16_t i, numEdges; 1516185377Ssam uint16_t tempChannelList[NUM_EDGES]; /* temp array for holding edge channels */ 1517185377Ssam uint16_t twiceMaxRDPower; 1518185377Ssam int16_t scaledPower = 0; /* for gcc -O2 */ 1519185377Ssam uint16_t mask = 0x3f; 1520185377Ssam HAL_BOOL paPreDEnable = 0; 1521185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction = 0; 1522185377Ssam 1523185377Ssam pRatesPower = ratesArray; 1524185377Ssam twiceMaxRDPower = chan->maxRegTxPower * 2; 1525185377Ssam 1526185377Ssam if (IS_CHAN_5GHZ(chan)) { 1527185377Ssam twiceAntennaGain = ee->ee_antennaGainMax[0]; 1528185377Ssam } else { 1529185377Ssam twiceAntennaGain = ee->ee_antennaGainMax[1]; 1530185377Ssam } 1531185377Ssam 1532185377Ssam twiceAntennaReduction = ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 1533185377Ssam 1534185377Ssam if (pRdEdgesPower) { 1535185377Ssam /* Get the edge power */ 1536185377Ssam for (i = 0; i < NUM_EDGES; i++) { 1537185377Ssam if (pRdEdgesPower[i].rdEdge == 0) 1538185377Ssam break; 1539185377Ssam tempChannelList[i] = pRdEdgesPower[i].rdEdge; 1540185377Ssam } 1541185377Ssam numEdges = i; 1542185377Ssam 1543185377Ssam ar5211GetLowerUpperValues(chan->channel, tempChannelList, 1544185377Ssam numEdges, &lowerChannel, &upperChannel); 1545185377Ssam /* Get the index for this channel */ 1546185377Ssam for (i = 0; i < numEdges; i++) 1547185377Ssam if (lowerChannel == tempChannelList[i]) 1548185377Ssam break; 1549185377Ssam HALASSERT(i != numEdges); 1550185377Ssam 1551185377Ssam if ((lowerChannel == upperChannel && 1552185377Ssam lowerChannel == chan->channel) || 1553185377Ssam pRdEdgesPower[i].flag) { 1554185377Ssam twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 1555185377Ssam HALASSERT(twiceMaxEdgePower > 0); 1556185377Ssam } 1557185377Ssam } 1558185377Ssam 1559185377Ssam /* extrapolate the power values for the test Groups */ 1560185377Ssam for (i = 0; i < numChannels; i++) 1561185377Ssam tempChannelList[i] = pPowerInfo[i].testChannel; 1562185377Ssam 1563185377Ssam ar5211GetLowerUpperValues(chan->channel, tempChannelList, 1564185377Ssam numChannels, &lowerChannel, &upperChannel); 1565185377Ssam 1566185377Ssam /* get the index for the channel */ 1567185377Ssam for (i = 0; i < numChannels; i++) { 1568185377Ssam if (lowerChannel == tempChannelList[i]) 1569185377Ssam lowerIndex = i; 1570185377Ssam if (upperChannel == tempChannelList[i]) { 1571185377Ssam upperIndex = i; 1572185377Ssam break; 1573185377Ssam } 1574185377Ssam } 1575185377Ssam 1576185377Ssam for (i = 0; i < NUM_RATES; i++) { 1577185377Ssam if (IS_CHAN_OFDM(chan)) { 1578185377Ssam /* power for rates 6,9,12,18,24 is all the same */ 1579185377Ssam if (i < 5) { 1580185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr6_24; 1581185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr6_24; 1582185377Ssam } else if (i == 5) { 1583185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr36; 1584185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr36; 1585185377Ssam } else if (i == 6) { 1586185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr48; 1587185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr48; 1588185377Ssam } else if (i == 7) { 1589185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr54; 1590185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr54; 1591185377Ssam } 1592185377Ssam } else { 1593185377Ssam switch (i) { 1594185377Ssam case 0: 1595185377Ssam case 1: 1596185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr6_24; 1597185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr6_24; 1598185377Ssam break; 1599185377Ssam case 2: 1600185377Ssam case 3: 1601185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr36; 1602185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr36; 1603185377Ssam break; 1604185377Ssam case 4: 1605185377Ssam case 5: 1606185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr48; 1607185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr48; 1608185377Ssam break; 1609185377Ssam case 6: 1610185377Ssam case 7: 1611185377Ssam lowerPower = pPowerInfo[lowerIndex].twicePwr54; 1612185377Ssam upperPower = pPowerInfo[upperIndex].twicePwr54; 1613185377Ssam break; 1614185377Ssam } 1615185377Ssam } 1616185377Ssam 1617185377Ssam twicePower = ar5211GetInterpolatedValue(chan->channel, 1618185377Ssam lowerChannel, upperChannel, lowerPower, upperPower, 0); 1619185377Ssam 1620185377Ssam /* Reduce power by band edge restrictions */ 1621185377Ssam twicePower = AH_MIN(twicePower, twiceMaxEdgePower); 1622185377Ssam 1623185377Ssam /* 1624185377Ssam * If turbo is set, reduce power to keep power 1625185377Ssam * consumption under 2 Watts. Note that we always do 1626185377Ssam * this unless specially configured. Then we limit 1627185377Ssam * power only for non-AP operation. 1628185377Ssam */ 1629185377Ssam if (IS_CHAN_TURBO(chan) && 1630185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1 1631185377Ssam#ifdef AH_ENABLE_AP_SUPPORT 1632185377Ssam && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 1633185377Ssam#endif 1634185377Ssam ) { 1635185377Ssam twicePower = AH_MIN(twicePower, ee->ee_turbo2WMaxPower5); 1636185377Ssam } 1637185377Ssam 1638185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 1639185377Ssam pRatesPower[i] = AH_MIN(twicePower, twiceMaxRDPower - twiceAntennaReduction); 1640185377Ssam 1641185377Ssam /* Use 6 Mb power level for transmit power scaling reduction */ 1642185377Ssam /* We don't want to reduce higher rates if its not needed */ 1643185377Ssam if (i == 0) { 1644185377Ssam scaledPower = pRatesPower[0] - 1645185377Ssam (tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2); 1646185377Ssam if (scaledPower < 1) 1647185377Ssam scaledPower = 1; 1648185377Ssam } 1649185377Ssam 1650185377Ssam pRatesPower[i] = AH_MIN(pRatesPower[i], scaledPower); 1651185377Ssam } 1652185377Ssam 1653185377Ssam /* Record txPower at Rate 6 for info gathering */ 1654185377Ssam ahp->ah_tx6PowerInHalfDbm = pRatesPower[0]; 1655185377Ssam 1656185377Ssam#ifdef AH_DEBUG 1657185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1658185377Ssam "%s: final output power setting %d MHz:\n", 1659185377Ssam __func__, chan->channel); 1660185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1661185377Ssam "6 Mb %d dBm, MaxRD: %d dBm, MaxEdge %d dBm\n", 1662185377Ssam scaledPower / 2, twiceMaxRDPower / 2, twiceMaxEdgePower / 2); 1663185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "TPC Scale %d dBm - Ant Red %d dBm\n", 1664185377Ssam tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale] * 2, 1665185377Ssam twiceAntennaReduction / 2); 1666185377Ssam if (IS_CHAN_TURBO(chan) && 1667185377Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3_1) 1668185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "Max Turbo %d dBm\n", 1669185377Ssam ee->ee_turbo2WMaxPower5); 1670185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 1671185377Ssam " %2d | %2d | %2d | %2d | %2d | %2d | %2d | %2d dBm\n", 1672185377Ssam pRatesPower[0] / 2, pRatesPower[1] / 2, pRatesPower[2] / 2, 1673185377Ssam pRatesPower[3] / 2, pRatesPower[4] / 2, pRatesPower[5] / 2, 1674185377Ssam pRatesPower[6] / 2, pRatesPower[7] / 2); 1675185377Ssam#endif /* AH_DEBUG */ 1676185377Ssam 1677185377Ssam /* Write the power table into the hardware */ 1678185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1679185377Ssam ((paPreDEnable & 1)<< 30) | ((pRatesPower[3] & mask) << 24) | 1680185377Ssam ((paPreDEnable & 1)<< 22) | ((pRatesPower[2] & mask) << 16) | 1681185377Ssam ((paPreDEnable & 1)<< 14) | ((pRatesPower[1] & mask) << 8) | 1682185377Ssam ((paPreDEnable & 1)<< 6 ) | (pRatesPower[0] & mask)); 1683185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1684185377Ssam ((paPreDEnable & 1)<< 30) | ((pRatesPower[7] & mask) << 24) | 1685185377Ssam ((paPreDEnable & 1)<< 22) | ((pRatesPower[6] & mask) << 16) | 1686185377Ssam ((paPreDEnable & 1)<< 14) | ((pRatesPower[5] & mask) << 8) | 1687185377Ssam ((paPreDEnable & 1)<< 6 ) | (pRatesPower[4] & mask)); 1688185377Ssam 1689185377Ssam /* set max power to the power value at rate 6 */ 1690185377Ssam ar5211SetTxPowerLimit(ah, pRatesPower[0]); 1691185377Ssam 1692185377Ssam AH_PRIVATE(ah)->ah_maxPowerLevel = pRatesPower[0]; 1693185377Ssam} 1694185377Ssam 1695185377Ssam/* 1696185377Ssam * Get or interpolate the pcdac value from the calibrated data 1697185377Ssam */ 1698185377Ssamuint16_t 1699185377Ssamar5211GetScaledPower(uint16_t channel, uint16_t pcdacValue, const PCDACS_EEPROM *pSrcStruct) 1700185377Ssam{ 1701185377Ssam uint16_t powerValue; 1702185377Ssam uint16_t lFreq, rFreq; /* left and right frequency values */ 1703185377Ssam uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */ 1704185377Ssam uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */ 1705185377Ssam uint16_t lPwr, uPwr; /* lower and upper temp pwr values */ 1706185377Ssam uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */ 1707185377Ssam 1708185377Ssam if (ar5211FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) 1709185377Ssam /* value was copied from srcStruct */ 1710185377Ssam return powerValue; 1711185377Ssam 1712185377Ssam ar5211GetLowerUpperValues(channel, pSrcStruct->pChannelList, 1713185377Ssam pSrcStruct->numChannels, &lFreq, &rFreq); 1714185377Ssam ar5211GetLowerUpperPcdacs(pcdacValue, lFreq, pSrcStruct, 1715185377Ssam &llPcdac, &ulPcdac); 1716185377Ssam ar5211GetLowerUpperPcdacs(pcdacValue, rFreq, pSrcStruct, 1717185377Ssam &lrPcdac, &urPcdac); 1718185377Ssam 1719185377Ssam /* get the power index for the pcdac value */ 1720185377Ssam ar5211FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr); 1721185377Ssam ar5211FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr); 1722185377Ssam lScaledPwr = ar5211GetInterpolatedValue(pcdacValue, 1723185377Ssam llPcdac, ulPcdac, lPwr, uPwr, 0); 1724185377Ssam 1725185377Ssam ar5211FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr); 1726185377Ssam ar5211FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr); 1727185377Ssam rScaledPwr = ar5211GetInterpolatedValue(pcdacValue, 1728185377Ssam lrPcdac, urPcdac, lPwr, uPwr, 0); 1729185377Ssam 1730185377Ssam return ar5211GetInterpolatedValue(channel, lFreq, rFreq, 1731185377Ssam lScaledPwr, rScaledPwr, 0); 1732185377Ssam} 1733185377Ssam 1734185377Ssam/* 1735185377Ssam * Find the value from the calibrated source data struct 1736185377Ssam */ 1737185377SsamHAL_BOOL 1738185377Ssamar5211FindValueInList(uint16_t channel, uint16_t pcdacValue, 1739185377Ssam const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue) 1740185377Ssam{ 1741185377Ssam const DATA_PER_CHANNEL *pChannelData; 1742185377Ssam const uint16_t *pPcdac; 1743185377Ssam uint16_t i, j; 1744185377Ssam 1745185377Ssam pChannelData = pSrcStruct->pDataPerChannel; 1746185377Ssam for (i = 0; i < pSrcStruct->numChannels; i++ ) { 1747185377Ssam if (pChannelData->channelValue == channel) { 1748185377Ssam pPcdac = pChannelData->PcdacValues; 1749185377Ssam for (j = 0; j < pChannelData->numPcdacValues; j++ ) { 1750185377Ssam if (*pPcdac == pcdacValue) { 1751185377Ssam *powerValue = pChannelData->PwrValues[j]; 1752185377Ssam return AH_TRUE; 1753185377Ssam } 1754185377Ssam pPcdac++; 1755185377Ssam } 1756185377Ssam } 1757185377Ssam pChannelData++; 1758185377Ssam } 1759185377Ssam return AH_FALSE; 1760185377Ssam} 1761185377Ssam 1762185377Ssam/* 1763185377Ssam * Returns interpolated or the scaled up interpolated value 1764185377Ssam */ 1765185377Ssamuint16_t 1766185377Ssamar5211GetInterpolatedValue(uint16_t target, 1767185377Ssam uint16_t srcLeft, uint16_t srcRight, 1768185377Ssam uint16_t targetLeft, uint16_t targetRight, 1769185377Ssam HAL_BOOL scaleUp) 1770185377Ssam{ 1771185377Ssam uint16_t rv; 1772185377Ssam int16_t lRatio; 1773185377Ssam uint16_t scaleValue = EEP_SCALE; 1774185377Ssam 1775185377Ssam /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 1776185377Ssam if ((targetLeft * targetRight) == 0) 1777185377Ssam return 0; 1778185377Ssam if (scaleUp) 1779185377Ssam scaleValue = 1; 1780185377Ssam 1781185377Ssam if (srcRight != srcLeft) { 1782185377Ssam /* 1783185377Ssam * Note the ratio always need to be scaled, 1784185377Ssam * since it will be a fraction. 1785185377Ssam */ 1786185377Ssam lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 1787185377Ssam if (lRatio < 0) { 1788185377Ssam /* Return as Left target if value would be negative */ 1789185377Ssam rv = targetLeft * (scaleUp ? EEP_SCALE : 1); 1790185377Ssam } else if (lRatio > EEP_SCALE) { 1791185377Ssam /* Return as Right target if Ratio is greater than 100% (SCALE) */ 1792185377Ssam rv = targetRight * (scaleUp ? EEP_SCALE : 1); 1793185377Ssam } else { 1794185377Ssam rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 1795185377Ssam targetLeft) / scaleValue; 1796185377Ssam } 1797185377Ssam } else { 1798185377Ssam rv = targetLeft; 1799185377Ssam if (scaleUp) 1800185377Ssam rv *= EEP_SCALE; 1801185377Ssam } 1802185377Ssam return rv; 1803185377Ssam} 1804185377Ssam 1805185377Ssam/* 1806185377Ssam * Look for value being within 0.1 of the search values 1807185377Ssam * however, NDIS can't do float calculations, so multiply everything 1808185377Ssam * up by EEP_SCALE so can do integer arithmatic 1809185377Ssam * 1810185377Ssam * INPUT value -value to search for 1811185377Ssam * INPUT pList -ptr to the list to search 1812185377Ssam * INPUT listSize -number of entries in list 1813185377Ssam * OUTPUT pLowerValue -return the lower value 1814185377Ssam * OUTPUT pUpperValue -return the upper value 1815185377Ssam */ 1816185377Ssamvoid 1817185377Ssamar5211GetLowerUpperValues(uint16_t value, 1818185377Ssam const uint16_t *pList, uint16_t listSize, 1819185377Ssam uint16_t *pLowerValue, uint16_t *pUpperValue) 1820185377Ssam{ 1821185377Ssam const uint16_t listEndValue = *(pList + listSize - 1); 1822185377Ssam uint32_t target = value * EEP_SCALE; 1823185377Ssam int i; 1824185377Ssam 1825185377Ssam /* 1826185377Ssam * See if value is lower than the first value in the list 1827185377Ssam * if so return first value 1828185377Ssam */ 1829185377Ssam if (target < (uint32_t)(*pList * EEP_SCALE - EEP_DELTA)) { 1830185377Ssam *pLowerValue = *pList; 1831185377Ssam *pUpperValue = *pList; 1832185377Ssam return; 1833185377Ssam } 1834185377Ssam 1835185377Ssam /* 1836185377Ssam * See if value is greater than last value in list 1837185377Ssam * if so return last value 1838185377Ssam */ 1839185377Ssam if (target > (uint32_t)(listEndValue * EEP_SCALE + EEP_DELTA)) { 1840185377Ssam *pLowerValue = listEndValue; 1841185377Ssam *pUpperValue = listEndValue; 1842185377Ssam return; 1843185377Ssam } 1844185377Ssam 1845185377Ssam /* look for value being near or between 2 values in list */ 1846185377Ssam for (i = 0; i < listSize; i++) { 1847185377Ssam /* 1848185377Ssam * If value is close to the current value of the list 1849185377Ssam * then target is not between values, it is one of the values 1850185377Ssam */ 1851185377Ssam if (abs(pList[i] * EEP_SCALE - (int32_t) target) < EEP_DELTA) { 1852185377Ssam *pLowerValue = pList[i]; 1853185377Ssam *pUpperValue = pList[i]; 1854185377Ssam return; 1855185377Ssam } 1856185377Ssam 1857185377Ssam /* 1858185377Ssam * Look for value being between current value and next value 1859185377Ssam * if so return these 2 values 1860185377Ssam */ 1861185377Ssam if (target < (uint32_t)(pList[i + 1] * EEP_SCALE - EEP_DELTA)) { 1862185377Ssam *pLowerValue = pList[i]; 1863185377Ssam *pUpperValue = pList[i + 1]; 1864185377Ssam return; 1865185377Ssam } 1866185377Ssam } 1867185377Ssam} 1868185377Ssam 1869185377Ssam/* 1870185377Ssam * Get the upper and lower pcdac given the channel and the pcdac 1871185377Ssam * used in the search 1872185377Ssam */ 1873185377Ssamvoid 1874185377Ssamar5211GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel, 1875185377Ssam const PCDACS_EEPROM *pSrcStruct, 1876185377Ssam uint16_t *pLowerPcdac, uint16_t *pUpperPcdac) 1877185377Ssam{ 1878185377Ssam const DATA_PER_CHANNEL *pChannelData; 1879185377Ssam int i; 1880185377Ssam 1881185377Ssam /* Find the channel information */ 1882185377Ssam pChannelData = pSrcStruct->pDataPerChannel; 1883185377Ssam for (i = 0; i < pSrcStruct->numChannels; i++) { 1884185377Ssam if (pChannelData->channelValue == channel) 1885185377Ssam break; 1886185377Ssam pChannelData++; 1887185377Ssam } 1888185377Ssam ar5211GetLowerUpperValues(pcdac, pChannelData->PcdacValues, 1889185377Ssam pChannelData->numPcdacValues, pLowerPcdac, pUpperPcdac); 1890185377Ssam} 1891185377Ssam 1892185377Ssam#define DYN_ADJ_UP_MARGIN 15 1893185377Ssam#define DYN_ADJ_LO_MARGIN 20 1894185377Ssam 1895185377Ssamstatic const GAIN_OPTIMIZATION_LADDER gainLadder = { 1896185377Ssam 9, /* numStepsInLadder */ 1897185377Ssam 4, /* defaultStepNum */ 1898185377Ssam { { {4, 1, 1, 1}, 6, "FG8"}, 1899185377Ssam { {4, 0, 1, 1}, 4, "FG7"}, 1900185377Ssam { {3, 1, 1, 1}, 3, "FG6"}, 1901185377Ssam { {4, 0, 0, 1}, 1, "FG5"}, 1902185377Ssam { {4, 1, 1, 0}, 0, "FG4"}, /* noJack */ 1903185377Ssam { {4, 0, 1, 0}, -2, "FG3"}, /* halfJack */ 1904185377Ssam { {3, 1, 1, 0}, -3, "FG2"}, /* clip3 */ 1905185377Ssam { {4, 0, 0, 0}, -4, "FG1"}, /* noJack */ 1906185377Ssam { {2, 1, 1, 0}, -6, "FG0"} /* clip2 */ 1907185377Ssam } 1908185377Ssam}; 1909185377Ssam 1910185377Ssam/* 1911185377Ssam * Initialize the gain structure to good values 1912185377Ssam */ 1913185377Ssamvoid 1914185377Ssamar5211InitializeGainValues(struct ath_hal *ah) 1915185377Ssam{ 1916185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1917185377Ssam GAIN_VALUES *gv = &ahp->ah_gainValues; 1918185377Ssam 1919185377Ssam /* initialize gain optimization values */ 1920185377Ssam gv->currStepNum = gainLadder.defaultStepNum; 1921185377Ssam gv->currStep = &gainLadder.optStep[gainLadder.defaultStepNum]; 1922185377Ssam gv->active = AH_TRUE; 1923185377Ssam gv->loTrig = 20; 1924185377Ssam gv->hiTrig = 35; 1925185377Ssam} 1926185377Ssam 1927185377Ssamstatic HAL_BOOL 1928185377Ssamar5211InvalidGainReadback(struct ath_hal *ah, GAIN_VALUES *gv) 1929185377Ssam{ 1930185377Ssam HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 1931185377Ssam uint32_t gStep, g; 1932185377Ssam uint32_t L1, L2, L3, L4; 1933185377Ssam 1934185377Ssam if (IS_CHAN_CCK(chan)) { 1935185377Ssam gStep = 0x18; 1936185377Ssam L1 = 0; 1937185377Ssam L2 = gStep + 4; 1938185377Ssam L3 = 0x40; 1939185377Ssam L4 = L3 + 50; 1940185377Ssam 1941185377Ssam gv->loTrig = L1; 1942185377Ssam gv->hiTrig = L4+5; 1943185377Ssam } else { 1944185377Ssam gStep = 0x3f; 1945185377Ssam L1 = 0; 1946185377Ssam L2 = 50; 1947185377Ssam L3 = L1; 1948185377Ssam L4 = L3 + 50; 1949185377Ssam 1950185377Ssam gv->loTrig = L1 + DYN_ADJ_LO_MARGIN; 1951185377Ssam gv->hiTrig = L4 - DYN_ADJ_UP_MARGIN; 1952185377Ssam } 1953185377Ssam g = gv->currGain; 1954185377Ssam 1955185377Ssam return !((g >= L1 && g<= L2) || (g >= L3 && g <= L4)); 1956185377Ssam} 1957185377Ssam 1958185377Ssam/* 1959185377Ssam * Enable the probe gain check on the next packet 1960185377Ssam */ 1961185377Ssamstatic void 1962185377Ssamar5211RequestRfgain(struct ath_hal *ah) 1963185377Ssam{ 1964185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1965185377Ssam 1966185377Ssam /* Enable the gain readback probe */ 1967185377Ssam OS_REG_WRITE(ah, AR_PHY_PAPD_PROBE, 1968185377Ssam SM(ahp->ah_tx6PowerInHalfDbm, AR_PHY_PAPD_PROBE_POWERTX) 1969185377Ssam | AR_PHY_PAPD_PROBE_NEXT_TX); 1970185377Ssam 1971185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_READ_REQUESTED; 1972185377Ssam} 1973185377Ssam 1974185377Ssam/* 1975185377Ssam * Exported call to check for a recent gain reading and return 1976185377Ssam * the current state of the thermal calibration gain engine. 1977185377Ssam */ 1978185377SsamHAL_RFGAIN 1979185377Ssamar5211GetRfgain(struct ath_hal *ah) 1980185377Ssam{ 1981185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 1982185377Ssam GAIN_VALUES *gv = &ahp->ah_gainValues; 1983185377Ssam uint32_t rddata; 1984185377Ssam 1985185377Ssam if (!gv->active) 1986185377Ssam return HAL_RFGAIN_INACTIVE; 1987185377Ssam 1988185377Ssam if (ahp->ah_rfgainState == HAL_RFGAIN_READ_REQUESTED) { 1989185377Ssam /* Caller had asked to setup a new reading. Check it. */ 1990185377Ssam rddata = OS_REG_READ(ah, AR_PHY_PAPD_PROBE); 1991185377Ssam 1992185377Ssam if ((rddata & AR_PHY_PAPD_PROBE_NEXT_TX) == 0) { 1993185377Ssam /* bit got cleared, we have a new reading. */ 1994185377Ssam gv->currGain = rddata >> AR_PHY_PAPD_PROBE_GAINF_S; 1995185377Ssam /* inactive by default */ 1996185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE; 1997185377Ssam 1998185377Ssam if (!ar5211InvalidGainReadback(ah, gv) && 1999185377Ssam ar5211IsGainAdjustNeeded(ah, gv) && 2000185377Ssam ar5211AdjustGain(ah, gv) > 0) { 2001185377Ssam /* 2002185377Ssam * Change needed. Copy ladder info 2003185377Ssam * into eeprom info. 2004185377Ssam */ 2005185377Ssam ar5211SetRfgain(ah, gv); 2006185377Ssam ahp->ah_rfgainState = HAL_RFGAIN_NEED_CHANGE; 2007185377Ssam } 2008185377Ssam } 2009185377Ssam } 2010185377Ssam return ahp->ah_rfgainState; 2011185377Ssam} 2012185377Ssam 2013185377Ssam/* 2014185377Ssam * Check to see if our readback gain level sits within the linear 2015185377Ssam * region of our current variable attenuation window 2016185377Ssam */ 2017185377Ssamstatic HAL_BOOL 2018185377Ssamar5211IsGainAdjustNeeded(struct ath_hal *ah, const GAIN_VALUES *gv) 2019185377Ssam{ 2020185377Ssam return (gv->currGain <= gv->loTrig || gv->currGain >= gv->hiTrig); 2021185377Ssam} 2022185377Ssam 2023185377Ssam/* 2024185377Ssam * Move the rabbit ears in the correct direction. 2025185377Ssam */ 2026185377Ssamstatic int32_t 2027185377Ssamar5211AdjustGain(struct ath_hal *ah, GAIN_VALUES *gv) 2028185377Ssam{ 2029185377Ssam /* return > 0 for valid adjustments. */ 2030185377Ssam if (!gv->active) 2031185377Ssam return -1; 2032185377Ssam 2033185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2034185377Ssam if (gv->currGain >= gv->hiTrig) { 2035185377Ssam if (gv->currStepNum == 0) { 2036185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2037185377Ssam "%s: Max gain limit.\n", __func__); 2038185377Ssam return -1; 2039185377Ssam } 2040185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2041185377Ssam "%s: Adding gain: currG=%d [%s] --> ", 2042185377Ssam __func__, gv->currGain, gv->currStep->stepName); 2043185377Ssam gv->targetGain = gv->currGain; 2044185377Ssam while (gv->targetGain >= gv->hiTrig && gv->currStepNum > 0) { 2045185377Ssam gv->targetGain -= 2 * (gainLadder.optStep[--(gv->currStepNum)].stepGain - 2046185377Ssam gv->currStep->stepGain); 2047185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2048185377Ssam } 2049185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n", 2050185377Ssam gv->targetGain, gv->currStep->stepName); 2051185377Ssam return 1; 2052185377Ssam } 2053185377Ssam if (gv->currGain <= gv->loTrig) { 2054185377Ssam if (gv->currStepNum == gainLadder.numStepsInLadder-1) { 2055185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2056185377Ssam "%s: Min gain limit.\n", __func__); 2057185377Ssam return -2; 2058185377Ssam } 2059185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2060185377Ssam "%s: Deducting gain: currG=%d [%s] --> ", 2061185377Ssam __func__, gv->currGain, gv->currStep->stepName); 2062185377Ssam gv->targetGain = gv->currGain; 2063185377Ssam while (gv->targetGain <= gv->loTrig && 2064185377Ssam gv->currStepNum < (gainLadder.numStepsInLadder - 1)) { 2065185377Ssam gv->targetGain -= 2 * 2066185377Ssam (gainLadder.optStep[++(gv->currStepNum)].stepGain - gv->currStep->stepGain); 2067185377Ssam gv->currStep = &gainLadder.optStep[gv->currStepNum]; 2068185377Ssam } 2069185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "targG=%d [%s]\n", 2070185377Ssam gv->targetGain, gv->currStep->stepName); 2071185377Ssam return 2; 2072185377Ssam } 2073185377Ssam return 0; /* caller didn't call needAdjGain first */ 2074185377Ssam} 2075185377Ssam 2076185377Ssam/* 2077185377Ssam * Adjust the 5GHz EEPROM information with the desired calibration values. 2078185377Ssam */ 2079185377Ssamstatic void 2080185377Ssamar5211SetRfgain(struct ath_hal *ah, const GAIN_VALUES *gv) 2081185377Ssam{ 2082185377Ssam HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2083185377Ssam 2084185377Ssam if (!gv->active) 2085185377Ssam return; 2086185377Ssam ee->ee_cornerCal.clip = gv->currStep->paramVal[0]; /* bb_tx_clip */ 2087185377Ssam ee->ee_cornerCal.pd90 = gv->currStep->paramVal[1]; /* rf_pwd_90 */ 2088185377Ssam ee->ee_cornerCal.pd84 = gv->currStep->paramVal[2]; /* rf_pwd_84 */ 2089185377Ssam ee->ee_cornerCal.gSel = gv->currStep->paramVal[3]; /* rf_rfgainsel */ 2090185377Ssam} 2091185377Ssam 2092185377Ssamstatic void 2093185377Ssamar5211SetOperatingMode(struct ath_hal *ah, int opmode) 2094185377Ssam{ 2095185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 2096185377Ssam uint32_t val; 2097185377Ssam 2098185377Ssam val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff; 2099185377Ssam switch (opmode) { 2100185377Ssam case HAL_M_HOSTAP: 2101185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2102185377Ssam | AR_STA_ID1_STA_AP 2103185377Ssam | AR_STA_ID1_RTS_USE_DEF 2104185377Ssam | ahp->ah_staId1Defaults); 2105185377Ssam break; 2106185377Ssam case HAL_M_IBSS: 2107185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2108185377Ssam | AR_STA_ID1_ADHOC 2109185377Ssam | AR_STA_ID1_DESC_ANTENNA 2110185377Ssam | ahp->ah_staId1Defaults); 2111185377Ssam break; 2112185377Ssam case HAL_M_STA: 2113185377Ssam case HAL_M_MONITOR: 2114185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val 2115185377Ssam | AR_STA_ID1_DEFAULT_ANTENNA 2116185377Ssam | ahp->ah_staId1Defaults); 2117185377Ssam break; 2118185377Ssam } 2119185377Ssam} 2120185377Ssam 2121185377Ssamvoid 2122185377Ssamar5211SetPCUConfig(struct ath_hal *ah) 2123185377Ssam{ 2124185377Ssam ar5211SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); 2125185377Ssam} 2126185377Ssam#endif /* AH_SUPPORT_AR5211 */ 2127