1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17191864Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam 24185377Ssam#include "ar5211/ar5211.h" 25185377Ssam#include "ar5211/ar5211reg.h" 26185377Ssam 27185377Ssam/* 28185377Ssam * Checks to see if an interrupt is pending on our NIC 29185377Ssam * 30185377Ssam * Returns: TRUE if an interrupt is pending 31185377Ssam * FALSE if not 32185377Ssam */ 33185377SsamHAL_BOOL 34185377Ssamar5211IsInterruptPending(struct ath_hal *ah) 35185377Ssam{ 36185377Ssam return OS_REG_READ(ah, AR_INTPEND) != 0; 37185377Ssam} 38185377Ssam 39185377Ssam/* 40185377Ssam * Reads the Interrupt Status Register value from the NIC, thus deasserting 41185377Ssam * the interrupt line, and returns both the masked and unmasked mapped ISR 42185377Ssam * values. The value returned is mapped to abstract the hw-specific bit 43185377Ssam * locations in the Interrupt Status Register. 44185377Ssam * 45185377Ssam * Returns: A hardware-abstracted bitmap of all non-masked-out 46185377Ssam * interrupts pending, as well as an unmasked value 47185377Ssam */ 48185377SsamHAL_BOOL 49185377Ssamar5211GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 50185377Ssam{ 51185377Ssam uint32_t isr; 52185377Ssam 53185377Ssam isr = OS_REG_READ(ah, AR_ISR_RAC); 54185377Ssam if (isr == 0xffffffff) { 55185377Ssam *masked = 0; 56185377Ssam return AH_FALSE; 57185377Ssam } 58185377Ssam 59185377Ssam *masked = isr & HAL_INT_COMMON; 60185377Ssam 61185377Ssam if (isr & AR_ISR_HIUERR) 62185377Ssam *masked |= HAL_INT_FATAL; 63185377Ssam if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 64185377Ssam *masked |= HAL_INT_RX; 65185377Ssam if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) 66185377Ssam *masked |= HAL_INT_TX; 67185377Ssam /* 68185380Ssam * Receive overrun is usually non-fatal on Oahu/Spirit. 69185380Ssam * BUT on some parts rx could fail and the chip must be reset. 70185380Ssam * So we force a hardware reset in all cases. 71185377Ssam */ 72185377Ssam if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { 73185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 74185377Ssam "%s: receive FIFO overrun interrupt\n", __func__); 75185377Ssam *masked |= HAL_INT_FATAL; 76185377Ssam } 77185377Ssam 78185377Ssam /* 79185377Ssam * On fatal errors collect ISR state for debugging. 80185377Ssam */ 81185377Ssam if (*masked & HAL_INT_FATAL) { 82185377Ssam AH_PRIVATE(ah)->ah_fatalState[0] = isr; 83185377Ssam AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 84185377Ssam AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 85185377Ssam AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 86185377Ssam AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 87185377Ssam AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 88185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 89185377Ssam "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n", 90185377Ssam __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); 91185377Ssam } 92185377Ssam return AH_TRUE; 93185377Ssam} 94185377Ssam 95185377SsamHAL_INT 96185377Ssamar5211GetInterrupts(struct ath_hal *ah) 97185377Ssam{ 98185377Ssam return AH5211(ah)->ah_maskReg; 99185377Ssam} 100185377Ssam 101185377Ssam/* 102185377Ssam * Atomically enables NIC interrupts. Interrupts are passed in 103185377Ssam * via the enumerated bitmask in ints. 104185377Ssam */ 105185377SsamHAL_INT 106185377Ssamar5211SetInterrupts(struct ath_hal *ah, HAL_INT ints) 107185377Ssam{ 108185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 109185377Ssam uint32_t omask = ahp->ah_maskReg; 110185377Ssam uint32_t mask; 111185377Ssam 112185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 113185377Ssam __func__, omask, ints); 114185377Ssam 115185377Ssam /* 116185377Ssam * Disable interrupts here before reading & modifying 117185377Ssam * the mask so that the ISR does not modify the mask 118185377Ssam * out from under us. 119185377Ssam */ 120185377Ssam if (omask & HAL_INT_GLOBAL) { 121185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 122185377Ssam OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 123185377Ssam /* XXX??? */ 124185377Ssam (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ 125185377Ssam } 126185377Ssam 127185377Ssam mask = ints & HAL_INT_COMMON; 128185377Ssam if (ints & HAL_INT_TX) { 129185377Ssam if (ahp->ah_txOkInterruptMask) 130185377Ssam mask |= AR_IMR_TXOK; 131185377Ssam if (ahp->ah_txErrInterruptMask) 132185377Ssam mask |= AR_IMR_TXERR; 133185377Ssam if (ahp->ah_txDescInterruptMask) 134185377Ssam mask |= AR_IMR_TXDESC; 135185377Ssam if (ahp->ah_txEolInterruptMask) 136185377Ssam mask |= AR_IMR_TXEOL; 137185377Ssam } 138185377Ssam if (ints & HAL_INT_RX) 139185377Ssam mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 140185377Ssam if (ints & HAL_INT_FATAL) { 141185377Ssam /* 142185377Ssam * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 143185377Ssam * so enabling HIUERR enables delivery. 144185377Ssam */ 145185377Ssam mask |= AR_IMR_HIUERR; 146185377Ssam } 147185377Ssam 148185377Ssam /* Write the new IMR and store off our SW copy. */ 149185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 150185377Ssam OS_REG_WRITE(ah, AR_IMR, mask); 151185377Ssam ahp->ah_maskReg = ints; 152185377Ssam 153185377Ssam /* Re-enable interrupts as appropriate. */ 154185377Ssam if (ints & HAL_INT_GLOBAL) { 155185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 156185377Ssam OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 157185377Ssam } 158185377Ssam 159185377Ssam return omask; 160185377Ssam} 161