1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2006 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam 24185377Ssam#include "ar5211/ar5211.h" 25185377Ssam#include "ar5211/ar5211reg.h" 26185377Ssam#include "ar5211/ar5211desc.h" 27185377Ssam 28185377Ssam/* 29185377Ssam * Routines used to initialize and generated beacons for the AR5211/AR5311. 30185377Ssam */ 31185377Ssam 32185377Ssam/* 33225444Sadrian * Return the hardware NextTBTT in TSF 34225444Sadrian */ 35225444Sadrianuint64_t 36225444Sadrianar5211GetNextTBTT(struct ath_hal *ah) 37225444Sadrian{ 38225444Sadrian#define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 39225444Sadrian return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 40225444Sadrian#undef TU_TO_TSF 41225444Sadrian} 42225444Sadrian 43225444Sadrian/* 44185377Ssam * Initialize all of the hardware registers used to send beacons. 45185377Ssam */ 46185377Ssamvoid 47185377Ssamar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 48185377Ssam{ 49185377Ssam 50185377Ssam OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); 51185377Ssam OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); 52185377Ssam OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); 53185377Ssam OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); 54185377Ssam /* 55185377Ssam * Set the Beacon register after setting all timers. 56185377Ssam */ 57185377Ssam OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 58185377Ssam} 59185377Ssam 60185377Ssam/* 61185377Ssam * Legacy api to initialize all of the beacon registers. 62185377Ssam */ 63185377Ssamvoid 64185377Ssamar5211BeaconInit(struct ath_hal *ah, 65185377Ssam uint32_t next_beacon, uint32_t beacon_period) 66185377Ssam{ 67185377Ssam HAL_BEACON_TIMERS bt; 68185377Ssam 69185377Ssam bt.bt_nexttbtt = next_beacon; 70185377Ssam /* 71185377Ssam * TIMER1: in AP/adhoc mode this controls the DMA beacon 72185377Ssam * alert timer; otherwise it controls the next wakeup time. 73185377Ssam * TIMER2: in AP mode, it controls the SBA beacon alert 74185377Ssam * interrupt; otherwise it sets the start of the next CFP. 75185377Ssam */ 76185377Ssam switch (AH_PRIVATE(ah)->ah_opmode) { 77185377Ssam case HAL_M_STA: 78185377Ssam case HAL_M_MONITOR: 79185377Ssam bt.bt_nextdba = 0xffff; 80185377Ssam bt.bt_nextswba = 0x7ffff; 81185377Ssam break; 82185377Ssam case HAL_M_IBSS: 83185377Ssam case HAL_M_HOSTAP: 84185377Ssam bt.bt_nextdba = (next_beacon - 85223459Sadrian ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 86185377Ssam bt.bt_nextswba = (next_beacon - 87223459Sadrian ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 88185377Ssam break; 89185377Ssam } 90185377Ssam /* 91185377Ssam * Set the ATIM window 92185377Ssam * Our hardware does not support an ATIM window of 0 93185377Ssam * (beacons will not work). If the ATIM windows is 0, 94185377Ssam * force it to 1. 95185377Ssam */ 96185377Ssam bt.bt_nextatim = next_beacon + 1; 97185377Ssam bt.bt_intval = beacon_period & 98185377Ssam (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 99185377Ssam ar5211SetBeaconTimers(ah, &bt); 100185377Ssam} 101185377Ssam 102185377Ssamvoid 103185377Ssamar5211ResetStaBeaconTimers(struct ath_hal *ah) 104185377Ssam{ 105185377Ssam uint32_t val; 106185377Ssam 107185377Ssam OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 108185377Ssam val = OS_REG_READ(ah, AR_STA_ID1); 109185377Ssam val |= AR_STA_ID1_PWR_SAV; /* XXX */ 110185377Ssam /* tell the h/w that the associated AP is not PCF capable */ 111185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 112185377Ssam val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 113185377Ssam OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 114185377Ssam} 115185377Ssam 116185377Ssam/* 117185377Ssam * Set all the beacon related bits on the h/w for stations 118185377Ssam * i.e. initializes the corresponding h/w timers; 119185377Ssam * also tells the h/w whether to anticipate PCF beacons 120185377Ssam */ 121185377Ssamvoid 122185377Ssamar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 123185377Ssam{ 124185377Ssam struct ath_hal_5211 *ahp = AH5211(ah); 125185377Ssam 126185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__); 127185377Ssam 128185377Ssam HALASSERT(bs->bs_intval != 0); 129185377Ssam /* if the AP will do PCF */ 130185377Ssam if (bs->bs_cfpmaxduration != 0) { 131185377Ssam /* tell the h/w that the associated AP is PCF capable */ 132185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 133185377Ssam OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF); 134185377Ssam 135185377Ssam /* set CFP_PERIOD(1.024ms) register */ 136185377Ssam OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 137185377Ssam 138185377Ssam /* set CFP_DUR(1.024ms) register to max cfp duration */ 139185377Ssam OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 140185377Ssam 141185377Ssam /* set TIMER2(128us) to anticipated time of next CFP */ 142185377Ssam OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 143185377Ssam } else { 144185377Ssam /* tell the h/w that the associated AP is not PCF capable */ 145185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 146185377Ssam OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF); 147185377Ssam } 148185377Ssam 149185377Ssam /* 150185377Ssam * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 151185377Ssam */ 152185377Ssam OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 153185377Ssam 154185377Ssam /* 155185377Ssam * Start the beacon timers by setting the BEACON register 156185377Ssam * to the beacon interval; also write the tim offset which 157185377Ssam * we should know by now. The code, in ar5211WriteAssocid, 158185377Ssam * also sets the tim offset once the AID is known which can 159185377Ssam * be left as such for now. 160185377Ssam */ 161185377Ssam OS_REG_WRITE(ah, AR_BEACON, 162185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 163185377Ssam | SM(bs->bs_intval, AR_BEACON_PERIOD) 164185377Ssam | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 165185377Ssam ); 166185377Ssam 167185377Ssam /* 168185377Ssam * Configure the BMISS interrupt. Note that we 169185377Ssam * assume the caller blocks interrupts while enabling 170185377Ssam * the threshold. 171185377Ssam */ 172185377Ssam HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR)); 173185377Ssam ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 174185377Ssam | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR); 175185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 176185377Ssam 177185377Ssam /* 178185377Ssam * Set the sleep duration in 1/8 TU's. 179185377Ssam */ 180185377Ssam#define SLEEP_SLOP 3 181185377Ssam OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR, 182185377Ssam (bs->bs_sleepduration - SLEEP_SLOP) << 3); 183185377Ssam#undef SLEEP_SLOP 184185377Ssam} 185