1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2004 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17204644Srpaulo * $FreeBSD$ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_desc.h" 24185377Ssam 25185377Ssam#include "ar5210/ar5210.h" 26185377Ssam#include "ar5210/ar5210reg.h" 27185377Ssam#include "ar5210/ar5210desc.h" 28185377Ssam 29185377Ssam/* 30225444Sadrian * Return the hardware NextTBTT in TSF 31225444Sadrian */ 32225444Sadrianuint64_t 33225444Sadrianar5210GetNextTBTT(struct ath_hal *ah) 34225444Sadrian{ 35225444Sadrian#define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 36225444Sadrian return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 37225444Sadrian#undef TU_TO_TSF 38225444Sadrian} 39225444Sadrian 40225444Sadrian/* 41185377Ssam * Initialize all of the hardware registers used to send beacons. 42185377Ssam */ 43185377Ssamvoid 44185377Ssamar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 45185377Ssam{ 46185377Ssam 47185377Ssam OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); 48185377Ssam OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); 49185377Ssam OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); 50185377Ssam OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); 51185377Ssam /* 52185377Ssam * Set the Beacon register after setting all timers. 53185377Ssam */ 54185377Ssam OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 55185377Ssam} 56185377Ssam 57185377Ssam/* 58185377Ssam * Legacy api to Initialize all of the beacon registers. 59185377Ssam */ 60185377Ssamvoid 61185377Ssamar5210BeaconInit(struct ath_hal *ah, 62185377Ssam uint32_t next_beacon, uint32_t beacon_period) 63185377Ssam{ 64185377Ssam HAL_BEACON_TIMERS bt; 65185377Ssam 66185377Ssam bt.bt_nexttbtt = next_beacon; 67185377Ssam 68185377Ssam if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) { 69185377Ssam bt.bt_nextdba = (next_beacon - 70223459Sadrian ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 71185377Ssam bt.bt_nextswba = (next_beacon - 72223459Sadrian ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 73185377Ssam /* 74185377Ssam * The SWBA interrupt is not used for beacons in ad hoc mode 75185377Ssam * as we don't yet support ATIMs. So since the beacon never 76185377Ssam * changes, the beacon descriptor is set up once and read 77185377Ssam * into a special HW buffer, from which it will be 78185377Ssam * automagically retrieved at each DMA Beacon Alert (DBA). 79185377Ssam */ 80185377Ssam 81185377Ssam /* Set the ATIM window */ 82185377Ssam bt.bt_nextatim = next_beacon + 0; /* NB: no ATIMs */ 83185377Ssam } else { 84185377Ssam bt.bt_nextdba = ~0; 85185377Ssam bt.bt_nextswba = ~0; 86185377Ssam bt.bt_nextatim = 1; 87185377Ssam } 88185377Ssam bt.bt_intval = beacon_period & 89185377Ssam (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 90185377Ssam ar5210SetBeaconTimers(ah, &bt); 91185377Ssam} 92185377Ssam 93185377Ssamvoid 94185377Ssamar5210ResetStaBeaconTimers(struct ath_hal *ah) 95185377Ssam{ 96185377Ssam uint32_t val; 97185377Ssam 98185377Ssam OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 99185377Ssam val = OS_REG_READ(ah, AR_STA_ID1); 100185377Ssam val |= AR_STA_ID1_NO_PSPOLL; /* XXX */ 101185377Ssam /* tell the h/w that the associated AP is not PCF capable */ 102185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 103185377Ssam val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 104185377Ssam OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 105185377Ssam} 106185377Ssam 107185377Ssam/* 108185377Ssam * Set all the beacon related bits on the h/w for stations 109185377Ssam * i.e. initializes the corresponding h/w timers; 110185377Ssam * also tells the h/w whether to anticipate PCF beacons 111185377Ssam * 112185377Ssam * dtim_count and cfp_count from the current beacon - their current 113185377Ssam * values aren't necessarily maintained in the device struct 114185377Ssam */ 115185377Ssamvoid 116185377Ssamar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 117185377Ssam{ 118185377Ssam struct ath_hal_5210 *ahp = AH5210(ah); 119185377Ssam 120185377Ssam HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__); 121185377Ssam 122185377Ssam HALASSERT(bs->bs_intval != 0); 123185377Ssam /* if the AP will do PCF */ 124185377Ssam if (bs->bs_cfpmaxduration != 0) { 125185377Ssam /* tell the h/w that the associated AP is PCF capable */ 126185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 127185377Ssam (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA) 128185377Ssam | AR_STA_ID1_PCF); 129185377Ssam 130185377Ssam /* set CFP_PERIOD(1.024ms) register */ 131185377Ssam OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 132185377Ssam 133185377Ssam /* set CFP_DUR(1.024ms) register to max cfp duration */ 134185377Ssam OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 135185377Ssam 136185377Ssam /* set TIMER2(128us) to anticipated time of next CFP */ 137185377Ssam OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 138185377Ssam } else { 139185377Ssam /* tell the h/w that the associated AP is not PCF capable */ 140185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, 141185377Ssam OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 142185377Ssam } 143185377Ssam 144185377Ssam /* 145185377Ssam * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 146185377Ssam */ 147185377Ssam OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 148185377Ssam 149185377Ssam /* 150185377Ssam * Start the beacon timers by setting the BEACON register 151185377Ssam * to the beacon interval; also write the tim offset which 152185377Ssam * we should know by now. The code, in ar5211WriteAssocid, 153185377Ssam * also sets the tim offset once the AID is known which can 154185377Ssam * be left as such for now. 155185377Ssam */ 156185377Ssam OS_REG_WRITE(ah, AR_BEACON, 157185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 158185377Ssam | SM(bs->bs_intval, AR_BEACON_PERIOD) 159185377Ssam | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 160185377Ssam ); 161185377Ssam 162185377Ssam /* 163185377Ssam * Configure the BMISS interrupt. Note that we 164185377Ssam * assume the caller blocks interrupts while enabling 165185377Ssam * the threshold. 166185377Ssam */ 167185377Ssam 168185377Ssam /* 169185377Ssam * Interrupt works only on Crete. 170185377Ssam */ 171185377Ssam if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE) 172185377Ssam return; 173185377Ssam /* 174185377Ssam * Counter is only 3-bits. 175185377Ssam * Count of 0 with BMISS interrupt enabled will hang the system 176185377Ssam * with too many interrupts 177185377Ssam */ 178185377Ssam if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE && 179185377Ssam (bs->bs_bmissthreshold&7) == 0) { 180185377Ssam#ifdef AH_DEBUG 181185377Ssam ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n", 182185377Ssam __func__, bs->bs_bmissthreshold); 183185377Ssam#endif 184185377Ssam return; 185185377Ssam } 186185377Ssam#define BMISS_MAX (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S) 187185377Ssam /* 188185377Ssam * Configure the BMISS interrupt. Note that we 189185377Ssam * assume the caller blocks interrupts while enabling 190185377Ssam * the threshold. 191185377Ssam * 192185377Ssam * NB: the beacon miss count field is only 3 bits which 193185377Ssam * is much smaller than what's found on later parts; 194185377Ssam * clamp overflow values as a safeguard. 195185377Ssam */ 196185377Ssam ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 197185377Ssam | SM(bs->bs_bmissthreshold > BMISS_MAX ? 198185377Ssam BMISS_MAX : bs->bs_bmissthreshold, 199185377Ssam AR_RSSI_THR_BM_THR); 200185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 201185377Ssam#undef BMISS_MAX 202185377Ssam} 203