ah_internal.h revision 277821
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 277821 2015-01-28 04:02:56Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint32_t start; /* first register */ 54 uint32_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_OPS_CONFIG *ah, 95 HAL_STATUS *error); 96}; 97#ifndef AH_CHIP 98#define AH_CHIP(_name, _probe, _attach) \ 99static struct ath_hal_chip _name##_chip = { \ 100 .name = #_name, \ 101 .probe = _probe, \ 102 .attach = _attach \ 103}; \ 104OS_DATA_SET(ah_chips, _name##_chip) 105#endif 106 107/* 108 * Each RF backend registers to offer support; this is mostly 109 * used by multi-chip 5212 solutions. Single-chip solutions 110 * have a fixed idea about which RF to use. 111 */ 112struct ath_hal_rf { 113 const char *name; 114 HAL_BOOL (*probe)(struct ath_hal *ah); 115 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 116}; 117#ifndef AH_RF 118#define AH_RF(_name, _probe, _attach) \ 119static struct ath_hal_rf _name##_rf = { \ 120 .name = __STRING(_name), \ 121 .probe = _probe, \ 122 .attach = _attach \ 123}; \ 124OS_DATA_SET(ah_rfs, _name##_rf) 125#endif 126 127struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 128 129/* 130 * Maximum number of internal channels. Entries are per unique 131 * frequency so this might be need to be increased to handle all 132 * usage cases; typically no more than 32 are really needed but 133 * dynamically allocating the data structures is a bit painful 134 * right now. 135 */ 136#ifndef AH_MAXCHAN 137#define AH_MAXCHAN 96 138#endif 139 140#define HAL_NF_CAL_HIST_LEN_FULL 5 141#define HAL_NF_CAL_HIST_LEN_SMALL 1 142#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 143#define HAL_NF_LOAD_DELAY 1000 144 145/* 146 * PER_CHAN doesn't work for now, as it looks like the device layer 147 * has to pre-populate the per-channel list with nominal values. 148 */ 149//#define ATH_NF_PER_CHAN 1 150 151typedef struct { 152 u_int8_t curr_index; 153 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 154 int16_t priv_nf[HAL_NUM_NF_READINGS]; 155} HAL_NFCAL_BASE; 156 157typedef struct { 158 HAL_NFCAL_BASE base; 159 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 160} HAL_NFCAL_HIST_FULL; 161 162typedef struct { 163 HAL_NFCAL_BASE base; 164 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 165} HAL_NFCAL_HIST_SMALL; 166 167#ifdef ATH_NF_PER_CHAN 168typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 169#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 170#else 171typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 172#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 173#endif /* ATH_NF_PER_CHAN */ 174 175/* 176 * Internal per-channel state. These are found 177 * using ic_devdata in the ieee80211_channel. 178 */ 179typedef struct { 180 uint16_t channel; /* h/w frequency, NB: may be mapped */ 181 uint8_t privFlags; 182#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 183#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 184#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 185#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 186 uint8_t calValid; /* bitmask of cal types */ 187 int8_t iCoff; 188 int8_t qCoff; 189 int16_t rawNoiseFloor; 190 int16_t noiseFloorAdjust; 191#ifdef AH_SUPPORT_AR5416 192 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 193 int16_t noiseFloorExt[AH_MAX_CHAINS]; 194#endif /* AH_SUPPORT_AR5416 */ 195 uint16_t mainSpur; /* cached spur value for this channel */ 196 197 /*XXX TODO: make these part of privFlags */ 198 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 199 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 200 int one_time_cals_done; 201 HAL_CHAN_NFCAL_HIST nf_cal_hist; 202} HAL_CHANNEL_INTERNAL; 203 204/* channel requires noise floor check */ 205#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 206 207/* all full-width channels */ 208#define IEEE80211_CHAN_ALLFULL \ 209 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 210#define IEEE80211_CHAN_ALLTURBOFULL \ 211 (IEEE80211_CHAN_ALLTURBO - \ 212 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 213 214typedef struct { 215 uint32_t halChanSpreadSupport : 1, 216 halSleepAfterBeaconBroken : 1, 217 halCompressSupport : 1, 218 halBurstSupport : 1, 219 halFastFramesSupport : 1, 220 halChapTuningSupport : 1, 221 halTurboGSupport : 1, 222 halTurboPrimeSupport : 1, 223 halMicAesCcmSupport : 1, 224 halMicCkipSupport : 1, 225 halMicTkipSupport : 1, 226 halTkipMicTxRxKeySupport : 1, 227 halCipherAesCcmSupport : 1, 228 halCipherCkipSupport : 1, 229 halCipherTkipSupport : 1, 230 halPSPollBroken : 1, 231 halVEOLSupport : 1, 232 halBssIdMaskSupport : 1, 233 halMcastKeySrchSupport : 1, 234 halTsfAddSupport : 1, 235 halChanHalfRate : 1, 236 halChanQuarterRate : 1, 237 halHTSupport : 1, 238 halHTSGI20Support : 1, 239 halRfSilentSupport : 1, 240 halHwPhyCounterSupport : 1, 241 halWowSupport : 1, 242 halWowMatchPatternExact : 1, 243 halAutoSleepSupport : 1, 244 halFastCCSupport : 1, 245 halBtCoexSupport : 1; 246 uint32_t halRxStbcSupport : 1, 247 halTxStbcSupport : 1, 248 halGTTSupport : 1, 249 halCSTSupport : 1, 250 halRifsRxSupport : 1, 251 halRifsTxSupport : 1, 252 hal4AddrAggrSupport : 1, 253 halExtChanDfsSupport : 1, 254 halUseCombinedRadarRssi : 1, 255 halForcePpmSupport : 1, 256 halEnhancedPmSupport : 1, 257 halEnhancedDfsSupport : 1, 258 halMbssidAggrSupport : 1, 259 halBssidMatchSupport : 1, 260 hal4kbSplitTransSupport : 1, 261 halHasRxSelfLinkedTail : 1, 262 halSupportsFastClock5GHz : 1, 263 halHasLongRxDescTsf : 1, 264 halHasBBReadWar : 1, 265 halSerialiseRegWar : 1, 266 halMciSupport : 1, 267 halRxTxAbortSupport : 1, 268 halPaprdEnabled : 1, 269 halHasUapsdSupport : 1, 270 halWpsPushButtonSupport : 1, 271 halBtCoexApsmWar : 1, 272 halGenTimerSupport : 1, 273 halLDPCSupport : 1, 274 halHwBeaconProcSupport : 1, 275 halEnhancedDmaSupport : 1; 276 uint32_t halIsrRacSupport : 1, 277 halApmEnable : 1, 278 halIntrMitigation : 1, 279 hal49GhzSupport : 1, 280 halAntDivCombSupport : 1, 281 halAntDivCombSupportOrg : 1, 282 halRadioRetentionSupport : 1, 283 halSpectralScanSupport : 1, 284 halRxUsingLnaMixing : 1, 285 halRxDoMyBeacon : 1, 286 halHwUapsdTrig : 1; 287 288 uint32_t halWirelessModes; 289 uint16_t halTotalQueues; 290 uint16_t halKeyCacheSize; 291 uint16_t halLow5GhzChan, halHigh5GhzChan; 292 uint16_t halLow2GhzChan, halHigh2GhzChan; 293 int halTstampPrecision; 294 int halRtsAggrLimit; 295 uint8_t halTxChainMask; 296 uint8_t halRxChainMask; 297 uint8_t halNumGpioPins; 298 uint8_t halNumAntCfg2GHz; 299 uint8_t halNumAntCfg5GHz; 300 uint32_t halIntrMask; 301 uint8_t halTxStreams; 302 uint8_t halRxStreams; 303 HAL_MFP_OPT_T halMfpSupport; 304 305 /* AR9300 HAL porting capabilities */ 306 int hal_paprd_enabled; 307 int hal_pcie_lcr_offset; 308 int hal_pcie_lcr_extsync_en; 309 int halNumTxMaps; 310 int halTxDescLen; 311 int halTxStatusLen; 312 int halRxStatusLen; 313 int halRxHpFifoDepth; 314 int halRxLpFifoDepth; 315 uint32_t halRegCap; /* XXX needed? */ 316 int halNumMRRetries; 317 int hal_ani_poll_interval; 318 int hal_channel_switch_time_usec; 319} HAL_CAPABILITIES; 320 321struct regDomain; 322 323/* 324 * Definitions for ah_flags in ath_hal_private 325 */ 326#define AH_USE_EEPROM 0x1 327#define AH_IS_HB63 0x2 328 329/* 330 * The ``private area'' follows immediately after the ``public area'' 331 * in the data structure returned by ath_hal_attach. Private data are 332 * used by device-independent code such as the regulatory domain support. 333 * In general, code within the HAL should never depend on data in the 334 * public area. Instead any public data needed internally should be 335 * shadowed here. 336 * 337 * When declaring a device-specific ath_hal data structure this structure 338 * is assumed to at the front; e.g. 339 * 340 * struct ath_hal_5212 { 341 * struct ath_hal_private ah_priv; 342 * ... 343 * }; 344 * 345 * It might be better to manage the method pointers in this structure 346 * using an indirect pointer to a read-only data structure but this would 347 * disallow class-style method overriding. 348 */ 349struct ath_hal_private { 350 struct ath_hal h; /* public area */ 351 352 /* NB: all methods go first to simplify initialization */ 353 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 354 uint16_t channelFlags, 355 uint16_t *lowChannel, uint16_t *highChannel); 356 u_int (*ah_getWirelessModes)(struct ath_hal*); 357 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 358 uint16_t *data); 359 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 360 uint16_t data); 361 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 362 struct ieee80211_channel *); 363 int16_t (*ah_getNfAdjust)(struct ath_hal *, 364 const HAL_CHANNEL_INTERNAL*); 365 void (*ah_getNoiseFloor)(struct ath_hal *, 366 int16_t nfarray[]); 367 368 void *ah_eeprom; /* opaque EEPROM state */ 369 uint16_t ah_eeversion; /* EEPROM version */ 370 void (*ah_eepromDetach)(struct ath_hal *); 371 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 372 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 373 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 374 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 375 const void *args, uint32_t argsize, 376 void **result, uint32_t *resultsize); 377 378 /* 379 * Device revision information. 380 */ 381 uint16_t ah_devid; /* PCI device ID */ 382 uint16_t ah_subvendorid; /* PCI subvendor ID */ 383 uint32_t ah_macVersion; /* MAC version id */ 384 uint16_t ah_macRev; /* MAC revision */ 385 uint16_t ah_phyRev; /* PHY revision */ 386 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 387 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 388 uint32_t ah_flags; /* misc flags */ 389 uint8_t ah_ispcie; /* PCIE, special treatment */ 390 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 391 392 HAL_OPMODE ah_opmode; /* operating mode from reset */ 393 const struct ieee80211_channel *ah_curchan;/* operating channel */ 394 HAL_CAPABILITIES ah_caps; /* device capabilities */ 395 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 396 int16_t ah_powerLimit; /* tx power cap */ 397 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 398 u_int ah_tpScale; /* tx power scale factor */ 399 u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 400 uint32_t ah_11nCompat; /* 11n compat controls */ 401 402 /* 403 * State for regulatory domain handling. 404 */ 405 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 406 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 407 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 408 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 409 u_int ah_nchan; /* valid items in ah_channels */ 410 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 411 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 412 413 uint8_t ah_coverageClass; /* coverage class */ 414 /* 415 * RF Silent handling; setup according to the EEPROM. 416 */ 417 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 418 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 419 /* 420 * Diagnostic support for discriminating HIUERR reports. 421 */ 422 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 423 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 424 425#ifndef ATH_NF_PER_CHAN 426 HAL_NFCAL_HIST_FULL nf_cal_hist; 427#endif /* ! ATH_NF_PER_CHAN */ 428}; 429 430#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 431 432#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 433 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 434#define ath_hal_getWirelessModes(_ah) \ 435 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 436#define ath_hal_eepromRead(_ah, _off, _data) \ 437 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 438#define ath_hal_eepromWrite(_ah, _off, _data) \ 439 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 440#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 441 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 442#define ath_hal_gpioCfgInput(_ah, _gpio) \ 443 (_ah)->ah_gpioCfgInput(_ah, _gpio) 444#define ath_hal_gpioGet(_ah, _gpio) \ 445 (_ah)->ah_gpioGet(_ah, _gpio) 446#define ath_hal_gpioSet(_ah, _gpio, _val) \ 447 (_ah)->ah_gpioSet(_ah, _gpio, _val) 448#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 449 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 450#define ath_hal_getpowerlimits(_ah, _chan) \ 451 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 452#define ath_hal_getNfAdjust(_ah, _c) \ 453 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 454#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 455 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 456#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 457 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 458#define ath_hal_disablePCIE(_ah) \ 459 (_ah)->ah_disablePCIE(_ah) 460#define ath_hal_setInterrupts(_ah, _mask) \ 461 (_ah)->ah_setInterrupts(_ah, _mask) 462 463#define ath_hal_isrfkillenabled(_ah) \ 464 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 465#define ath_hal_enable_rfkill(_ah, _v) \ 466 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 467#define ath_hal_hasrfkill_int(_ah) \ 468 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 469 470#define ath_hal_eepromDetach(_ah) do { \ 471 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 472 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 473} while (0) 474#define ath_hal_eepromGet(_ah, _param, _val) \ 475 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 476#define ath_hal_eepromSet(_ah, _param, _val) \ 477 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 478#define ath_hal_eepromGetFlag(_ah, _param) \ 479 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 480#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 481 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 482#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 483 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 484 485#ifndef _NET_IF_IEEE80211_H_ 486/* 487 * Stuff that would naturally come from _ieee80211.h 488 */ 489#define IEEE80211_ADDR_LEN 6 490 491#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 492#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 493#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 494 495#define IEEE80211_CRC_LEN 4 496 497#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 498 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 499#endif /* _NET_IF_IEEE80211_H_ */ 500 501#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 502 503#define INIT_AIFS 2 504#define INIT_CWMIN 15 505#define INIT_CWMIN_11B 31 506#define INIT_CWMAX 1023 507#define INIT_SH_RETRY 10 508#define INIT_LG_RETRY 10 509#define INIT_SSH_RETRY 32 510#define INIT_SLG_RETRY 32 511 512typedef struct { 513 uint32_t tqi_ver; /* HAL TXQ verson */ 514 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 515 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 516 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 517 uint32_t tqi_priority; 518 uint32_t tqi_aifs; /* aifs */ 519 uint32_t tqi_cwmin; /* cwMin */ 520 uint32_t tqi_cwmax; /* cwMax */ 521 uint16_t tqi_shretry; /* frame short retry limit */ 522 uint16_t tqi_lgretry; /* frame long retry limit */ 523 uint32_t tqi_cbrPeriod; 524 uint32_t tqi_cbrOverflowLimit; 525 uint32_t tqi_burstTime; 526 uint32_t tqi_readyTime; 527 uint32_t tqi_physCompBuf; 528 uint32_t tqi_intFlags; /* flags for internal use */ 529} HAL_TX_QUEUE_INFO; 530 531extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 532 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 533extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 534 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 535 536#define HAL_SPUR_VAL_MASK 0x3FFF 537#define HAL_SPUR_CHAN_WIDTH 87 538#define HAL_BIN_WIDTH_BASE_100HZ 3125 539#define HAL_BIN_WIDTH_TURBO_100HZ 6250 540#define HAL_MAX_BINS_ALLOWED 28 541 542#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 543#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 544 545#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 546 547/* 548 * Deduce if the host cpu has big- or litt-endian byte order. 549 */ 550static __inline__ int 551isBigEndian(void) 552{ 553 union { 554 int32_t i; 555 char c[4]; 556 } u; 557 u.i = 1; 558 return (u.c[0] == 0); 559} 560 561/* unalligned little endian access */ 562#define LE_READ_2(p) \ 563 ((uint16_t) \ 564 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 565#define LE_READ_4(p) \ 566 ((uint32_t) \ 567 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 568 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 569 570/* 571 * Register manipulation macros that expect bit field defines 572 * to follow the convention that an _S suffix is appended for 573 * a shift count, while the field mask has no suffix. 574 */ 575#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 576#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 577#define OS_REG_RMW(_a, _r, _set, _clr) \ 578 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 579#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 580 OS_REG_WRITE(_a, _r, \ 581 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 582#define OS_REG_SET_BIT(_a, _r, _f) \ 583 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 584#define OS_REG_CLR_BIT(_a, _r, _f) \ 585 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 586#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 587 ((OS_REG_READ(_a, _r) & (_f)) != 0) 588#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 589 OS_REG_WRITE(_a, _r, \ 590 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 591 (((_v) << _f##_S) & (_f<<_f##_S))) 592#define OS_REG_READ_FIELD(_a, _r, _f) \ 593 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 594#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 595 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 596 597/* Analog register writes may require a delay between each one (eg Merlin?) */ 598#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 599 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 600 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 601#define OS_A_REG_WRITE(_a, _r, _v) \ 602 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 603 604/* wait for the register contents to have the specified value */ 605extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 606 uint32_t mask, uint32_t val); 607extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 608 uint32_t mask, uint32_t val, uint32_t timeout); 609 610/* return the first n bits in val reversed */ 611extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 612 613/* printf interfaces */ 614extern void ath_hal_printf(struct ath_hal *, const char*, ...) 615 __printflike(2,3); 616extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 617 __printflike(2, 0); 618extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 619 620/* allocate and free memory */ 621extern void *ath_hal_malloc(size_t); 622extern void ath_hal_free(void *); 623 624/* common debugging interfaces */ 625#ifdef AH_DEBUG 626#include "ah_debug.h" 627extern int ath_hal_debug; /* Global debug flags */ 628 629/* 630 * The typecast is purely because some callers will pass in 631 * AH_NULL directly rather than using a NULL ath_hal pointer. 632 */ 633#define HALDEBUG(_ah, __m, ...) \ 634 do { \ 635 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 636 ath_hal_debug & (__m) || \ 637 ((_ah) != NULL && \ 638 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 639 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 640 } \ 641 } while(0); 642 643extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 644 __printflike(3,4); 645#else 646#define HALDEBUG(_ah, __m, ...) 647#endif /* AH_DEBUG */ 648 649/* 650 * Register logging definitions shared with ardecode. 651 */ 652#include "ah_decode.h" 653 654/* 655 * Common assertion interface. Note: it is a bad idea to generate 656 * an assertion failure for any recoverable event. Instead catch 657 * the violation and, if possible, fix it up or recover from it; either 658 * with an error return value or a diagnostic messages. System software 659 * does not panic unless the situation is hopeless. 660 */ 661#ifdef AH_ASSERT 662extern void ath_hal_assert_failed(const char* filename, 663 int lineno, const char* msg); 664 665#define HALASSERT(_x) do { \ 666 if (!(_x)) { \ 667 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 668 } \ 669} while (0) 670#else 671#define HALASSERT(_x) 672#endif /* AH_ASSERT */ 673 674/* 675 * Regulatory domain support. 676 */ 677 678/* 679 * Return the max allowed antenna gain and apply any regulatory 680 * domain specific changes. 681 */ 682u_int ath_hal_getantennareduction(struct ath_hal *ah, 683 const struct ieee80211_channel *chan, u_int twiceGain); 684 685/* 686 * Return the test group for the specific channel based on 687 * the current regulatory setup. 688 */ 689u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 690 691/* 692 * Map a public channel definition to the corresponding 693 * internal data structure. This implicitly specifies 694 * whether or not the specified channel is ok to use 695 * based on the current regulatory domain constraints. 696 */ 697#ifndef AH_DEBUG 698static OS_INLINE HAL_CHANNEL_INTERNAL * 699ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 700{ 701 HAL_CHANNEL_INTERNAL *cc; 702 703 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 704 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 705 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 706 return cc; 707} 708#else 709/* NB: non-inline version that checks state */ 710HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 711 const struct ieee80211_channel *); 712#endif /* AH_DEBUG */ 713 714/* 715 * Return the h/w frequency for a channel. This may be 716 * different from ic_freq if this is a GSM device that 717 * takes 2.4GHz frequencies and down-converts them. 718 */ 719static OS_INLINE uint16_t 720ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 721{ 722 return ath_hal_checkchannel(ah, c)->channel; 723} 724 725/* 726 * Convert between microseconds and core system clocks. 727 */ 728extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 729extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 730 731/* 732 * Generic get/set capability support. Each chip overrides 733 * this routine to support chip-specific capabilities. 734 */ 735extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 736 HAL_CAPABILITY_TYPE type, uint32_t capability, 737 uint32_t *result); 738extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 739 HAL_CAPABILITY_TYPE type, uint32_t capability, 740 uint32_t setting, HAL_STATUS *status); 741 742/* The diagnostic codes used to be internally defined here -adrian */ 743#include "ah_diagcodes.h" 744 745/* 746 * The AR5416 and later HALs have MAC and baseband hang checking. 747 */ 748typedef struct { 749 uint32_t hang_reg_offset; 750 uint32_t hang_val; 751 uint32_t hang_mask; 752 uint32_t hang_offset; 753} hal_hw_hang_check_t; 754 755typedef struct { 756 uint32_t dma_dbg_3; 757 uint32_t dma_dbg_4; 758 uint32_t dma_dbg_5; 759 uint32_t dma_dbg_6; 760} mac_dbg_regs_t; 761 762typedef enum { 763 dcu_chain_state = 0x1, 764 dcu_complete_state = 0x2, 765 qcu_state = 0x4, 766 qcu_fsp_ok = 0x8, 767 qcu_fsp_state = 0x10, 768 qcu_stitch_state = 0x20, 769 qcu_fetch_state = 0x40, 770 qcu_complete_state = 0x80 771} hal_mac_hangs_t; 772 773typedef struct { 774 int states; 775 uint8_t dcu_chain_state; 776 uint8_t dcu_complete_state; 777 uint8_t qcu_state; 778 uint8_t qcu_fsp_ok; 779 uint8_t qcu_fsp_state; 780 uint8_t qcu_stitch_state; 781 uint8_t qcu_fetch_state; 782 uint8_t qcu_complete_state; 783} hal_mac_hang_check_t; 784 785enum { 786 HAL_BB_HANG_DFS = 0x0001, 787 HAL_BB_HANG_RIFS = 0x0002, 788 HAL_BB_HANG_RX_CLEAR = 0x0004, 789 HAL_BB_HANG_UNKNOWN = 0x0080, 790 791 HAL_MAC_HANG_SIG1 = 0x0100, 792 HAL_MAC_HANG_SIG2 = 0x0200, 793 HAL_MAC_HANG_UNKNOWN = 0x8000, 794 795 HAL_BB_HANGS = HAL_BB_HANG_DFS 796 | HAL_BB_HANG_RIFS 797 | HAL_BB_HANG_RX_CLEAR 798 | HAL_BB_HANG_UNKNOWN, 799 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 800 | HAL_MAC_HANG_SIG2 801 | HAL_MAC_HANG_UNKNOWN, 802}; 803 804/* Merge these with above */ 805typedef enum hal_hw_hangs { 806 HAL_DFS_BB_HANG_WAR = 0x1, 807 HAL_RIFS_BB_HANG_WAR = 0x2, 808 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 809 HAL_MAC_HANG_WAR = 0x8, 810 HAL_PHYRESTART_CLR_WAR = 0x10, 811 HAL_MAC_HANG_DETECTED = 0x40000000, 812 HAL_BB_HANG_DETECTED = 0x80000000 813} hal_hw_hangs_t; 814 815/* 816 * Device revision information. 817 */ 818typedef struct { 819 uint16_t ah_devid; /* PCI device ID */ 820 uint16_t ah_subvendorid; /* PCI subvendor ID */ 821 uint32_t ah_macVersion; /* MAC version id */ 822 uint16_t ah_macRev; /* MAC revision */ 823 uint16_t ah_phyRev; /* PHY revision */ 824 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 825 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 826} HAL_REVS; 827 828/* 829 * Argument payload for HAL_DIAG_SETKEY. 830 */ 831typedef struct { 832 HAL_KEYVAL dk_keyval; 833 uint16_t dk_keyix; /* key index */ 834 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 835 int dk_xor; /* XOR key data */ 836} HAL_DIAG_KEYVAL; 837 838/* 839 * Argument payload for HAL_DIAG_EEWRITE. 840 */ 841typedef struct { 842 uint16_t ee_off; /* eeprom offset */ 843 uint16_t ee_data; /* write data */ 844} HAL_DIAG_EEVAL; 845 846 847typedef struct { 848 u_int offset; /* reg offset */ 849 uint32_t val; /* reg value */ 850} HAL_DIAG_REGVAL; 851 852/* 853 * 11n compatibility tweaks. 854 */ 855#define HAL_DIAG_11N_SERVICES 0x00000003 856#define HAL_DIAG_11N_SERVICES_S 0 857#define HAL_DIAG_11N_TXSTOMP 0x0000000c 858#define HAL_DIAG_11N_TXSTOMP_S 2 859 860typedef struct { 861 int maxNoiseImmunityLevel; /* [0..4] */ 862 int totalSizeDesired[5]; 863 int coarseHigh[5]; 864 int coarseLow[5]; 865 int firpwr[5]; 866 867 int maxSpurImmunityLevel; /* [0..7] */ 868 int cycPwrThr1[8]; 869 870 int maxFirstepLevel; /* [0..2] */ 871 int firstep[3]; 872 873 uint32_t ofdmTrigHigh; 874 uint32_t ofdmTrigLow; 875 int32_t cckTrigHigh; 876 int32_t cckTrigLow; 877 int32_t rssiThrLow; 878 int32_t rssiThrHigh; 879 880 int period; /* update listen period */ 881} HAL_ANI_PARAMS; 882 883extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 884 const void *args, uint32_t argsize, 885 void **result, uint32_t *resultsize); 886 887/* 888 * Setup a h/w rate table for use. 889 */ 890extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 891 892/* 893 * Common routine for implementing getChanNoise api. 894 */ 895int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 896 897/* 898 * Initialization support. 899 */ 900typedef struct { 901 const uint32_t *data; 902 int rows, cols; 903} HAL_INI_ARRAY; 904 905#define HAL_INI_INIT(_ia, _data, _cols) do { \ 906 (_ia)->data = (const uint32_t *)(_data); \ 907 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 908 (_ia)->cols = (_cols); \ 909} while (0) 910#define HAL_INI_VAL(_ia, _r, _c) \ 911 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 912 913/* 914 * OS_DELAY() does a PIO READ on the PCI bus which allows 915 * other cards' DMA reads to complete in the middle of our reset. 916 */ 917#define DMA_YIELD(x) do { \ 918 if ((++(x) % 64) == 0) \ 919 OS_DELAY(1); \ 920} while (0) 921 922#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 923 int r; \ 924 for (r = 0; r < N(regArray); r++) { \ 925 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 926 DMA_YIELD(regWr); \ 927 } \ 928} while (0) 929 930#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 931 int r; \ 932 for (r = 0; r < N(regArray); r++) { \ 933 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 934 DMA_YIELD(regWr); \ 935 } \ 936} while (0) 937 938extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 939 int col, int regWr); 940extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 941 int col); 942extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 943 const uint32_t data[], int regWr); 944 945#define CCK_SIFS_TIME 10 946#define CCK_PREAMBLE_BITS 144 947#define CCK_PLCP_BITS 48 948 949#define OFDM_SIFS_TIME 16 950#define OFDM_PREAMBLE_TIME 20 951#define OFDM_PLCP_BITS 22 952#define OFDM_SYMBOL_TIME 4 953 954#define OFDM_HALF_SIFS_TIME 32 955#define OFDM_HALF_PREAMBLE_TIME 40 956#define OFDM_HALF_PLCP_BITS 22 957#define OFDM_HALF_SYMBOL_TIME 8 958 959#define OFDM_QUARTER_SIFS_TIME 64 960#define OFDM_QUARTER_PREAMBLE_TIME 80 961#define OFDM_QUARTER_PLCP_BITS 22 962#define OFDM_QUARTER_SYMBOL_TIME 16 963 964#define TURBO_SIFS_TIME 8 965#define TURBO_PREAMBLE_TIME 14 966#define TURBO_PLCP_BITS 22 967#define TURBO_SYMBOL_TIME 4 968 969#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 970 971/* Generic EEPROM board value functions */ 972extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 973 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 974extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 975 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 976 uint8_t *pRetVpdList); 977extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 978 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 979 980/* Whether 5ghz fast clock is needed */ 981/* 982 * The chipset (Merlin, AR9300/later) should set the capability flag below; 983 * this flag simply says that the hardware can do it, not that the EEPROM 984 * says it can. 985 * 986 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 987 * if the relevant eeprom flag is set. 988 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 989 * by default. 990 */ 991#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 992 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 993 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 994 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 995 996/* 997 * Fetch the maximum regulatory domain power for the given channel 998 * in 1/2dBm steps. 999 */ 1000static inline int 1001ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 1002 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 1003{ 1004 struct ath_hal *ah = &ahp->h; 1005 1006 if (! chan) { 1007 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1008 return (0); 1009 } 1010 return (chan->ic_maxpower); 1011} 1012 1013/* 1014 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1015 */ 1016static inline int 1017ath_hal_getantennaallowed(struct ath_hal *ah, 1018 const struct ieee80211_channel *chan) 1019{ 1020 1021 if (! chan) 1022 return (0); 1023 1024 return (chan->ic_maxantgain); 1025} 1026 1027/* 1028 * Map the given 2GHz channel to an IEEE number. 1029 */ 1030extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 1031 1032#endif /* _ATH_AH_INTERAL_H_ */ 1033