ah_internal.h revision 272292
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 272292 2014-09-30 03:19:29Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint32_t start; /* first register */ 54 uint32_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_OPS_CONFIG *ah, 95 HAL_STATUS *error); 96}; 97#ifndef AH_CHIP 98#define AH_CHIP(_name, _probe, _attach) \ 99static struct ath_hal_chip _name##_chip = { \ 100 .name = #_name, \ 101 .probe = _probe, \ 102 .attach = _attach \ 103}; \ 104OS_DATA_SET(ah_chips, _name##_chip) 105#endif 106 107/* 108 * Each RF backend registers to offer support; this is mostly 109 * used by multi-chip 5212 solutions. Single-chip solutions 110 * have a fixed idea about which RF to use. 111 */ 112struct ath_hal_rf { 113 const char *name; 114 HAL_BOOL (*probe)(struct ath_hal *ah); 115 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 116}; 117#ifndef AH_RF 118#define AH_RF(_name, _probe, _attach) \ 119static struct ath_hal_rf _name##_rf = { \ 120 .name = __STRING(_name), \ 121 .probe = _probe, \ 122 .attach = _attach \ 123}; \ 124OS_DATA_SET(ah_rfs, _name##_rf) 125#endif 126 127struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 128 129/* 130 * Maximum number of internal channels. Entries are per unique 131 * frequency so this might be need to be increased to handle all 132 * usage cases; typically no more than 32 are really needed but 133 * dynamically allocating the data structures is a bit painful 134 * right now. 135 */ 136#ifndef AH_MAXCHAN 137#define AH_MAXCHAN 96 138#endif 139 140#define HAL_NF_CAL_HIST_LEN_FULL 5 141#define HAL_NF_CAL_HIST_LEN_SMALL 1 142#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 143#define HAL_NF_LOAD_DELAY 1000 144 145/* 146 * PER_CHAN doesn't work for now, as it looks like the device layer 147 * has to pre-populate the per-channel list with nominal values. 148 */ 149//#define ATH_NF_PER_CHAN 1 150 151typedef struct { 152 u_int8_t curr_index; 153 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 154 int16_t priv_nf[HAL_NUM_NF_READINGS]; 155} HAL_NFCAL_BASE; 156 157typedef struct { 158 HAL_NFCAL_BASE base; 159 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 160} HAL_NFCAL_HIST_FULL; 161 162typedef struct { 163 HAL_NFCAL_BASE base; 164 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 165} HAL_NFCAL_HIST_SMALL; 166 167#ifdef ATH_NF_PER_CHAN 168typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 169#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 170#else 171typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 172#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 173#endif /* ATH_NF_PER_CHAN */ 174 175/* 176 * Internal per-channel state. These are found 177 * using ic_devdata in the ieee80211_channel. 178 */ 179typedef struct { 180 uint16_t channel; /* h/w frequency, NB: may be mapped */ 181 uint8_t privFlags; 182#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 183#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 184#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 185#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 186 uint8_t calValid; /* bitmask of cal types */ 187 int8_t iCoff; 188 int8_t qCoff; 189 int16_t rawNoiseFloor; 190 int16_t noiseFloorAdjust; 191#ifdef AH_SUPPORT_AR5416 192 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 193 int16_t noiseFloorExt[AH_MAX_CHAINS]; 194#endif /* AH_SUPPORT_AR5416 */ 195 uint16_t mainSpur; /* cached spur value for this channel */ 196 197 /*XXX TODO: make these part of privFlags */ 198 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 199 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 200 int one_time_cals_done; 201 HAL_CHAN_NFCAL_HIST nf_cal_hist; 202} HAL_CHANNEL_INTERNAL; 203 204/* channel requires noise floor check */ 205#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 206 207/* all full-width channels */ 208#define IEEE80211_CHAN_ALLFULL \ 209 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 210#define IEEE80211_CHAN_ALLTURBOFULL \ 211 (IEEE80211_CHAN_ALLTURBO - \ 212 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 213 214typedef struct { 215 uint32_t halChanSpreadSupport : 1, 216 halSleepAfterBeaconBroken : 1, 217 halCompressSupport : 1, 218 halBurstSupport : 1, 219 halFastFramesSupport : 1, 220 halChapTuningSupport : 1, 221 halTurboGSupport : 1, 222 halTurboPrimeSupport : 1, 223 halMicAesCcmSupport : 1, 224 halMicCkipSupport : 1, 225 halMicTkipSupport : 1, 226 halTkipMicTxRxKeySupport : 1, 227 halCipherAesCcmSupport : 1, 228 halCipherCkipSupport : 1, 229 halCipherTkipSupport : 1, 230 halPSPollBroken : 1, 231 halVEOLSupport : 1, 232 halBssIdMaskSupport : 1, 233 halMcastKeySrchSupport : 1, 234 halTsfAddSupport : 1, 235 halChanHalfRate : 1, 236 halChanQuarterRate : 1, 237 halHTSupport : 1, 238 halHTSGI20Support : 1, 239 halRfSilentSupport : 1, 240 halHwPhyCounterSupport : 1, 241 halWowSupport : 1, 242 halWowMatchPatternExact : 1, 243 halAutoSleepSupport : 1, 244 halFastCCSupport : 1, 245 halBtCoexSupport : 1; 246 uint32_t halRxStbcSupport : 1, 247 halTxStbcSupport : 1, 248 halGTTSupport : 1, 249 halCSTSupport : 1, 250 halRifsRxSupport : 1, 251 halRifsTxSupport : 1, 252 hal4AddrAggrSupport : 1, 253 halExtChanDfsSupport : 1, 254 halUseCombinedRadarRssi : 1, 255 halForcePpmSupport : 1, 256 halEnhancedPmSupport : 1, 257 halEnhancedDfsSupport : 1, 258 halMbssidAggrSupport : 1, 259 halBssidMatchSupport : 1, 260 hal4kbSplitTransSupport : 1, 261 halHasRxSelfLinkedTail : 1, 262 halSupportsFastClock5GHz : 1, 263 halHasLongRxDescTsf : 1, 264 halHasBBReadWar : 1, 265 halSerialiseRegWar : 1, 266 halMciSupport : 1, 267 halRxTxAbortSupport : 1, 268 halPaprdEnabled : 1, 269 halHasUapsdSupport : 1, 270 halWpsPushButtonSupport : 1, 271 halBtCoexApsmWar : 1, 272 halGenTimerSupport : 1, 273 halLDPCSupport : 1, 274 halHwBeaconProcSupport : 1, 275 halEnhancedDmaSupport : 1; 276 uint32_t halIsrRacSupport : 1, 277 halApmEnable : 1, 278 halIntrMitigation : 1, 279 hal49GhzSupport : 1, 280 halAntDivCombSupport : 1, 281 halAntDivCombSupportOrg : 1, 282 halRadioRetentionSupport : 1, 283 halSpectralScanSupport : 1, 284 halRxUsingLnaMixing : 1, 285 halRxDoMyBeacon : 1; 286 287 uint32_t halWirelessModes; 288 uint16_t halTotalQueues; 289 uint16_t halKeyCacheSize; 290 uint16_t halLow5GhzChan, halHigh5GhzChan; 291 uint16_t halLow2GhzChan, halHigh2GhzChan; 292 int halTstampPrecision; 293 int halRtsAggrLimit; 294 uint8_t halTxChainMask; 295 uint8_t halRxChainMask; 296 uint8_t halNumGpioPins; 297 uint8_t halNumAntCfg2GHz; 298 uint8_t halNumAntCfg5GHz; 299 uint32_t halIntrMask; 300 uint8_t halTxStreams; 301 uint8_t halRxStreams; 302 HAL_MFP_OPT_T halMfpSupport; 303 304 /* AR9300 HAL porting capabilities */ 305 int hal_paprd_enabled; 306 int hal_pcie_lcr_offset; 307 int hal_pcie_lcr_extsync_en; 308 int halNumTxMaps; 309 int halTxDescLen; 310 int halTxStatusLen; 311 int halRxStatusLen; 312 int halRxHpFifoDepth; 313 int halRxLpFifoDepth; 314 uint32_t halRegCap; /* XXX needed? */ 315 int halNumMRRetries; 316 int hal_ani_poll_interval; 317 int hal_channel_switch_time_usec; 318} HAL_CAPABILITIES; 319 320struct regDomain; 321 322/* 323 * Definitions for ah_flags in ath_hal_private 324 */ 325#define AH_USE_EEPROM 0x1 326#define AH_IS_HB63 0x2 327 328/* 329 * The ``private area'' follows immediately after the ``public area'' 330 * in the data structure returned by ath_hal_attach. Private data are 331 * used by device-independent code such as the regulatory domain support. 332 * In general, code within the HAL should never depend on data in the 333 * public area. Instead any public data needed internally should be 334 * shadowed here. 335 * 336 * When declaring a device-specific ath_hal data structure this structure 337 * is assumed to at the front; e.g. 338 * 339 * struct ath_hal_5212 { 340 * struct ath_hal_private ah_priv; 341 * ... 342 * }; 343 * 344 * It might be better to manage the method pointers in this structure 345 * using an indirect pointer to a read-only data structure but this would 346 * disallow class-style method overriding. 347 */ 348struct ath_hal_private { 349 struct ath_hal h; /* public area */ 350 351 /* NB: all methods go first to simplify initialization */ 352 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 353 uint16_t channelFlags, 354 uint16_t *lowChannel, uint16_t *highChannel); 355 u_int (*ah_getWirelessModes)(struct ath_hal*); 356 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 357 uint16_t *data); 358 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 359 uint16_t data); 360 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 361 struct ieee80211_channel *); 362 int16_t (*ah_getNfAdjust)(struct ath_hal *, 363 const HAL_CHANNEL_INTERNAL*); 364 void (*ah_getNoiseFloor)(struct ath_hal *, 365 int16_t nfarray[]); 366 367 void *ah_eeprom; /* opaque EEPROM state */ 368 uint16_t ah_eeversion; /* EEPROM version */ 369 void (*ah_eepromDetach)(struct ath_hal *); 370 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 371 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 372 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 373 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 374 const void *args, uint32_t argsize, 375 void **result, uint32_t *resultsize); 376 377 /* 378 * Device revision information. 379 */ 380 uint16_t ah_devid; /* PCI device ID */ 381 uint16_t ah_subvendorid; /* PCI subvendor ID */ 382 uint32_t ah_macVersion; /* MAC version id */ 383 uint16_t ah_macRev; /* MAC revision */ 384 uint16_t ah_phyRev; /* PHY revision */ 385 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 386 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 387 uint32_t ah_flags; /* misc flags */ 388 uint8_t ah_ispcie; /* PCIE, special treatment */ 389 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 390 391 HAL_OPMODE ah_opmode; /* operating mode from reset */ 392 const struct ieee80211_channel *ah_curchan;/* operating channel */ 393 HAL_CAPABILITIES ah_caps; /* device capabilities */ 394 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 395 int16_t ah_powerLimit; /* tx power cap */ 396 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 397 u_int ah_tpScale; /* tx power scale factor */ 398 u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 399 uint32_t ah_11nCompat; /* 11n compat controls */ 400 401 /* 402 * State for regulatory domain handling. 403 */ 404 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 405 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 406 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 407 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 408 u_int ah_nchan; /* valid items in ah_channels */ 409 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 410 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 411 412 uint8_t ah_coverageClass; /* coverage class */ 413 /* 414 * RF Silent handling; setup according to the EEPROM. 415 */ 416 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 417 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 418 /* 419 * Diagnostic support for discriminating HIUERR reports. 420 */ 421 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 422 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 423 424#ifndef ATH_NF_PER_CHAN 425 HAL_NFCAL_HIST_FULL nf_cal_hist; 426#endif /* ! ATH_NF_PER_CHAN */ 427}; 428 429#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 430 431#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 432 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 433#define ath_hal_getWirelessModes(_ah) \ 434 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 435#define ath_hal_eepromRead(_ah, _off, _data) \ 436 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 437#define ath_hal_eepromWrite(_ah, _off, _data) \ 438 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 439#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 440 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 441#define ath_hal_gpioCfgInput(_ah, _gpio) \ 442 (_ah)->ah_gpioCfgInput(_ah, _gpio) 443#define ath_hal_gpioGet(_ah, _gpio) \ 444 (_ah)->ah_gpioGet(_ah, _gpio) 445#define ath_hal_gpioSet(_ah, _gpio, _val) \ 446 (_ah)->ah_gpioSet(_ah, _gpio, _val) 447#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 448 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 449#define ath_hal_getpowerlimits(_ah, _chan) \ 450 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 451#define ath_hal_getNfAdjust(_ah, _c) \ 452 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 453#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 454 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 455#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 456 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 457#define ath_hal_disablePCIE(_ah) \ 458 (_ah)->ah_disablePCIE(_ah) 459#define ath_hal_setInterrupts(_ah, _mask) \ 460 (_ah)->ah_setInterrupts(_ah, _mask) 461 462#define ath_hal_isrfkillenabled(_ah) \ 463 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 464#define ath_hal_enable_rfkill(_ah, _v) \ 465 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 466#define ath_hal_hasrfkill_int(_ah) \ 467 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 468 469#define ath_hal_eepromDetach(_ah) do { \ 470 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 471 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 472} while (0) 473#define ath_hal_eepromGet(_ah, _param, _val) \ 474 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 475#define ath_hal_eepromSet(_ah, _param, _val) \ 476 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 477#define ath_hal_eepromGetFlag(_ah, _param) \ 478 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 479#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 480 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 481#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 482 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 483 484#ifndef _NET_IF_IEEE80211_H_ 485/* 486 * Stuff that would naturally come from _ieee80211.h 487 */ 488#define IEEE80211_ADDR_LEN 6 489 490#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 491#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 492#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 493 494#define IEEE80211_CRC_LEN 4 495 496#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 497 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 498#endif /* _NET_IF_IEEE80211_H_ */ 499 500#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 501 502#define INIT_AIFS 2 503#define INIT_CWMIN 15 504#define INIT_CWMIN_11B 31 505#define INIT_CWMAX 1023 506#define INIT_SH_RETRY 10 507#define INIT_LG_RETRY 10 508#define INIT_SSH_RETRY 32 509#define INIT_SLG_RETRY 32 510 511typedef struct { 512 uint32_t tqi_ver; /* HAL TXQ verson */ 513 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 514 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 515 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 516 uint32_t tqi_priority; 517 uint32_t tqi_aifs; /* aifs */ 518 uint32_t tqi_cwmin; /* cwMin */ 519 uint32_t tqi_cwmax; /* cwMax */ 520 uint16_t tqi_shretry; /* frame short retry limit */ 521 uint16_t tqi_lgretry; /* frame long retry limit */ 522 uint32_t tqi_cbrPeriod; 523 uint32_t tqi_cbrOverflowLimit; 524 uint32_t tqi_burstTime; 525 uint32_t tqi_readyTime; 526 uint32_t tqi_physCompBuf; 527 uint32_t tqi_intFlags; /* flags for internal use */ 528} HAL_TX_QUEUE_INFO; 529 530extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 531 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 532extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 533 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 534 535#define HAL_SPUR_VAL_MASK 0x3FFF 536#define HAL_SPUR_CHAN_WIDTH 87 537#define HAL_BIN_WIDTH_BASE_100HZ 3125 538#define HAL_BIN_WIDTH_TURBO_100HZ 6250 539#define HAL_MAX_BINS_ALLOWED 28 540 541#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 542#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 543 544#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 545 546/* 547 * Deduce if the host cpu has big- or litt-endian byte order. 548 */ 549static __inline__ int 550isBigEndian(void) 551{ 552 union { 553 int32_t i; 554 char c[4]; 555 } u; 556 u.i = 1; 557 return (u.c[0] == 0); 558} 559 560/* unalligned little endian access */ 561#define LE_READ_2(p) \ 562 ((uint16_t) \ 563 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 564#define LE_READ_4(p) \ 565 ((uint32_t) \ 566 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 567 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 568 569/* 570 * Register manipulation macros that expect bit field defines 571 * to follow the convention that an _S suffix is appended for 572 * a shift count, while the field mask has no suffix. 573 */ 574#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 575#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 576#define OS_REG_RMW(_a, _r, _set, _clr) \ 577 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 578#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 579 OS_REG_WRITE(_a, _r, \ 580 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 581#define OS_REG_SET_BIT(_a, _r, _f) \ 582 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 583#define OS_REG_CLR_BIT(_a, _r, _f) \ 584 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 585#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 586 ((OS_REG_READ(_a, _r) & (_f)) != 0) 587#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 588 OS_REG_WRITE(_a, _r, \ 589 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 590 (((_v) << _f##_S) & (_f<<_f##_S))) 591#define OS_REG_READ_FIELD(_a, _r, _f) \ 592 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 593#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 594 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 595 596/* Analog register writes may require a delay between each one (eg Merlin?) */ 597#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 598 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 599 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 600#define OS_A_REG_WRITE(_a, _r, _v) \ 601 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 602 603/* wait for the register contents to have the specified value */ 604extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 605 uint32_t mask, uint32_t val); 606extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 607 uint32_t mask, uint32_t val, uint32_t timeout); 608 609/* return the first n bits in val reversed */ 610extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 611 612/* printf interfaces */ 613extern void ath_hal_printf(struct ath_hal *, const char*, ...) 614 __printflike(2,3); 615extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 616 __printflike(2, 0); 617extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 618 619/* allocate and free memory */ 620extern void *ath_hal_malloc(size_t); 621extern void ath_hal_free(void *); 622 623/* common debugging interfaces */ 624#ifdef AH_DEBUG 625#include "ah_debug.h" 626extern int ath_hal_debug; /* Global debug flags */ 627 628/* 629 * The typecast is purely because some callers will pass in 630 * AH_NULL directly rather than using a NULL ath_hal pointer. 631 */ 632#define HALDEBUG(_ah, __m, ...) \ 633 do { \ 634 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 635 ath_hal_debug & (__m) || \ 636 ((_ah) != NULL && \ 637 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 638 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 639 } \ 640 } while(0); 641 642extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 643 __printflike(3,4); 644#else 645#define HALDEBUG(_ah, __m, ...) 646#endif /* AH_DEBUG */ 647 648/* 649 * Register logging definitions shared with ardecode. 650 */ 651#include "ah_decode.h" 652 653/* 654 * Common assertion interface. Note: it is a bad idea to generate 655 * an assertion failure for any recoverable event. Instead catch 656 * the violation and, if possible, fix it up or recover from it; either 657 * with an error return value or a diagnostic messages. System software 658 * does not panic unless the situation is hopeless. 659 */ 660#ifdef AH_ASSERT 661extern void ath_hal_assert_failed(const char* filename, 662 int lineno, const char* msg); 663 664#define HALASSERT(_x) do { \ 665 if (!(_x)) { \ 666 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 667 } \ 668} while (0) 669#else 670#define HALASSERT(_x) 671#endif /* AH_ASSERT */ 672 673/* 674 * Regulatory domain support. 675 */ 676 677/* 678 * Return the max allowed antenna gain and apply any regulatory 679 * domain specific changes. 680 */ 681u_int ath_hal_getantennareduction(struct ath_hal *ah, 682 const struct ieee80211_channel *chan, u_int twiceGain); 683 684/* 685 * Return the test group for the specific channel based on 686 * the current regulatory setup. 687 */ 688u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 689 690/* 691 * Map a public channel definition to the corresponding 692 * internal data structure. This implicitly specifies 693 * whether or not the specified channel is ok to use 694 * based on the current regulatory domain constraints. 695 */ 696#ifndef AH_DEBUG 697static OS_INLINE HAL_CHANNEL_INTERNAL * 698ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 699{ 700 HAL_CHANNEL_INTERNAL *cc; 701 702 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 703 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 704 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 705 return cc; 706} 707#else 708/* NB: non-inline version that checks state */ 709HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 710 const struct ieee80211_channel *); 711#endif /* AH_DEBUG */ 712 713/* 714 * Return the h/w frequency for a channel. This may be 715 * different from ic_freq if this is a GSM device that 716 * takes 2.4GHz frequencies and down-converts them. 717 */ 718static OS_INLINE uint16_t 719ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 720{ 721 return ath_hal_checkchannel(ah, c)->channel; 722} 723 724/* 725 * Convert between microseconds and core system clocks. 726 */ 727extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 728extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 729 730/* 731 * Generic get/set capability support. Each chip overrides 732 * this routine to support chip-specific capabilities. 733 */ 734extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 735 HAL_CAPABILITY_TYPE type, uint32_t capability, 736 uint32_t *result); 737extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 738 HAL_CAPABILITY_TYPE type, uint32_t capability, 739 uint32_t setting, HAL_STATUS *status); 740 741/* The diagnostic codes used to be internally defined here -adrian */ 742#include "ah_diagcodes.h" 743 744/* 745 * The AR5416 and later HALs have MAC and baseband hang checking. 746 */ 747typedef struct { 748 uint32_t hang_reg_offset; 749 uint32_t hang_val; 750 uint32_t hang_mask; 751 uint32_t hang_offset; 752} hal_hw_hang_check_t; 753 754typedef struct { 755 uint32_t dma_dbg_3; 756 uint32_t dma_dbg_4; 757 uint32_t dma_dbg_5; 758 uint32_t dma_dbg_6; 759} mac_dbg_regs_t; 760 761typedef enum { 762 dcu_chain_state = 0x1, 763 dcu_complete_state = 0x2, 764 qcu_state = 0x4, 765 qcu_fsp_ok = 0x8, 766 qcu_fsp_state = 0x10, 767 qcu_stitch_state = 0x20, 768 qcu_fetch_state = 0x40, 769 qcu_complete_state = 0x80 770} hal_mac_hangs_t; 771 772typedef struct { 773 int states; 774 uint8_t dcu_chain_state; 775 uint8_t dcu_complete_state; 776 uint8_t qcu_state; 777 uint8_t qcu_fsp_ok; 778 uint8_t qcu_fsp_state; 779 uint8_t qcu_stitch_state; 780 uint8_t qcu_fetch_state; 781 uint8_t qcu_complete_state; 782} hal_mac_hang_check_t; 783 784enum { 785 HAL_BB_HANG_DFS = 0x0001, 786 HAL_BB_HANG_RIFS = 0x0002, 787 HAL_BB_HANG_RX_CLEAR = 0x0004, 788 HAL_BB_HANG_UNKNOWN = 0x0080, 789 790 HAL_MAC_HANG_SIG1 = 0x0100, 791 HAL_MAC_HANG_SIG2 = 0x0200, 792 HAL_MAC_HANG_UNKNOWN = 0x8000, 793 794 HAL_BB_HANGS = HAL_BB_HANG_DFS 795 | HAL_BB_HANG_RIFS 796 | HAL_BB_HANG_RX_CLEAR 797 | HAL_BB_HANG_UNKNOWN, 798 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 799 | HAL_MAC_HANG_SIG2 800 | HAL_MAC_HANG_UNKNOWN, 801}; 802 803/* Merge these with above */ 804typedef enum hal_hw_hangs { 805 HAL_DFS_BB_HANG_WAR = 0x1, 806 HAL_RIFS_BB_HANG_WAR = 0x2, 807 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 808 HAL_MAC_HANG_WAR = 0x8, 809 HAL_PHYRESTART_CLR_WAR = 0x10, 810 HAL_MAC_HANG_DETECTED = 0x40000000, 811 HAL_BB_HANG_DETECTED = 0x80000000 812} hal_hw_hangs_t; 813 814/* 815 * Device revision information. 816 */ 817typedef struct { 818 uint16_t ah_devid; /* PCI device ID */ 819 uint16_t ah_subvendorid; /* PCI subvendor ID */ 820 uint32_t ah_macVersion; /* MAC version id */ 821 uint16_t ah_macRev; /* MAC revision */ 822 uint16_t ah_phyRev; /* PHY revision */ 823 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 824 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 825} HAL_REVS; 826 827/* 828 * Argument payload for HAL_DIAG_SETKEY. 829 */ 830typedef struct { 831 HAL_KEYVAL dk_keyval; 832 uint16_t dk_keyix; /* key index */ 833 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 834 int dk_xor; /* XOR key data */ 835} HAL_DIAG_KEYVAL; 836 837/* 838 * Argument payload for HAL_DIAG_EEWRITE. 839 */ 840typedef struct { 841 uint16_t ee_off; /* eeprom offset */ 842 uint16_t ee_data; /* write data */ 843} HAL_DIAG_EEVAL; 844 845 846typedef struct { 847 u_int offset; /* reg offset */ 848 uint32_t val; /* reg value */ 849} HAL_DIAG_REGVAL; 850 851/* 852 * 11n compatibility tweaks. 853 */ 854#define HAL_DIAG_11N_SERVICES 0x00000003 855#define HAL_DIAG_11N_SERVICES_S 0 856#define HAL_DIAG_11N_TXSTOMP 0x0000000c 857#define HAL_DIAG_11N_TXSTOMP_S 2 858 859typedef struct { 860 int maxNoiseImmunityLevel; /* [0..4] */ 861 int totalSizeDesired[5]; 862 int coarseHigh[5]; 863 int coarseLow[5]; 864 int firpwr[5]; 865 866 int maxSpurImmunityLevel; /* [0..7] */ 867 int cycPwrThr1[8]; 868 869 int maxFirstepLevel; /* [0..2] */ 870 int firstep[3]; 871 872 uint32_t ofdmTrigHigh; 873 uint32_t ofdmTrigLow; 874 int32_t cckTrigHigh; 875 int32_t cckTrigLow; 876 int32_t rssiThrLow; 877 int32_t rssiThrHigh; 878 879 int period; /* update listen period */ 880} HAL_ANI_PARAMS; 881 882extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 883 const void *args, uint32_t argsize, 884 void **result, uint32_t *resultsize); 885 886/* 887 * Setup a h/w rate table for use. 888 */ 889extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 890 891/* 892 * Common routine for implementing getChanNoise api. 893 */ 894int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 895 896/* 897 * Initialization support. 898 */ 899typedef struct { 900 const uint32_t *data; 901 int rows, cols; 902} HAL_INI_ARRAY; 903 904#define HAL_INI_INIT(_ia, _data, _cols) do { \ 905 (_ia)->data = (const uint32_t *)(_data); \ 906 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 907 (_ia)->cols = (_cols); \ 908} while (0) 909#define HAL_INI_VAL(_ia, _r, _c) \ 910 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 911 912/* 913 * OS_DELAY() does a PIO READ on the PCI bus which allows 914 * other cards' DMA reads to complete in the middle of our reset. 915 */ 916#define DMA_YIELD(x) do { \ 917 if ((++(x) % 64) == 0) \ 918 OS_DELAY(1); \ 919} while (0) 920 921#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 922 int r; \ 923 for (r = 0; r < N(regArray); r++) { \ 924 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 925 DMA_YIELD(regWr); \ 926 } \ 927} while (0) 928 929#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 930 int r; \ 931 for (r = 0; r < N(regArray); r++) { \ 932 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 933 DMA_YIELD(regWr); \ 934 } \ 935} while (0) 936 937extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 938 int col, int regWr); 939extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 940 int col); 941extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 942 const uint32_t data[], int regWr); 943 944#define CCK_SIFS_TIME 10 945#define CCK_PREAMBLE_BITS 144 946#define CCK_PLCP_BITS 48 947 948#define OFDM_SIFS_TIME 16 949#define OFDM_PREAMBLE_TIME 20 950#define OFDM_PLCP_BITS 22 951#define OFDM_SYMBOL_TIME 4 952 953#define OFDM_HALF_SIFS_TIME 32 954#define OFDM_HALF_PREAMBLE_TIME 40 955#define OFDM_HALF_PLCP_BITS 22 956#define OFDM_HALF_SYMBOL_TIME 8 957 958#define OFDM_QUARTER_SIFS_TIME 64 959#define OFDM_QUARTER_PREAMBLE_TIME 80 960#define OFDM_QUARTER_PLCP_BITS 22 961#define OFDM_QUARTER_SYMBOL_TIME 16 962 963#define TURBO_SIFS_TIME 8 964#define TURBO_PREAMBLE_TIME 14 965#define TURBO_PLCP_BITS 22 966#define TURBO_SYMBOL_TIME 4 967 968#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 969 970/* Generic EEPROM board value functions */ 971extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 972 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 973extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 974 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 975 uint8_t *pRetVpdList); 976extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 977 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 978 979/* Whether 5ghz fast clock is needed */ 980/* 981 * The chipset (Merlin, AR9300/later) should set the capability flag below; 982 * this flag simply says that the hardware can do it, not that the EEPROM 983 * says it can. 984 * 985 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 986 * if the relevant eeprom flag is set. 987 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 988 * by default. 989 */ 990#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 991 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 992 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 993 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 994 995/* 996 * Fetch the maximum regulatory domain power for the given channel 997 * in 1/2dBm steps. 998 */ 999static inline int 1000ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 1001 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 1002{ 1003 struct ath_hal *ah = &ahp->h; 1004 1005 if (! chan) { 1006 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1007 return (0); 1008 } 1009 return (chan->ic_maxpower); 1010} 1011 1012/* 1013 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1014 */ 1015static inline int 1016ath_hal_getantennaallowed(struct ath_hal *ah, 1017 const struct ieee80211_channel *chan) 1018{ 1019 1020 if (! chan) 1021 return (0); 1022 1023 return (chan->ic_maxantgain); 1024} 1025 1026/* 1027 * Map the given 2GHz channel to an IEEE number. 1028 */ 1029extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 1030 1031#endif /* _ATH_AH_INTERAL_H_ */ 1032