ah_internal.h revision 252236
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 252236 2013-06-26 04:46:03Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_STATUS *error); 95}; 96#ifndef AH_CHIP 97#define AH_CHIP(_name, _probe, _attach) \ 98static struct ath_hal_chip _name##_chip = { \ 99 .name = #_name, \ 100 .probe = _probe, \ 101 .attach = _attach \ 102}; \ 103OS_DATA_SET(ah_chips, _name##_chip) 104#endif 105 106/* 107 * Each RF backend registers to offer support; this is mostly 108 * used by multi-chip 5212 solutions. Single-chip solutions 109 * have a fixed idea about which RF to use. 110 */ 111struct ath_hal_rf { 112 const char *name; 113 HAL_BOOL (*probe)(struct ath_hal *ah); 114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 115}; 116#ifndef AH_RF 117#define AH_RF(_name, _probe, _attach) \ 118static struct ath_hal_rf _name##_rf = { \ 119 .name = __STRING(_name), \ 120 .probe = _probe, \ 121 .attach = _attach \ 122}; \ 123OS_DATA_SET(ah_rfs, _name##_rf) 124#endif 125 126struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 127 128/* 129 * Maximum number of internal channels. Entries are per unique 130 * frequency so this might be need to be increased to handle all 131 * usage cases; typically no more than 32 are really needed but 132 * dynamically allocating the data structures is a bit painful 133 * right now. 134 */ 135#ifndef AH_MAXCHAN 136#define AH_MAXCHAN 96 137#endif 138 139#define HAL_NF_CAL_HIST_LEN_FULL 5 140#define HAL_NF_CAL_HIST_LEN_SMALL 1 141#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 142#define HAL_NF_LOAD_DELAY 1000 143 144/* 145 * PER_CHAN doesn't work for now, as it looks like the device layer 146 * has to pre-populate the per-channel list with nominal values. 147 */ 148//#define ATH_NF_PER_CHAN 1 149 150typedef struct { 151 u_int8_t curr_index; 152 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 153 int16_t priv_nf[HAL_NUM_NF_READINGS]; 154} HAL_NFCAL_BASE; 155 156typedef struct { 157 HAL_NFCAL_BASE base; 158 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 159} HAL_NFCAL_HIST_FULL; 160 161typedef struct { 162 HAL_NFCAL_BASE base; 163 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 164} HAL_NFCAL_HIST_SMALL; 165 166#ifdef ATH_NF_PER_CHAN 167typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 168#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 169#else 170typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 171#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 172#endif /* ATH_NF_PER_CHAN */ 173 174/* 175 * Internal per-channel state. These are found 176 * using ic_devdata in the ieee80211_channel. 177 */ 178typedef struct { 179 uint16_t channel; /* h/w frequency, NB: may be mapped */ 180 uint8_t privFlags; 181#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 182#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 183#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 184#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 185 uint8_t calValid; /* bitmask of cal types */ 186 int8_t iCoff; 187 int8_t qCoff; 188 int16_t rawNoiseFloor; 189 int16_t noiseFloorAdjust; 190#ifdef AH_SUPPORT_AR5416 191 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 192 int16_t noiseFloorExt[AH_MAX_CHAINS]; 193#endif /* AH_SUPPORT_AR5416 */ 194 uint16_t mainSpur; /* cached spur value for this channel */ 195 196 /*XXX TODO: make these part of privFlags */ 197 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 198 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 199 int one_time_cals_done; 200 HAL_CHAN_NFCAL_HIST nf_cal_hist; 201} HAL_CHANNEL_INTERNAL; 202 203/* channel requires noise floor check */ 204#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 205 206/* all full-width channels */ 207#define IEEE80211_CHAN_ALLFULL \ 208 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 209#define IEEE80211_CHAN_ALLTURBOFULL \ 210 (IEEE80211_CHAN_ALLTURBO - \ 211 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 212 213typedef struct { 214 uint32_t halChanSpreadSupport : 1, 215 halSleepAfterBeaconBroken : 1, 216 halCompressSupport : 1, 217 halBurstSupport : 1, 218 halFastFramesSupport : 1, 219 halChapTuningSupport : 1, 220 halTurboGSupport : 1, 221 halTurboPrimeSupport : 1, 222 halMicAesCcmSupport : 1, 223 halMicCkipSupport : 1, 224 halMicTkipSupport : 1, 225 halTkipMicTxRxKeySupport : 1, 226 halCipherAesCcmSupport : 1, 227 halCipherCkipSupport : 1, 228 halCipherTkipSupport : 1, 229 halPSPollBroken : 1, 230 halVEOLSupport : 1, 231 halBssIdMaskSupport : 1, 232 halMcastKeySrchSupport : 1, 233 halTsfAddSupport : 1, 234 halChanHalfRate : 1, 235 halChanQuarterRate : 1, 236 halHTSupport : 1, 237 halHTSGI20Support : 1, 238 halRfSilentSupport : 1, 239 halHwPhyCounterSupport : 1, 240 halWowSupport : 1, 241 halWowMatchPatternExact : 1, 242 halAutoSleepSupport : 1, 243 halFastCCSupport : 1, 244 halBtCoexSupport : 1; 245 uint32_t halRxStbcSupport : 1, 246 halTxStbcSupport : 1, 247 halGTTSupport : 1, 248 halCSTSupport : 1, 249 halRifsRxSupport : 1, 250 halRifsTxSupport : 1, 251 hal4AddrAggrSupport : 1, 252 halExtChanDfsSupport : 1, 253 halUseCombinedRadarRssi : 1, 254 halForcePpmSupport : 1, 255 halEnhancedPmSupport : 1, 256 halEnhancedDfsSupport : 1, 257 halMbssidAggrSupport : 1, 258 halBssidMatchSupport : 1, 259 hal4kbSplitTransSupport : 1, 260 halHasRxSelfLinkedTail : 1, 261 halSupportsFastClock5GHz : 1, 262 halHasLongRxDescTsf : 1, 263 halHasBBReadWar : 1, 264 halSerialiseRegWar : 1, 265 halMciSupport : 1, 266 halRxTxAbortSupport : 1, 267 halPaprdEnabled : 1, 268 halHasUapsdSupport : 1, 269 halWpsPushButtonSupport : 1, 270 halBtCoexApsmWar : 1, 271 halGenTimerSupport : 1, 272 halLDPCSupport : 1, 273 halHwBeaconProcSupport : 1, 274 halEnhancedDmaSupport : 1; 275 uint32_t halIsrRacSupport : 1, 276 halApmEnable : 1, 277 halIntrMitigation : 1, 278 hal49GhzSupport : 1, 279 halAntDivCombSupport : 1, 280 halAntDivCombSupportOrg : 1, 281 halRadioRetentionSupport : 1, 282 halSpectralScanSupport : 1, 283 halRxUsingLnaMixing : 1; 284 285 uint32_t halWirelessModes; 286 uint16_t halTotalQueues; 287 uint16_t halKeyCacheSize; 288 uint16_t halLow5GhzChan, halHigh5GhzChan; 289 uint16_t halLow2GhzChan, halHigh2GhzChan; 290 int halTstampPrecision; 291 int halRtsAggrLimit; 292 uint8_t halTxChainMask; 293 uint8_t halRxChainMask; 294 uint8_t halNumGpioPins; 295 uint8_t halNumAntCfg2GHz; 296 uint8_t halNumAntCfg5GHz; 297 uint32_t halIntrMask; 298 uint8_t halTxStreams; 299 uint8_t halRxStreams; 300 HAL_MFP_OPT_T halMfpSupport; 301 302 /* AR9300 HAL porting capabilities */ 303 int hal_paprd_enabled; 304 int hal_pcie_lcr_offset; 305 int hal_pcie_lcr_extsync_en; 306 int halNumTxMaps; 307 int halTxDescLen; 308 int halTxStatusLen; 309 int halRxStatusLen; 310 int halRxHpFifoDepth; 311 int halRxLpFifoDepth; 312 uint32_t halRegCap; /* XXX needed? */ 313 int halNumMRRetries; 314 int hal_ani_poll_interval; 315 int hal_channel_switch_time_usec; 316} HAL_CAPABILITIES; 317 318struct regDomain; 319 320/* 321 * Definitions for ah_flags in ath_hal_private 322 */ 323#define AH_USE_EEPROM 0x1 324#define AH_IS_HB63 0x2 325 326/* 327 * The ``private area'' follows immediately after the ``public area'' 328 * in the data structure returned by ath_hal_attach. Private data are 329 * used by device-independent code such as the regulatory domain support. 330 * In general, code within the HAL should never depend on data in the 331 * public area. Instead any public data needed internally should be 332 * shadowed here. 333 * 334 * When declaring a device-specific ath_hal data structure this structure 335 * is assumed to at the front; e.g. 336 * 337 * struct ath_hal_5212 { 338 * struct ath_hal_private ah_priv; 339 * ... 340 * }; 341 * 342 * It might be better to manage the method pointers in this structure 343 * using an indirect pointer to a read-only data structure but this would 344 * disallow class-style method overriding. 345 */ 346struct ath_hal_private { 347 struct ath_hal h; /* public area */ 348 349 /* NB: all methods go first to simplify initialization */ 350 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 351 uint16_t channelFlags, 352 uint16_t *lowChannel, uint16_t *highChannel); 353 u_int (*ah_getWirelessModes)(struct ath_hal*); 354 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 355 uint16_t *data); 356 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 357 uint16_t data); 358 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 359 struct ieee80211_channel *); 360 int16_t (*ah_getNfAdjust)(struct ath_hal *, 361 const HAL_CHANNEL_INTERNAL*); 362 void (*ah_getNoiseFloor)(struct ath_hal *, 363 int16_t nfarray[]); 364 365 void *ah_eeprom; /* opaque EEPROM state */ 366 uint16_t ah_eeversion; /* EEPROM version */ 367 void (*ah_eepromDetach)(struct ath_hal *); 368 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 369 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 370 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 371 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 372 const void *args, uint32_t argsize, 373 void **result, uint32_t *resultsize); 374 375 /* 376 * Device revision information. 377 */ 378 uint16_t ah_devid; /* PCI device ID */ 379 uint16_t ah_subvendorid; /* PCI subvendor ID */ 380 uint32_t ah_macVersion; /* MAC version id */ 381 uint16_t ah_macRev; /* MAC revision */ 382 uint16_t ah_phyRev; /* PHY revision */ 383 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 384 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 385 uint32_t ah_flags; /* misc flags */ 386 uint8_t ah_ispcie; /* PCIE, special treatment */ 387 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 388 389 HAL_OPMODE ah_opmode; /* operating mode from reset */ 390 const struct ieee80211_channel *ah_curchan;/* operating channel */ 391 HAL_CAPABILITIES ah_caps; /* device capabilities */ 392 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 393 int16_t ah_powerLimit; /* tx power cap */ 394 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 395 u_int ah_tpScale; /* tx power scale factor */ 396 u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 397 uint32_t ah_11nCompat; /* 11n compat controls */ 398 399 /* 400 * State for regulatory domain handling. 401 */ 402 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 403 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 404 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 405 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 406 u_int ah_nchan; /* valid items in ah_channels */ 407 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 408 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 409 410 uint8_t ah_coverageClass; /* coverage class */ 411 /* 412 * RF Silent handling; setup according to the EEPROM. 413 */ 414 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 415 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 416 /* 417 * Diagnostic support for discriminating HIUERR reports. 418 */ 419 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 420 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 421 422#ifndef ATH_NF_PER_CHAN 423 HAL_NFCAL_HIST_FULL nf_cal_hist; 424#endif /* ! ATH_NF_PER_CHAN */ 425}; 426 427#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 428 429#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 430 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 431#define ath_hal_getWirelessModes(_ah) \ 432 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 433#define ath_hal_eepromRead(_ah, _off, _data) \ 434 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 435#define ath_hal_eepromWrite(_ah, _off, _data) \ 436 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 437#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 438 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 439#define ath_hal_gpioCfgInput(_ah, _gpio) \ 440 (_ah)->ah_gpioCfgInput(_ah, _gpio) 441#define ath_hal_gpioGet(_ah, _gpio) \ 442 (_ah)->ah_gpioGet(_ah, _gpio) 443#define ath_hal_gpioSet(_ah, _gpio, _val) \ 444 (_ah)->ah_gpioSet(_ah, _gpio, _val) 445#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 446 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 447#define ath_hal_getpowerlimits(_ah, _chan) \ 448 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 449#define ath_hal_getNfAdjust(_ah, _c) \ 450 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 451#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 452 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 453#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 454 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 455#define ath_hal_disablePCIE(_ah) \ 456 (_ah)->ah_disablePCIE(_ah) 457#define ath_hal_setInterrupts(_ah, _mask) \ 458 (_ah)->ah_setInterrupts(_ah, _mask) 459 460#define ath_hal_isrfkillenabled(_ah) \ 461 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 462#define ath_hal_enable_rfkill(_ah, _v) \ 463 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 464#define ath_hal_hasrfkill_int(_ah) \ 465 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 466 467#define ath_hal_eepromDetach(_ah) do { \ 468 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 469 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 470} while (0) 471#define ath_hal_eepromGet(_ah, _param, _val) \ 472 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 473#define ath_hal_eepromSet(_ah, _param, _val) \ 474 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 475#define ath_hal_eepromGetFlag(_ah, _param) \ 476 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 477#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 478 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 479#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 480 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 481 482#ifndef _NET_IF_IEEE80211_H_ 483/* 484 * Stuff that would naturally come from _ieee80211.h 485 */ 486#define IEEE80211_ADDR_LEN 6 487 488#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 489#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 490#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 491 492#define IEEE80211_CRC_LEN 4 493 494#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 495 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 496#endif /* _NET_IF_IEEE80211_H_ */ 497 498#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 499 500#define INIT_AIFS 2 501#define INIT_CWMIN 15 502#define INIT_CWMIN_11B 31 503#define INIT_CWMAX 1023 504#define INIT_SH_RETRY 10 505#define INIT_LG_RETRY 10 506#define INIT_SSH_RETRY 32 507#define INIT_SLG_RETRY 32 508 509typedef struct { 510 uint32_t tqi_ver; /* HAL TXQ verson */ 511 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 512 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 513 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 514 uint32_t tqi_priority; 515 uint32_t tqi_aifs; /* aifs */ 516 uint32_t tqi_cwmin; /* cwMin */ 517 uint32_t tqi_cwmax; /* cwMax */ 518 uint16_t tqi_shretry; /* frame short retry limit */ 519 uint16_t tqi_lgretry; /* frame long retry limit */ 520 uint32_t tqi_cbrPeriod; 521 uint32_t tqi_cbrOverflowLimit; 522 uint32_t tqi_burstTime; 523 uint32_t tqi_readyTime; 524 uint32_t tqi_physCompBuf; 525 uint32_t tqi_intFlags; /* flags for internal use */ 526} HAL_TX_QUEUE_INFO; 527 528extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 529 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 530extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 531 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 532 533#define HAL_SPUR_VAL_MASK 0x3FFF 534#define HAL_SPUR_CHAN_WIDTH 87 535#define HAL_BIN_WIDTH_BASE_100HZ 3125 536#define HAL_BIN_WIDTH_TURBO_100HZ 6250 537#define HAL_MAX_BINS_ALLOWED 28 538 539#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 540#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 541 542#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 543 544/* 545 * Deduce if the host cpu has big- or litt-endian byte order. 546 */ 547static __inline__ int 548isBigEndian(void) 549{ 550 union { 551 int32_t i; 552 char c[4]; 553 } u; 554 u.i = 1; 555 return (u.c[0] == 0); 556} 557 558/* unalligned little endian access */ 559#define LE_READ_2(p) \ 560 ((uint16_t) \ 561 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 562#define LE_READ_4(p) \ 563 ((uint32_t) \ 564 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 565 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 566 567/* 568 * Register manipulation macros that expect bit field defines 569 * to follow the convention that an _S suffix is appended for 570 * a shift count, while the field mask has no suffix. 571 */ 572#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 573#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 574#define OS_REG_RMW(_a, _r, _set, _clr) \ 575 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 576#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 577 OS_REG_WRITE(_a, _r, \ 578 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 579#define OS_REG_SET_BIT(_a, _r, _f) \ 580 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 581#define OS_REG_CLR_BIT(_a, _r, _f) \ 582 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 583#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 584 ((OS_REG_READ(_a, _r) & (_f)) != 0) 585#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 586 OS_REG_WRITE(_a, _r, \ 587 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 588 (((_v) << _f##_S) & (_f<<_f##_S))) 589#define OS_REG_READ_FIELD(_a, _r, _f) \ 590 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 591#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 592 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 593 594/* Analog register writes may require a delay between each one (eg Merlin?) */ 595#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 596 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 597 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 598#define OS_A_REG_WRITE(_a, _r, _v) \ 599 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 600 601/* wait for the register contents to have the specified value */ 602extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 603 uint32_t mask, uint32_t val); 604extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 605 uint32_t mask, uint32_t val, uint32_t timeout); 606 607/* return the first n bits in val reversed */ 608extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 609 610/* printf interfaces */ 611extern void ath_hal_printf(struct ath_hal *, const char*, ...) 612 __printflike(2,3); 613extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 614 __printflike(2, 0); 615extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 616 617/* allocate and free memory */ 618extern void *ath_hal_malloc(size_t); 619extern void ath_hal_free(void *); 620 621/* common debugging interfaces */ 622#ifdef AH_DEBUG 623#include "ah_debug.h" 624extern int ath_hal_debug; /* Global debug flags */ 625 626/* 627 * The typecast is purely because some callers will pass in 628 * AH_NULL directly rather than using a NULL ath_hal pointer. 629 */ 630#define HALDEBUG(_ah, __m, ...) \ 631 do { \ 632 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 633 ath_hal_debug & (__m) || \ 634 ((_ah) != NULL && \ 635 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 636 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 637 } \ 638 } while(0); 639 640extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 641 __printflike(3,4); 642#else 643#define HALDEBUG(_ah, __m, ...) 644#endif /* AH_DEBUG */ 645 646/* 647 * Register logging definitions shared with ardecode. 648 */ 649#include "ah_decode.h" 650 651/* 652 * Common assertion interface. Note: it is a bad idea to generate 653 * an assertion failure for any recoverable event. Instead catch 654 * the violation and, if possible, fix it up or recover from it; either 655 * with an error return value or a diagnostic messages. System software 656 * does not panic unless the situation is hopeless. 657 */ 658#ifdef AH_ASSERT 659extern void ath_hal_assert_failed(const char* filename, 660 int lineno, const char* msg); 661 662#define HALASSERT(_x) do { \ 663 if (!(_x)) { \ 664 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 665 } \ 666} while (0) 667#else 668#define HALASSERT(_x) 669#endif /* AH_ASSERT */ 670 671/* 672 * Regulatory domain support. 673 */ 674 675/* 676 * Return the max allowed antenna gain and apply any regulatory 677 * domain specific changes. 678 */ 679u_int ath_hal_getantennareduction(struct ath_hal *ah, 680 const struct ieee80211_channel *chan, u_int twiceGain); 681 682/* 683 * Return the test group for the specific channel based on 684 * the current regulatory setup. 685 */ 686u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 687 688/* 689 * Map a public channel definition to the corresponding 690 * internal data structure. This implicitly specifies 691 * whether or not the specified channel is ok to use 692 * based on the current regulatory domain constraints. 693 */ 694#ifndef AH_DEBUG 695static OS_INLINE HAL_CHANNEL_INTERNAL * 696ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 697{ 698 HAL_CHANNEL_INTERNAL *cc; 699 700 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 701 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 702 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 703 return cc; 704} 705#else 706/* NB: non-inline version that checks state */ 707HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 708 const struct ieee80211_channel *); 709#endif /* AH_DEBUG */ 710 711/* 712 * Return the h/w frequency for a channel. This may be 713 * different from ic_freq if this is a GSM device that 714 * takes 2.4GHz frequencies and down-converts them. 715 */ 716static OS_INLINE uint16_t 717ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 718{ 719 return ath_hal_checkchannel(ah, c)->channel; 720} 721 722/* 723 * Convert between microseconds and core system clocks. 724 */ 725extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 726extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 727 728/* 729 * Generic get/set capability support. Each chip overrides 730 * this routine to support chip-specific capabilities. 731 */ 732extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 733 HAL_CAPABILITY_TYPE type, uint32_t capability, 734 uint32_t *result); 735extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 736 HAL_CAPABILITY_TYPE type, uint32_t capability, 737 uint32_t setting, HAL_STATUS *status); 738 739/* The diagnostic codes used to be internally defined here -adrian */ 740#include "ah_diagcodes.h" 741 742/* 743 * The AR5416 and later HALs have MAC and baseband hang checking. 744 */ 745typedef struct { 746 uint32_t hang_reg_offset; 747 uint32_t hang_val; 748 uint32_t hang_mask; 749 uint32_t hang_offset; 750} hal_hw_hang_check_t; 751 752typedef struct { 753 uint32_t dma_dbg_3; 754 uint32_t dma_dbg_4; 755 uint32_t dma_dbg_5; 756 uint32_t dma_dbg_6; 757} mac_dbg_regs_t; 758 759typedef enum { 760 dcu_chain_state = 0x1, 761 dcu_complete_state = 0x2, 762 qcu_state = 0x4, 763 qcu_fsp_ok = 0x8, 764 qcu_fsp_state = 0x10, 765 qcu_stitch_state = 0x20, 766 qcu_fetch_state = 0x40, 767 qcu_complete_state = 0x80 768} hal_mac_hangs_t; 769 770typedef struct { 771 int states; 772 uint8_t dcu_chain_state; 773 uint8_t dcu_complete_state; 774 uint8_t qcu_state; 775 uint8_t qcu_fsp_ok; 776 uint8_t qcu_fsp_state; 777 uint8_t qcu_stitch_state; 778 uint8_t qcu_fetch_state; 779 uint8_t qcu_complete_state; 780} hal_mac_hang_check_t; 781 782enum { 783 HAL_BB_HANG_DFS = 0x0001, 784 HAL_BB_HANG_RIFS = 0x0002, 785 HAL_BB_HANG_RX_CLEAR = 0x0004, 786 HAL_BB_HANG_UNKNOWN = 0x0080, 787 788 HAL_MAC_HANG_SIG1 = 0x0100, 789 HAL_MAC_HANG_SIG2 = 0x0200, 790 HAL_MAC_HANG_UNKNOWN = 0x8000, 791 792 HAL_BB_HANGS = HAL_BB_HANG_DFS 793 | HAL_BB_HANG_RIFS 794 | HAL_BB_HANG_RX_CLEAR 795 | HAL_BB_HANG_UNKNOWN, 796 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 797 | HAL_MAC_HANG_SIG2 798 | HAL_MAC_HANG_UNKNOWN, 799}; 800 801/* Merge these with above */ 802typedef enum hal_hw_hangs { 803 HAL_DFS_BB_HANG_WAR = 0x1, 804 HAL_RIFS_BB_HANG_WAR = 0x2, 805 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 806 HAL_MAC_HANG_WAR = 0x8, 807 HAL_PHYRESTART_CLR_WAR = 0x10, 808 HAL_MAC_HANG_DETECTED = 0x40000000, 809 HAL_BB_HANG_DETECTED = 0x80000000 810} hal_hw_hangs_t; 811 812/* 813 * Device revision information. 814 */ 815typedef struct { 816 uint16_t ah_devid; /* PCI device ID */ 817 uint16_t ah_subvendorid; /* PCI subvendor ID */ 818 uint32_t ah_macVersion; /* MAC version id */ 819 uint16_t ah_macRev; /* MAC revision */ 820 uint16_t ah_phyRev; /* PHY revision */ 821 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 822 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 823} HAL_REVS; 824 825/* 826 * Argument payload for HAL_DIAG_SETKEY. 827 */ 828typedef struct { 829 HAL_KEYVAL dk_keyval; 830 uint16_t dk_keyix; /* key index */ 831 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 832 int dk_xor; /* XOR key data */ 833} HAL_DIAG_KEYVAL; 834 835/* 836 * Argument payload for HAL_DIAG_EEWRITE. 837 */ 838typedef struct { 839 uint16_t ee_off; /* eeprom offset */ 840 uint16_t ee_data; /* write data */ 841} HAL_DIAG_EEVAL; 842 843 844typedef struct { 845 u_int offset; /* reg offset */ 846 uint32_t val; /* reg value */ 847} HAL_DIAG_REGVAL; 848 849/* 850 * 11n compatibility tweaks. 851 */ 852#define HAL_DIAG_11N_SERVICES 0x00000003 853#define HAL_DIAG_11N_SERVICES_S 0 854#define HAL_DIAG_11N_TXSTOMP 0x0000000c 855#define HAL_DIAG_11N_TXSTOMP_S 2 856 857typedef struct { 858 int maxNoiseImmunityLevel; /* [0..4] */ 859 int totalSizeDesired[5]; 860 int coarseHigh[5]; 861 int coarseLow[5]; 862 int firpwr[5]; 863 864 int maxSpurImmunityLevel; /* [0..7] */ 865 int cycPwrThr1[8]; 866 867 int maxFirstepLevel; /* [0..2] */ 868 int firstep[3]; 869 870 uint32_t ofdmTrigHigh; 871 uint32_t ofdmTrigLow; 872 int32_t cckTrigHigh; 873 int32_t cckTrigLow; 874 int32_t rssiThrLow; 875 int32_t rssiThrHigh; 876 877 int period; /* update listen period */ 878} HAL_ANI_PARAMS; 879 880extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 881 const void *args, uint32_t argsize, 882 void **result, uint32_t *resultsize); 883 884/* 885 * Setup a h/w rate table for use. 886 */ 887extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 888 889/* 890 * Common routine for implementing getChanNoise api. 891 */ 892int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 893 894/* 895 * Initialization support. 896 */ 897typedef struct { 898 const uint32_t *data; 899 int rows, cols; 900} HAL_INI_ARRAY; 901 902#define HAL_INI_INIT(_ia, _data, _cols) do { \ 903 (_ia)->data = (const uint32_t *)(_data); \ 904 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 905 (_ia)->cols = (_cols); \ 906} while (0) 907#define HAL_INI_VAL(_ia, _r, _c) \ 908 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 909 910/* 911 * OS_DELAY() does a PIO READ on the PCI bus which allows 912 * other cards' DMA reads to complete in the middle of our reset. 913 */ 914#define DMA_YIELD(x) do { \ 915 if ((++(x) % 64) == 0) \ 916 OS_DELAY(1); \ 917} while (0) 918 919#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 920 int r; \ 921 for (r = 0; r < N(regArray); r++) { \ 922 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 923 DMA_YIELD(regWr); \ 924 } \ 925} while (0) 926 927#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 928 int r; \ 929 for (r = 0; r < N(regArray); r++) { \ 930 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 931 DMA_YIELD(regWr); \ 932 } \ 933} while (0) 934 935extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 936 int col, int regWr); 937extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 938 int col); 939extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 940 const uint32_t data[], int regWr); 941 942#define CCK_SIFS_TIME 10 943#define CCK_PREAMBLE_BITS 144 944#define CCK_PLCP_BITS 48 945 946#define OFDM_SIFS_TIME 16 947#define OFDM_PREAMBLE_TIME 20 948#define OFDM_PLCP_BITS 22 949#define OFDM_SYMBOL_TIME 4 950 951#define OFDM_HALF_SIFS_TIME 32 952#define OFDM_HALF_PREAMBLE_TIME 40 953#define OFDM_HALF_PLCP_BITS 22 954#define OFDM_HALF_SYMBOL_TIME 8 955 956#define OFDM_QUARTER_SIFS_TIME 64 957#define OFDM_QUARTER_PREAMBLE_TIME 80 958#define OFDM_QUARTER_PLCP_BITS 22 959#define OFDM_QUARTER_SYMBOL_TIME 16 960 961#define TURBO_SIFS_TIME 8 962#define TURBO_PREAMBLE_TIME 14 963#define TURBO_PLCP_BITS 22 964#define TURBO_SYMBOL_TIME 4 965 966#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 967 968/* Generic EEPROM board value functions */ 969extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 970 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 971extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 972 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 973 uint8_t *pRetVpdList); 974extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 975 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 976 977/* Whether 5ghz fast clock is needed */ 978/* 979 * The chipset (Merlin, AR9300/later) should set the capability flag below; 980 * this flag simply says that the hardware can do it, not that the EEPROM 981 * says it can. 982 * 983 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 984 * if the relevant eeprom flag is set. 985 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 986 * by default. 987 */ 988#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 989 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 990 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 991 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 992 993/* 994 * Fetch the maximum regulatory domain power for the given channel 995 * in 1/2dBm steps. 996 */ 997static inline int 998ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 999 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 1000{ 1001 struct ath_hal *ah = &ahp->h; 1002 1003 if (! chan) { 1004 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1005 return (0); 1006 } 1007 return (chan->ic_maxpower); 1008} 1009 1010/* 1011 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1012 */ 1013static inline int 1014ath_hal_getantennaallowed(struct ath_hal *ah, 1015 const struct ieee80211_channel *chan) 1016{ 1017 1018 if (! chan) 1019 return (0); 1020 1021 return (chan->ic_maxantgain); 1022} 1023 1024/* 1025 * Map the given 2GHz channel to an IEEE number. 1026 */ 1027extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 1028 1029#endif /* _ATH_AH_INTERAL_H_ */ 1030