ah_internal.h revision 249137
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 249137 2013-04-05 09:06:39Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_STATUS *error); 95}; 96#ifndef AH_CHIP 97#define AH_CHIP(_name, _probe, _attach) \ 98static struct ath_hal_chip _name##_chip = { \ 99 .name = #_name, \ 100 .probe = _probe, \ 101 .attach = _attach \ 102}; \ 103OS_DATA_SET(ah_chips, _name##_chip) 104#endif 105 106/* 107 * Each RF backend registers to offer support; this is mostly 108 * used by multi-chip 5212 solutions. Single-chip solutions 109 * have a fixed idea about which RF to use. 110 */ 111struct ath_hal_rf { 112 const char *name; 113 HAL_BOOL (*probe)(struct ath_hal *ah); 114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 115}; 116#ifndef AH_RF 117#define AH_RF(_name, _probe, _attach) \ 118static struct ath_hal_rf _name##_rf = { \ 119 .name = __STRING(_name), \ 120 .probe = _probe, \ 121 .attach = _attach \ 122}; \ 123OS_DATA_SET(ah_rfs, _name##_rf) 124#endif 125 126struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 127 128/* 129 * Maximum number of internal channels. Entries are per unique 130 * frequency so this might be need to be increased to handle all 131 * usage cases; typically no more than 32 are really needed but 132 * dynamically allocating the data structures is a bit painful 133 * right now. 134 */ 135#ifndef AH_MAXCHAN 136#define AH_MAXCHAN 96 137#endif 138 139#define HAL_NF_CAL_HIST_LEN_FULL 5 140#define HAL_NF_CAL_HIST_LEN_SMALL 1 141#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 142#define HAL_NF_LOAD_DELAY 1000 143 144/* 145 * PER_CHAN doesn't work for now, as it looks like the device layer 146 * has to pre-populate the per-channel list with nominal values. 147 */ 148//#define ATH_NF_PER_CHAN 1 149 150typedef struct { 151 u_int8_t curr_index; 152 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 153 int16_t priv_nf[HAL_NUM_NF_READINGS]; 154} HAL_NFCAL_BASE; 155 156typedef struct { 157 HAL_NFCAL_BASE base; 158 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 159} HAL_NFCAL_HIST_FULL; 160 161typedef struct { 162 HAL_NFCAL_BASE base; 163 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 164} HAL_NFCAL_HIST_SMALL; 165 166#ifdef ATH_NF_PER_CHAN 167typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 168#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 169#else 170typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 171#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 172#endif /* ATH_NF_PER_CHAN */ 173 174/* 175 * Internal per-channel state. These are found 176 * using ic_devdata in the ieee80211_channel. 177 */ 178typedef struct { 179 uint16_t channel; /* h/w frequency, NB: may be mapped */ 180 uint8_t privFlags; 181#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 182#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 183#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 184#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 185 uint8_t calValid; /* bitmask of cal types */ 186 int8_t iCoff; 187 int8_t qCoff; 188 int16_t rawNoiseFloor; 189 int16_t noiseFloorAdjust; 190#ifdef AH_SUPPORT_AR5416 191 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 192 int16_t noiseFloorExt[AH_MAX_CHAINS]; 193#endif /* AH_SUPPORT_AR5416 */ 194 uint16_t mainSpur; /* cached spur value for this channel */ 195 196 /*XXX TODO: make these part of privFlags */ 197 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 198 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 199 int one_time_cals_done; 200 HAL_CHAN_NFCAL_HIST nf_cal_hist; 201} HAL_CHANNEL_INTERNAL; 202 203/* channel requires noise floor check */ 204#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 205 206/* all full-width channels */ 207#define IEEE80211_CHAN_ALLFULL \ 208 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 209#define IEEE80211_CHAN_ALLTURBOFULL \ 210 (IEEE80211_CHAN_ALLTURBO - \ 211 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 212 213typedef struct { 214 uint32_t halChanSpreadSupport : 1, 215 halSleepAfterBeaconBroken : 1, 216 halCompressSupport : 1, 217 halBurstSupport : 1, 218 halFastFramesSupport : 1, 219 halChapTuningSupport : 1, 220 halTurboGSupport : 1, 221 halTurboPrimeSupport : 1, 222 halMicAesCcmSupport : 1, 223 halMicCkipSupport : 1, 224 halMicTkipSupport : 1, 225 halTkipMicTxRxKeySupport : 1, 226 halCipherAesCcmSupport : 1, 227 halCipherCkipSupport : 1, 228 halCipherTkipSupport : 1, 229 halPSPollBroken : 1, 230 halVEOLSupport : 1, 231 halBssIdMaskSupport : 1, 232 halMcastKeySrchSupport : 1, 233 halTsfAddSupport : 1, 234 halChanHalfRate : 1, 235 halChanQuarterRate : 1, 236 halHTSupport : 1, 237 halHTSGI20Support : 1, 238 halRfSilentSupport : 1, 239 halHwPhyCounterSupport : 1, 240 halWowSupport : 1, 241 halWowMatchPatternExact : 1, 242 halAutoSleepSupport : 1, 243 halFastCCSupport : 1, 244 halBtCoexSupport : 1; 245 uint32_t halRxStbcSupport : 1, 246 halTxStbcSupport : 1, 247 halGTTSupport : 1, 248 halCSTSupport : 1, 249 halRifsRxSupport : 1, 250 halRifsTxSupport : 1, 251 hal4AddrAggrSupport : 1, 252 halExtChanDfsSupport : 1, 253 halUseCombinedRadarRssi : 1, 254 halForcePpmSupport : 1, 255 halEnhancedPmSupport : 1, 256 halEnhancedDfsSupport : 1, 257 halMbssidAggrSupport : 1, 258 halBssidMatchSupport : 1, 259 hal4kbSplitTransSupport : 1, 260 halHasRxSelfLinkedTail : 1, 261 halSupportsFastClock5GHz : 1, 262 halHasLongRxDescTsf : 1, 263 halHasBBReadWar : 1, 264 halSerialiseRegWar : 1, 265 halMciSupport : 1, 266 halRxTxAbortSupport : 1, 267 halPaprdEnabled : 1, 268 halHasUapsdSupport : 1, 269 halWpsPushButtonSupport : 1, 270 halBtCoexApsmWar : 1, 271 halGenTimerSupport : 1, 272 halLDPCSupport : 1, 273 halHwBeaconProcSupport : 1, 274 halEnhancedDmaSupport : 1; 275 uint32_t halIsrRacSupport : 1, 276 halApmEnable : 1, 277 halIntrMitigation : 1, 278 hal49GhzSupport : 1, 279 halAntDivCombSupport : 1, 280 halAntDivCombSupportOrg : 1, 281 halRadioRetentionSupport : 1, 282 halSpectralScanSupport : 1; 283 284 uint32_t halWirelessModes; 285 uint16_t halTotalQueues; 286 uint16_t halKeyCacheSize; 287 uint16_t halLow5GhzChan, halHigh5GhzChan; 288 uint16_t halLow2GhzChan, halHigh2GhzChan; 289 int halTstampPrecision; 290 int halRtsAggrLimit; 291 uint8_t halTxChainMask; 292 uint8_t halRxChainMask; 293 uint8_t halNumGpioPins; 294 uint8_t halNumAntCfg2GHz; 295 uint8_t halNumAntCfg5GHz; 296 uint32_t halIntrMask; 297 uint8_t halTxStreams; 298 uint8_t halRxStreams; 299 HAL_MFP_OPT_T halMfpSupport; 300 301 /* AR9300 HAL porting capabilities */ 302 int hal_paprd_enabled; 303 int hal_pcie_lcr_offset; 304 int hal_pcie_lcr_extsync_en; 305 int halNumTxMaps; 306 int halTxDescLen; 307 int halTxStatusLen; 308 int halRxStatusLen; 309 int halRxHpFifoDepth; 310 int halRxLpFifoDepth; 311 uint32_t halRegCap; /* XXX needed? */ 312 int halNumMRRetries; 313 int hal_ani_poll_interval; 314 int hal_channel_switch_time_usec; 315} HAL_CAPABILITIES; 316 317struct regDomain; 318 319/* 320 * Definitions for ah_flags in ath_hal_private 321 */ 322#define AH_USE_EEPROM 0x1 323#define AH_IS_HB63 0x2 324 325/* 326 * The ``private area'' follows immediately after the ``public area'' 327 * in the data structure returned by ath_hal_attach. Private data are 328 * used by device-independent code such as the regulatory domain support. 329 * In general, code within the HAL should never depend on data in the 330 * public area. Instead any public data needed internally should be 331 * shadowed here. 332 * 333 * When declaring a device-specific ath_hal data structure this structure 334 * is assumed to at the front; e.g. 335 * 336 * struct ath_hal_5212 { 337 * struct ath_hal_private ah_priv; 338 * ... 339 * }; 340 * 341 * It might be better to manage the method pointers in this structure 342 * using an indirect pointer to a read-only data structure but this would 343 * disallow class-style method overriding. 344 */ 345struct ath_hal_private { 346 struct ath_hal h; /* public area */ 347 348 /* NB: all methods go first to simplify initialization */ 349 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 350 uint16_t channelFlags, 351 uint16_t *lowChannel, uint16_t *highChannel); 352 u_int (*ah_getWirelessModes)(struct ath_hal*); 353 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 354 uint16_t *data); 355 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 356 uint16_t data); 357 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 358 struct ieee80211_channel *); 359 int16_t (*ah_getNfAdjust)(struct ath_hal *, 360 const HAL_CHANNEL_INTERNAL*); 361 void (*ah_getNoiseFloor)(struct ath_hal *, 362 int16_t nfarray[]); 363 364 void *ah_eeprom; /* opaque EEPROM state */ 365 uint16_t ah_eeversion; /* EEPROM version */ 366 void (*ah_eepromDetach)(struct ath_hal *); 367 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 368 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 369 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 370 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 371 const void *args, uint32_t argsize, 372 void **result, uint32_t *resultsize); 373 374 /* 375 * Device revision information. 376 */ 377 uint16_t ah_devid; /* PCI device ID */ 378 uint16_t ah_subvendorid; /* PCI subvendor ID */ 379 uint32_t ah_macVersion; /* MAC version id */ 380 uint16_t ah_macRev; /* MAC revision */ 381 uint16_t ah_phyRev; /* PHY revision */ 382 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 383 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 384 uint32_t ah_flags; /* misc flags */ 385 uint8_t ah_ispcie; /* PCIE, special treatment */ 386 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 387 388 HAL_OPMODE ah_opmode; /* operating mode from reset */ 389 const struct ieee80211_channel *ah_curchan;/* operating channel */ 390 HAL_CAPABILITIES ah_caps; /* device capabilities */ 391 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 392 int16_t ah_powerLimit; /* tx power cap */ 393 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 394 u_int ah_tpScale; /* tx power scale factor */ 395 u_int16_t ah_extraTxPow; /* low rates extra-txpower */ 396 uint32_t ah_11nCompat; /* 11n compat controls */ 397 398 /* 399 * State for regulatory domain handling. 400 */ 401 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 402 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 403 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 404 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 405 u_int ah_nchan; /* valid items in ah_channels */ 406 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 407 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 408 409 uint8_t ah_coverageClass; /* coverage class */ 410 /* 411 * RF Silent handling; setup according to the EEPROM. 412 */ 413 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 414 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 415 /* 416 * Diagnostic support for discriminating HIUERR reports. 417 */ 418 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 419 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 420 421#ifndef ATH_NF_PER_CHAN 422 HAL_NFCAL_HIST_FULL nf_cal_hist; 423#endif /* ! ATH_NF_PER_CHAN */ 424}; 425 426#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 427 428#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 429 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 430#define ath_hal_getWirelessModes(_ah) \ 431 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 432#define ath_hal_eepromRead(_ah, _off, _data) \ 433 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 434#define ath_hal_eepromWrite(_ah, _off, _data) \ 435 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 436#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 437 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 438#define ath_hal_gpioCfgInput(_ah, _gpio) \ 439 (_ah)->ah_gpioCfgInput(_ah, _gpio) 440#define ath_hal_gpioGet(_ah, _gpio) \ 441 (_ah)->ah_gpioGet(_ah, _gpio) 442#define ath_hal_gpioSet(_ah, _gpio, _val) \ 443 (_ah)->ah_gpioSet(_ah, _gpio, _val) 444#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 445 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 446#define ath_hal_getpowerlimits(_ah, _chan) \ 447 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 448#define ath_hal_getNfAdjust(_ah, _c) \ 449 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 450#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 451 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 452#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 453 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 454#define ath_hal_disablePCIE(_ah) \ 455 (_ah)->ah_disablePCIE(_ah) 456#define ath_hal_setInterrupts(_ah, _mask) \ 457 (_ah)->ah_setInterrupts(_ah, _mask) 458 459#define ath_hal_isrfkillenabled(_ah) \ 460 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 461#define ath_hal_enable_rfkill(_ah, _v) \ 462 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 463#define ath_hal_hasrfkill_int(_ah) \ 464 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 465 466#define ath_hal_eepromDetach(_ah) do { \ 467 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 468 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 469} while (0) 470#define ath_hal_eepromGet(_ah, _param, _val) \ 471 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 472#define ath_hal_eepromSet(_ah, _param, _val) \ 473 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 474#define ath_hal_eepromGetFlag(_ah, _param) \ 475 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 476#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 477 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 478#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 479 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 480 481#ifndef _NET_IF_IEEE80211_H_ 482/* 483 * Stuff that would naturally come from _ieee80211.h 484 */ 485#define IEEE80211_ADDR_LEN 6 486 487#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 488#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 489#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 490 491#define IEEE80211_CRC_LEN 4 492 493#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 494 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 495#endif /* _NET_IF_IEEE80211_H_ */ 496 497#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 498 499#define INIT_AIFS 2 500#define INIT_CWMIN 15 501#define INIT_CWMIN_11B 31 502#define INIT_CWMAX 1023 503#define INIT_SH_RETRY 10 504#define INIT_LG_RETRY 10 505#define INIT_SSH_RETRY 32 506#define INIT_SLG_RETRY 32 507 508typedef struct { 509 uint32_t tqi_ver; /* HAL TXQ verson */ 510 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 511 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 512 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 513 uint32_t tqi_priority; 514 uint32_t tqi_aifs; /* aifs */ 515 uint32_t tqi_cwmin; /* cwMin */ 516 uint32_t tqi_cwmax; /* cwMax */ 517 uint16_t tqi_shretry; /* frame short retry limit */ 518 uint16_t tqi_lgretry; /* frame long retry limit */ 519 uint32_t tqi_cbrPeriod; 520 uint32_t tqi_cbrOverflowLimit; 521 uint32_t tqi_burstTime; 522 uint32_t tqi_readyTime; 523 uint32_t tqi_physCompBuf; 524 uint32_t tqi_intFlags; /* flags for internal use */ 525} HAL_TX_QUEUE_INFO; 526 527extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 528 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 529extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 530 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 531 532#define HAL_SPUR_VAL_MASK 0x3FFF 533#define HAL_SPUR_CHAN_WIDTH 87 534#define HAL_BIN_WIDTH_BASE_100HZ 3125 535#define HAL_BIN_WIDTH_TURBO_100HZ 6250 536#define HAL_MAX_BINS_ALLOWED 28 537 538#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 539#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 540 541#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 542 543/* 544 * Deduce if the host cpu has big- or litt-endian byte order. 545 */ 546static __inline__ int 547isBigEndian(void) 548{ 549 union { 550 int32_t i; 551 char c[4]; 552 } u; 553 u.i = 1; 554 return (u.c[0] == 0); 555} 556 557/* unalligned little endian access */ 558#define LE_READ_2(p) \ 559 ((uint16_t) \ 560 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 561#define LE_READ_4(p) \ 562 ((uint32_t) \ 563 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 564 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 565 566/* 567 * Register manipulation macros that expect bit field defines 568 * to follow the convention that an _S suffix is appended for 569 * a shift count, while the field mask has no suffix. 570 */ 571#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 572#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 573#define OS_REG_RMW(_a, _r, _set, _clr) \ 574 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 575#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 576 OS_REG_WRITE(_a, _r, \ 577 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 578#define OS_REG_SET_BIT(_a, _r, _f) \ 579 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 580#define OS_REG_CLR_BIT(_a, _r, _f) \ 581 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 582#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 583 ((OS_REG_READ(_a, _r) & (_f)) != 0) 584#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 585 OS_REG_WRITE(_a, _r, \ 586 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 587 (((_v) << _f##_S) & (_f<<_f##_S))) 588#define OS_REG_READ_FIELD(_a, _r, _f) \ 589 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 590#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 591 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 592 593/* Analog register writes may require a delay between each one (eg Merlin?) */ 594#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 595 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 596 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 597#define OS_A_REG_WRITE(_a, _r, _v) \ 598 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 599 600/* wait for the register contents to have the specified value */ 601extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 602 uint32_t mask, uint32_t val); 603extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 604 uint32_t mask, uint32_t val, uint32_t timeout); 605 606/* return the first n bits in val reversed */ 607extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 608 609/* printf interfaces */ 610extern void ath_hal_printf(struct ath_hal *, const char*, ...) 611 __printflike(2,3); 612extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 613 __printflike(2, 0); 614extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 615 616/* allocate and free memory */ 617extern void *ath_hal_malloc(size_t); 618extern void ath_hal_free(void *); 619 620/* common debugging interfaces */ 621#ifdef AH_DEBUG 622#include "ah_debug.h" 623extern int ath_hal_debug; /* Global debug flags */ 624 625/* 626 * The typecast is purely because some callers will pass in 627 * AH_NULL directly rather than using a NULL ath_hal pointer. 628 */ 629#define HALDEBUG(_ah, __m, ...) \ 630 do { \ 631 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 632 ath_hal_debug & (__m) || \ 633 ((_ah) != NULL && \ 634 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 635 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 636 } \ 637 } while(0); 638 639extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 640 __printflike(3,4); 641#else 642#define HALDEBUG(_ah, __m, ...) 643#endif /* AH_DEBUG */ 644 645/* 646 * Register logging definitions shared with ardecode. 647 */ 648#include "ah_decode.h" 649 650/* 651 * Common assertion interface. Note: it is a bad idea to generate 652 * an assertion failure for any recoverable event. Instead catch 653 * the violation and, if possible, fix it up or recover from it; either 654 * with an error return value or a diagnostic messages. System software 655 * does not panic unless the situation is hopeless. 656 */ 657#ifdef AH_ASSERT 658extern void ath_hal_assert_failed(const char* filename, 659 int lineno, const char* msg); 660 661#define HALASSERT(_x) do { \ 662 if (!(_x)) { \ 663 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 664 } \ 665} while (0) 666#else 667#define HALASSERT(_x) 668#endif /* AH_ASSERT */ 669 670/* 671 * Regulatory domain support. 672 */ 673 674/* 675 * Return the max allowed antenna gain and apply any regulatory 676 * domain specific changes. 677 */ 678u_int ath_hal_getantennareduction(struct ath_hal *ah, 679 const struct ieee80211_channel *chan, u_int twiceGain); 680 681/* 682 * Return the test group for the specific channel based on 683 * the current regulatory setup. 684 */ 685u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 686 687/* 688 * Map a public channel definition to the corresponding 689 * internal data structure. This implicitly specifies 690 * whether or not the specified channel is ok to use 691 * based on the current regulatory domain constraints. 692 */ 693#ifndef AH_DEBUG 694static OS_INLINE HAL_CHANNEL_INTERNAL * 695ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 696{ 697 HAL_CHANNEL_INTERNAL *cc; 698 699 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 700 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 701 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 702 return cc; 703} 704#else 705/* NB: non-inline version that checks state */ 706HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 707 const struct ieee80211_channel *); 708#endif /* AH_DEBUG */ 709 710/* 711 * Return the h/w frequency for a channel. This may be 712 * different from ic_freq if this is a GSM device that 713 * takes 2.4GHz frequencies and down-converts them. 714 */ 715static OS_INLINE uint16_t 716ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 717{ 718 return ath_hal_checkchannel(ah, c)->channel; 719} 720 721/* 722 * Convert between microseconds and core system clocks. 723 */ 724extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 725extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 726 727/* 728 * Generic get/set capability support. Each chip overrides 729 * this routine to support chip-specific capabilities. 730 */ 731extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 732 HAL_CAPABILITY_TYPE type, uint32_t capability, 733 uint32_t *result); 734extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 735 HAL_CAPABILITY_TYPE type, uint32_t capability, 736 uint32_t setting, HAL_STATUS *status); 737 738/* The diagnostic codes used to be internally defined here -adrian */ 739#include "ah_diagcodes.h" 740 741/* 742 * The AR5416 and later HALs have MAC and baseband hang checking. 743 */ 744typedef struct { 745 uint32_t hang_reg_offset; 746 uint32_t hang_val; 747 uint32_t hang_mask; 748 uint32_t hang_offset; 749} hal_hw_hang_check_t; 750 751typedef struct { 752 uint32_t dma_dbg_3; 753 uint32_t dma_dbg_4; 754 uint32_t dma_dbg_5; 755 uint32_t dma_dbg_6; 756} mac_dbg_regs_t; 757 758typedef enum { 759 dcu_chain_state = 0x1, 760 dcu_complete_state = 0x2, 761 qcu_state = 0x4, 762 qcu_fsp_ok = 0x8, 763 qcu_fsp_state = 0x10, 764 qcu_stitch_state = 0x20, 765 qcu_fetch_state = 0x40, 766 qcu_complete_state = 0x80 767} hal_mac_hangs_t; 768 769typedef struct { 770 int states; 771 uint8_t dcu_chain_state; 772 uint8_t dcu_complete_state; 773 uint8_t qcu_state; 774 uint8_t qcu_fsp_ok; 775 uint8_t qcu_fsp_state; 776 uint8_t qcu_stitch_state; 777 uint8_t qcu_fetch_state; 778 uint8_t qcu_complete_state; 779} hal_mac_hang_check_t; 780 781enum { 782 HAL_BB_HANG_DFS = 0x0001, 783 HAL_BB_HANG_RIFS = 0x0002, 784 HAL_BB_HANG_RX_CLEAR = 0x0004, 785 HAL_BB_HANG_UNKNOWN = 0x0080, 786 787 HAL_MAC_HANG_SIG1 = 0x0100, 788 HAL_MAC_HANG_SIG2 = 0x0200, 789 HAL_MAC_HANG_UNKNOWN = 0x8000, 790 791 HAL_BB_HANGS = HAL_BB_HANG_DFS 792 | HAL_BB_HANG_RIFS 793 | HAL_BB_HANG_RX_CLEAR 794 | HAL_BB_HANG_UNKNOWN, 795 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 796 | HAL_MAC_HANG_SIG2 797 | HAL_MAC_HANG_UNKNOWN, 798}; 799 800/* Merge these with above */ 801typedef enum hal_hw_hangs { 802 HAL_DFS_BB_HANG_WAR = 0x1, 803 HAL_RIFS_BB_HANG_WAR = 0x2, 804 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 805 HAL_MAC_HANG_WAR = 0x8, 806 HAL_PHYRESTART_CLR_WAR = 0x10, 807 HAL_MAC_HANG_DETECTED = 0x40000000, 808 HAL_BB_HANG_DETECTED = 0x80000000 809} hal_hw_hangs_t; 810 811/* 812 * Device revision information. 813 */ 814typedef struct { 815 uint16_t ah_devid; /* PCI device ID */ 816 uint16_t ah_subvendorid; /* PCI subvendor ID */ 817 uint32_t ah_macVersion; /* MAC version id */ 818 uint16_t ah_macRev; /* MAC revision */ 819 uint16_t ah_phyRev; /* PHY revision */ 820 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 821 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 822} HAL_REVS; 823 824/* 825 * Argument payload for HAL_DIAG_SETKEY. 826 */ 827typedef struct { 828 HAL_KEYVAL dk_keyval; 829 uint16_t dk_keyix; /* key index */ 830 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 831 int dk_xor; /* XOR key data */ 832} HAL_DIAG_KEYVAL; 833 834/* 835 * Argument payload for HAL_DIAG_EEWRITE. 836 */ 837typedef struct { 838 uint16_t ee_off; /* eeprom offset */ 839 uint16_t ee_data; /* write data */ 840} HAL_DIAG_EEVAL; 841 842 843typedef struct { 844 u_int offset; /* reg offset */ 845 uint32_t val; /* reg value */ 846} HAL_DIAG_REGVAL; 847 848/* 849 * 11n compatibility tweaks. 850 */ 851#define HAL_DIAG_11N_SERVICES 0x00000003 852#define HAL_DIAG_11N_SERVICES_S 0 853#define HAL_DIAG_11N_TXSTOMP 0x0000000c 854#define HAL_DIAG_11N_TXSTOMP_S 2 855 856typedef struct { 857 int maxNoiseImmunityLevel; /* [0..4] */ 858 int totalSizeDesired[5]; 859 int coarseHigh[5]; 860 int coarseLow[5]; 861 int firpwr[5]; 862 863 int maxSpurImmunityLevel; /* [0..7] */ 864 int cycPwrThr1[8]; 865 866 int maxFirstepLevel; /* [0..2] */ 867 int firstep[3]; 868 869 uint32_t ofdmTrigHigh; 870 uint32_t ofdmTrigLow; 871 int32_t cckTrigHigh; 872 int32_t cckTrigLow; 873 int32_t rssiThrLow; 874 int32_t rssiThrHigh; 875 876 int period; /* update listen period */ 877} HAL_ANI_PARAMS; 878 879extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 880 const void *args, uint32_t argsize, 881 void **result, uint32_t *resultsize); 882 883/* 884 * Setup a h/w rate table for use. 885 */ 886extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 887 888/* 889 * Common routine for implementing getChanNoise api. 890 */ 891int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 892 893/* 894 * Initialization support. 895 */ 896typedef struct { 897 const uint32_t *data; 898 int rows, cols; 899} HAL_INI_ARRAY; 900 901#define HAL_INI_INIT(_ia, _data, _cols) do { \ 902 (_ia)->data = (const uint32_t *)(_data); \ 903 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 904 (_ia)->cols = (_cols); \ 905} while (0) 906#define HAL_INI_VAL(_ia, _r, _c) \ 907 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 908 909/* 910 * OS_DELAY() does a PIO READ on the PCI bus which allows 911 * other cards' DMA reads to complete in the middle of our reset. 912 */ 913#define DMA_YIELD(x) do { \ 914 if ((++(x) % 64) == 0) \ 915 OS_DELAY(1); \ 916} while (0) 917 918#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 919 int r; \ 920 for (r = 0; r < N(regArray); r++) { \ 921 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 922 DMA_YIELD(regWr); \ 923 } \ 924} while (0) 925 926#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 927 int r; \ 928 for (r = 0; r < N(regArray); r++) { \ 929 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 930 DMA_YIELD(regWr); \ 931 } \ 932} while (0) 933 934extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 935 int col, int regWr); 936extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 937 int col); 938extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 939 const uint32_t data[], int regWr); 940 941#define CCK_SIFS_TIME 10 942#define CCK_PREAMBLE_BITS 144 943#define CCK_PLCP_BITS 48 944 945#define OFDM_SIFS_TIME 16 946#define OFDM_PREAMBLE_TIME 20 947#define OFDM_PLCP_BITS 22 948#define OFDM_SYMBOL_TIME 4 949 950#define OFDM_HALF_SIFS_TIME 32 951#define OFDM_HALF_PREAMBLE_TIME 40 952#define OFDM_HALF_PLCP_BITS 22 953#define OFDM_HALF_SYMBOL_TIME 8 954 955#define OFDM_QUARTER_SIFS_TIME 64 956#define OFDM_QUARTER_PREAMBLE_TIME 80 957#define OFDM_QUARTER_PLCP_BITS 22 958#define OFDM_QUARTER_SYMBOL_TIME 16 959 960#define TURBO_SIFS_TIME 8 961#define TURBO_PREAMBLE_TIME 14 962#define TURBO_PLCP_BITS 22 963#define TURBO_SYMBOL_TIME 4 964 965#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 966 967/* Generic EEPROM board value functions */ 968extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 969 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 970extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 971 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 972 uint8_t *pRetVpdList); 973extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 974 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 975 976/* Whether 5ghz fast clock is needed */ 977/* 978 * The chipset (Merlin, AR9300/later) should set the capability flag below; 979 * this flag simply says that the hardware can do it, not that the EEPROM 980 * says it can. 981 * 982 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 983 * if the relevant eeprom flag is set. 984 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 985 * by default. 986 */ 987#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 988 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 989 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 990 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 991 992/* 993 * Fetch the maximum regulatory domain power for the given channel 994 * in 1/2dBm steps. 995 */ 996static inline int 997ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 998 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 999{ 1000 struct ath_hal *ah = &ahp->h; 1001 1002 if (! chan) { 1003 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1004 return (0); 1005 } 1006 return (chan->ic_maxpower); 1007} 1008 1009/* 1010 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1011 */ 1012static inline int 1013ath_hal_getantennaallowed(struct ath_hal *ah, 1014 const struct ieee80211_channel *chan) 1015{ 1016 1017 if (! chan) 1018 return (0); 1019 1020 return (chan->ic_maxantgain); 1021} 1022 1023 1024#endif /* _ATH_AH_INTERAL_H_ */ 1025