ah_internal.h revision 242407
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 242407 2012-10-31 21:00:01Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_STATUS *error); 95}; 96#ifndef AH_CHIP 97#define AH_CHIP(_name, _probe, _attach) \ 98static struct ath_hal_chip _name##_chip = { \ 99 .name = #_name, \ 100 .probe = _probe, \ 101 .attach = _attach \ 102}; \ 103OS_DATA_SET(ah_chips, _name##_chip) 104#endif 105 106/* 107 * Each RF backend registers to offer support; this is mostly 108 * used by multi-chip 5212 solutions. Single-chip solutions 109 * have a fixed idea about which RF to use. 110 */ 111struct ath_hal_rf { 112 const char *name; 113 HAL_BOOL (*probe)(struct ath_hal *ah); 114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 115}; 116#ifndef AH_RF 117#define AH_RF(_name, _probe, _attach) \ 118static struct ath_hal_rf _name##_rf = { \ 119 .name = __STRING(_name), \ 120 .probe = _probe, \ 121 .attach = _attach \ 122}; \ 123OS_DATA_SET(ah_rfs, _name##_rf) 124#endif 125 126struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 127 128/* 129 * Maximum number of internal channels. Entries are per unique 130 * frequency so this might be need to be increased to handle all 131 * usage cases; typically no more than 32 are really needed but 132 * dynamically allocating the data structures is a bit painful 133 * right now. 134 */ 135#ifndef AH_MAXCHAN 136#define AH_MAXCHAN 96 137#endif 138 139#define HAL_NF_CAL_HIST_LEN_FULL 5 140#define HAL_NF_CAL_HIST_LEN_SMALL 1 141#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */ 142#define HAL_NF_LOAD_DELAY 1000 143 144/* 145 * PER_CHAN doesn't work for now, as it looks like the device layer 146 * has to pre-populate the per-channel list with nominal values. 147 */ 148//#define ATH_NF_PER_CHAN 1 149 150typedef struct { 151 u_int8_t curr_index; 152 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */ 153 int16_t priv_nf[HAL_NUM_NF_READINGS]; 154} HAL_NFCAL_BASE; 155 156typedef struct { 157 HAL_NFCAL_BASE base; 158 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS]; 159} HAL_NFCAL_HIST_FULL; 160 161typedef struct { 162 HAL_NFCAL_BASE base; 163 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS]; 164} HAL_NFCAL_HIST_SMALL; 165 166#ifdef ATH_NF_PER_CHAN 167typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST; 168#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL) 169#else 170typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST; 171#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist) 172#endif /* ATH_NF_PER_CHAN */ 173 174/* 175 * Internal per-channel state. These are found 176 * using ic_devdata in the ieee80211_channel. 177 */ 178typedef struct { 179 uint16_t channel; /* h/w frequency, NB: may be mapped */ 180 uint8_t privFlags; 181#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 182#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 183#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 184#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 185 uint8_t calValid; /* bitmask of cal types */ 186 int8_t iCoff; 187 int8_t qCoff; 188 int16_t rawNoiseFloor; 189 int16_t noiseFloorAdjust; 190#ifdef AH_SUPPORT_AR5416 191 int16_t noiseFloorCtl[AH_MAX_CHAINS]; 192 int16_t noiseFloorExt[AH_MAX_CHAINS]; 193#endif /* AH_SUPPORT_AR5416 */ 194 uint16_t mainSpur; /* cached spur value for this channel */ 195 196 /*XXX TODO: make these part of privFlags */ 197 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */ 198 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */ 199 int one_time_cals_done; 200 HAL_CHAN_NFCAL_HIST nf_cal_hist; 201} HAL_CHANNEL_INTERNAL; 202 203/* channel requires noise floor check */ 204#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 205 206/* all full-width channels */ 207#define IEEE80211_CHAN_ALLFULL \ 208 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 209#define IEEE80211_CHAN_ALLTURBOFULL \ 210 (IEEE80211_CHAN_ALLTURBO - \ 211 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 212 213typedef struct { 214 uint32_t halChanSpreadSupport : 1, 215 halSleepAfterBeaconBroken : 1, 216 halCompressSupport : 1, 217 halBurstSupport : 1, 218 halFastFramesSupport : 1, 219 halChapTuningSupport : 1, 220 halTurboGSupport : 1, 221 halTurboPrimeSupport : 1, 222 halMicAesCcmSupport : 1, 223 halMicCkipSupport : 1, 224 halMicTkipSupport : 1, 225 halTkipMicTxRxKeySupport : 1, 226 halCipherAesCcmSupport : 1, 227 halCipherCkipSupport : 1, 228 halCipherTkipSupport : 1, 229 halPSPollBroken : 1, 230 halVEOLSupport : 1, 231 halBssIdMaskSupport : 1, 232 halMcastKeySrchSupport : 1, 233 halTsfAddSupport : 1, 234 halChanHalfRate : 1, 235 halChanQuarterRate : 1, 236 halHTSupport : 1, 237 halHTSGI20Support : 1, 238 halRfSilentSupport : 1, 239 halHwPhyCounterSupport : 1, 240 halWowSupport : 1, 241 halWowMatchPatternExact : 1, 242 halAutoSleepSupport : 1, 243 halFastCCSupport : 1, 244 halBtCoexSupport : 1; 245 uint32_t halRxStbcSupport : 1, 246 halTxStbcSupport : 1, 247 halGTTSupport : 1, 248 halCSTSupport : 1, 249 halRifsRxSupport : 1, 250 halRifsTxSupport : 1, 251 hal4AddrAggrSupport : 1, 252 halExtChanDfsSupport : 1, 253 halUseCombinedRadarRssi : 1, 254 halForcePpmSupport : 1, 255 halEnhancedPmSupport : 1, 256 halEnhancedDfsSupport : 1, 257 halMbssidAggrSupport : 1, 258 halBssidMatchSupport : 1, 259 hal4kbSplitTransSupport : 1, 260 halHasRxSelfLinkedTail : 1, 261 halSupportsFastClock5GHz : 1, 262 halHasLongRxDescTsf : 1, 263 halHasBBReadWar : 1, 264 halSerialiseRegWar : 1, 265 halMciSupport : 1, 266 halRxTxAbortSupport : 1, 267 halPaprdEnabled : 1, 268 halHasUapsdSupport : 1, 269 halWpsPushButtonSupport : 1, 270 halBtCoexApsmWar : 1, 271 halGenTimerSupport : 1, 272 halLDPCSupport : 1, 273 halHwBeaconProcSupport : 1, 274 halEnhancedDmaSupport : 1; 275 uint32_t halIsrRacSupport : 1, 276 halApmEnable : 1, 277 halIntrMitigation : 1, 278 hal49GhzSupport : 1, 279 halAntDivCombSupport : 1; 280 281 uint32_t halWirelessModes; 282 uint16_t halTotalQueues; 283 uint16_t halKeyCacheSize; 284 uint16_t halLow5GhzChan, halHigh5GhzChan; 285 uint16_t halLow2GhzChan, halHigh2GhzChan; 286 int halTstampPrecision; 287 int halRtsAggrLimit; 288 uint8_t halTxChainMask; 289 uint8_t halRxChainMask; 290 uint8_t halNumGpioPins; 291 uint8_t halNumAntCfg2GHz; 292 uint8_t halNumAntCfg5GHz; 293 uint32_t halIntrMask; 294 uint8_t halTxStreams; 295 uint8_t halRxStreams; 296 HAL_MFP_OPT_T halMfpSupport; 297 298 /* AR9300 HAL porting capabilities */ 299 int hal_paprd_enabled; 300 int hal_pcie_lcr_offset; 301 int hal_pcie_lcr_extsync_en; 302 int halNumTxMaps; 303 int halTxDescLen; 304 int halTxStatusLen; 305 int halRxStatusLen; 306 int halRxHpFifoDepth; 307 int halRxLpFifoDepth; 308 uint32_t halRegCap; /* XXX needed? */ 309 int halNumMRRetries; 310 int hal_ani_poll_interval; 311 int hal_channel_switch_time_usec; 312} HAL_CAPABILITIES; 313 314struct regDomain; 315 316/* 317 * Definitions for ah_flags in ath_hal_private 318 */ 319#define AH_USE_EEPROM 0x1 320#define AH_IS_HB63 0x2 321 322/* 323 * The ``private area'' follows immediately after the ``public area'' 324 * in the data structure returned by ath_hal_attach. Private data are 325 * used by device-independent code such as the regulatory domain support. 326 * In general, code within the HAL should never depend on data in the 327 * public area. Instead any public data needed internally should be 328 * shadowed here. 329 * 330 * When declaring a device-specific ath_hal data structure this structure 331 * is assumed to at the front; e.g. 332 * 333 * struct ath_hal_5212 { 334 * struct ath_hal_private ah_priv; 335 * ... 336 * }; 337 * 338 * It might be better to manage the method pointers in this structure 339 * using an indirect pointer to a read-only data structure but this would 340 * disallow class-style method overriding. 341 */ 342struct ath_hal_private { 343 struct ath_hal h; /* public area */ 344 345 /* NB: all methods go first to simplify initialization */ 346 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 347 uint16_t channelFlags, 348 uint16_t *lowChannel, uint16_t *highChannel); 349 u_int (*ah_getWirelessModes)(struct ath_hal*); 350 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 351 uint16_t *data); 352 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 353 uint16_t data); 354 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 355 struct ieee80211_channel *); 356 int16_t (*ah_getNfAdjust)(struct ath_hal *, 357 const HAL_CHANNEL_INTERNAL*); 358 void (*ah_getNoiseFloor)(struct ath_hal *, 359 int16_t nfarray[]); 360 361 void *ah_eeprom; /* opaque EEPROM state */ 362 uint16_t ah_eeversion; /* EEPROM version */ 363 void (*ah_eepromDetach)(struct ath_hal *); 364 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 365 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 366 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 367 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 368 const void *args, uint32_t argsize, 369 void **result, uint32_t *resultsize); 370 371 /* 372 * Device revision information. 373 */ 374 uint16_t ah_devid; /* PCI device ID */ 375 uint16_t ah_subvendorid; /* PCI subvendor ID */ 376 uint32_t ah_macVersion; /* MAC version id */ 377 uint16_t ah_macRev; /* MAC revision */ 378 uint16_t ah_phyRev; /* PHY revision */ 379 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 380 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 381 uint32_t ah_flags; /* misc flags */ 382 uint8_t ah_ispcie; /* PCIE, special treatment */ 383 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 384 385 HAL_OPMODE ah_opmode; /* operating mode from reset */ 386 const struct ieee80211_channel *ah_curchan;/* operating channel */ 387 HAL_CAPABILITIES ah_caps; /* device capabilities */ 388 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 389 int16_t ah_powerLimit; /* tx power cap */ 390 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 391 u_int ah_tpScale; /* tx power scale factor */ 392 uint32_t ah_11nCompat; /* 11n compat controls */ 393 394 /* 395 * State for regulatory domain handling. 396 */ 397 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 398 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 399 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 400 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 401 u_int ah_nchan; /* valid items in ah_channels */ 402 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 403 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 404 405 uint8_t ah_coverageClass; /* coverage class */ 406 /* 407 * RF Silent handling; setup according to the EEPROM. 408 */ 409 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 410 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 411 /* 412 * Diagnostic support for discriminating HIUERR reports. 413 */ 414 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 415 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 416 417#ifndef ATH_NF_PER_CHAN 418 HAL_NFCAL_HIST_FULL nf_cal_hist; 419#endif /* ! ATH_NF_PER_CHAN */ 420}; 421 422#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 423 424#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 425 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 426#define ath_hal_getWirelessModes(_ah) \ 427 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 428#define ath_hal_eepromRead(_ah, _off, _data) \ 429 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 430#define ath_hal_eepromWrite(_ah, _off, _data) \ 431 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 432#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 433 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 434#define ath_hal_gpioCfgInput(_ah, _gpio) \ 435 (_ah)->ah_gpioCfgInput(_ah, _gpio) 436#define ath_hal_gpioGet(_ah, _gpio) \ 437 (_ah)->ah_gpioGet(_ah, _gpio) 438#define ath_hal_gpioSet(_ah, _gpio, _val) \ 439 (_ah)->ah_gpioSet(_ah, _gpio, _val) 440#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 441 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 442#define ath_hal_getpowerlimits(_ah, _chan) \ 443 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 444#define ath_hal_getNfAdjust(_ah, _c) \ 445 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 446#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 447 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 448#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 449 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 450#define ath_hal_disablePCIE(_ah) \ 451 (_ah)->ah_disablePCIE(_ah) 452#define ath_hal_setInterrupts(_ah, _mask) \ 453 (_ah)->ah_setInterrupts(_ah, _mask) 454 455#define ath_hal_isrfkillenabled(_ah) \ 456 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 457#define ath_hal_enable_rfkill(_ah, _v) \ 458 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 459#define ath_hal_hasrfkill_int(_ah) \ 460 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 461 462#define ath_hal_eepromDetach(_ah) do { \ 463 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 464 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 465} while (0) 466#define ath_hal_eepromGet(_ah, _param, _val) \ 467 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 468#define ath_hal_eepromSet(_ah, _param, _val) \ 469 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 470#define ath_hal_eepromGetFlag(_ah, _param) \ 471 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 472#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 473 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 474#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 475 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 476 477#ifndef _NET_IF_IEEE80211_H_ 478/* 479 * Stuff that would naturally come from _ieee80211.h 480 */ 481#define IEEE80211_ADDR_LEN 6 482 483#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 484#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 485#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 486 487#define IEEE80211_CRC_LEN 4 488 489#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 490 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 491#endif /* _NET_IF_IEEE80211_H_ */ 492 493#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 494 495#define INIT_AIFS 2 496#define INIT_CWMIN 15 497#define INIT_CWMIN_11B 31 498#define INIT_CWMAX 1023 499#define INIT_SH_RETRY 10 500#define INIT_LG_RETRY 10 501#define INIT_SSH_RETRY 32 502#define INIT_SLG_RETRY 32 503 504typedef struct { 505 uint32_t tqi_ver; /* HAL TXQ verson */ 506 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 507 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 508 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 509 uint32_t tqi_priority; 510 uint32_t tqi_aifs; /* aifs */ 511 uint32_t tqi_cwmin; /* cwMin */ 512 uint32_t tqi_cwmax; /* cwMax */ 513 uint16_t tqi_shretry; /* frame short retry limit */ 514 uint16_t tqi_lgretry; /* frame long retry limit */ 515 uint32_t tqi_cbrPeriod; 516 uint32_t tqi_cbrOverflowLimit; 517 uint32_t tqi_burstTime; 518 uint32_t tqi_readyTime; 519 uint32_t tqi_physCompBuf; 520 uint32_t tqi_intFlags; /* flags for internal use */ 521} HAL_TX_QUEUE_INFO; 522 523extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 524 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 525extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 526 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 527 528#define HAL_SPUR_VAL_MASK 0x3FFF 529#define HAL_SPUR_CHAN_WIDTH 87 530#define HAL_BIN_WIDTH_BASE_100HZ 3125 531#define HAL_BIN_WIDTH_TURBO_100HZ 6250 532#define HAL_MAX_BINS_ALLOWED 28 533 534#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 535#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 536 537#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 538 539/* 540 * Deduce if the host cpu has big- or litt-endian byte order. 541 */ 542static __inline__ int 543isBigEndian(void) 544{ 545 union { 546 int32_t i; 547 char c[4]; 548 } u; 549 u.i = 1; 550 return (u.c[0] == 0); 551} 552 553/* unalligned little endian access */ 554#define LE_READ_2(p) \ 555 ((uint16_t) \ 556 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 557#define LE_READ_4(p) \ 558 ((uint32_t) \ 559 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 560 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 561 562/* 563 * Register manipulation macros that expect bit field defines 564 * to follow the convention that an _S suffix is appended for 565 * a shift count, while the field mask has no suffix. 566 */ 567#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 568#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 569#define OS_REG_RMW(_a, _r, _set, _clr) \ 570 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 571#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 572 OS_REG_WRITE(_a, _r, \ 573 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 574#define OS_REG_SET_BIT(_a, _r, _f) \ 575 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 576#define OS_REG_CLR_BIT(_a, _r, _f) \ 577 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 578#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 579 ((OS_REG_READ(_a, _r) & (_f)) != 0) 580#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \ 581 OS_REG_WRITE(_a, _r, \ 582 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \ 583 (((_v) << _f##_S) & (_f<<_f##_S))) 584#define OS_REG_READ_FIELD(_a, _r, _f) \ 585 (((OS_REG_READ(_a, _r) & _f) >> _f##_S)) 586#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \ 587 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f)) 588 589/* Analog register writes may require a delay between each one (eg Merlin?) */ 590#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 591 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 592 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 593#define OS_A_REG_WRITE(_a, _r, _v) \ 594 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 595 596/* wait for the register contents to have the specified value */ 597extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 598 uint32_t mask, uint32_t val); 599extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 600 uint32_t mask, uint32_t val, uint32_t timeout); 601 602/* return the first n bits in val reversed */ 603extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 604 605/* printf interfaces */ 606extern void ath_hal_printf(struct ath_hal *, const char*, ...) 607 __printflike(2,3); 608extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 609 __printflike(2, 0); 610extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 611 612/* allocate and free memory */ 613extern void *ath_hal_malloc(size_t); 614extern void ath_hal_free(void *); 615 616/* common debugging interfaces */ 617#ifdef AH_DEBUG 618#include "ah_debug.h" 619extern int ath_hal_debug; /* Global debug flags */ 620 621/* 622 * The typecast is purely because some callers will pass in 623 * AH_NULL directly rather than using a NULL ath_hal pointer. 624 */ 625#define HALDEBUG(_ah, __m, ...) \ 626 do { \ 627 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 628 ath_hal_debug & (__m) || \ 629 ((_ah) != NULL && \ 630 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 631 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 632 } \ 633 } while(0); 634 635extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 636 __printflike(3,4); 637#else 638#define HALDEBUG(_ah, __m, ...) 639#endif /* AH_DEBUG */ 640 641/* 642 * Register logging definitions shared with ardecode. 643 */ 644#include "ah_decode.h" 645 646/* 647 * Common assertion interface. Note: it is a bad idea to generate 648 * an assertion failure for any recoverable event. Instead catch 649 * the violation and, if possible, fix it up or recover from it; either 650 * with an error return value or a diagnostic messages. System software 651 * does not panic unless the situation is hopeless. 652 */ 653#ifdef AH_ASSERT 654extern void ath_hal_assert_failed(const char* filename, 655 int lineno, const char* msg); 656 657#define HALASSERT(_x) do { \ 658 if (!(_x)) { \ 659 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 660 } \ 661} while (0) 662#else 663#define HALASSERT(_x) 664#endif /* AH_ASSERT */ 665 666/* 667 * Regulatory domain support. 668 */ 669 670/* 671 * Return the max allowed antenna gain and apply any regulatory 672 * domain specific changes. 673 */ 674u_int ath_hal_getantennareduction(struct ath_hal *ah, 675 const struct ieee80211_channel *chan, u_int twiceGain); 676 677/* 678 * Return the test group for the specific channel based on 679 * the current regulatory setup. 680 */ 681u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 682 683/* 684 * Map a public channel definition to the corresponding 685 * internal data structure. This implicitly specifies 686 * whether or not the specified channel is ok to use 687 * based on the current regulatory domain constraints. 688 */ 689#ifndef AH_DEBUG 690static OS_INLINE HAL_CHANNEL_INTERNAL * 691ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 692{ 693 HAL_CHANNEL_INTERNAL *cc; 694 695 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 696 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 697 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 698 return cc; 699} 700#else 701/* NB: non-inline version that checks state */ 702HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 703 const struct ieee80211_channel *); 704#endif /* AH_DEBUG */ 705 706/* 707 * Return the h/w frequency for a channel. This may be 708 * different from ic_freq if this is a GSM device that 709 * takes 2.4GHz frequencies and down-converts them. 710 */ 711static OS_INLINE uint16_t 712ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 713{ 714 return ath_hal_checkchannel(ah, c)->channel; 715} 716 717/* 718 * Convert between microseconds and core system clocks. 719 */ 720extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 721extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 722 723/* 724 * Generic get/set capability support. Each chip overrides 725 * this routine to support chip-specific capabilities. 726 */ 727extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 728 HAL_CAPABILITY_TYPE type, uint32_t capability, 729 uint32_t *result); 730extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 731 HAL_CAPABILITY_TYPE type, uint32_t capability, 732 uint32_t setting, HAL_STATUS *status); 733 734/* The diagnostic codes used to be internally defined here -adrian */ 735#include "ah_diagcodes.h" 736 737/* 738 * The AR5416 and later HALs have MAC and baseband hang checking. 739 */ 740typedef struct { 741 uint32_t hang_reg_offset; 742 uint32_t hang_val; 743 uint32_t hang_mask; 744 uint32_t hang_offset; 745} hal_hw_hang_check_t; 746 747typedef struct { 748 uint32_t dma_dbg_3; 749 uint32_t dma_dbg_4; 750 uint32_t dma_dbg_5; 751 uint32_t dma_dbg_6; 752} mac_dbg_regs_t; 753 754typedef enum { 755 dcu_chain_state = 0x1, 756 dcu_complete_state = 0x2, 757 qcu_state = 0x4, 758 qcu_fsp_ok = 0x8, 759 qcu_fsp_state = 0x10, 760 qcu_stitch_state = 0x20, 761 qcu_fetch_state = 0x40, 762 qcu_complete_state = 0x80 763} hal_mac_hangs_t; 764 765typedef struct { 766 int states; 767 uint8_t dcu_chain_state; 768 uint8_t dcu_complete_state; 769 uint8_t qcu_state; 770 uint8_t qcu_fsp_ok; 771 uint8_t qcu_fsp_state; 772 uint8_t qcu_stitch_state; 773 uint8_t qcu_fetch_state; 774 uint8_t qcu_complete_state; 775} hal_mac_hang_check_t; 776 777enum { 778 HAL_BB_HANG_DFS = 0x0001, 779 HAL_BB_HANG_RIFS = 0x0002, 780 HAL_BB_HANG_RX_CLEAR = 0x0004, 781 HAL_BB_HANG_UNKNOWN = 0x0080, 782 783 HAL_MAC_HANG_SIG1 = 0x0100, 784 HAL_MAC_HANG_SIG2 = 0x0200, 785 HAL_MAC_HANG_UNKNOWN = 0x8000, 786 787 HAL_BB_HANGS = HAL_BB_HANG_DFS 788 | HAL_BB_HANG_RIFS 789 | HAL_BB_HANG_RX_CLEAR 790 | HAL_BB_HANG_UNKNOWN, 791 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 792 | HAL_MAC_HANG_SIG2 793 | HAL_MAC_HANG_UNKNOWN, 794}; 795 796/* Merge these with above */ 797typedef enum hal_hw_hangs { 798 HAL_DFS_BB_HANG_WAR = 0x1, 799 HAL_RIFS_BB_HANG_WAR = 0x2, 800 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4, 801 HAL_MAC_HANG_WAR = 0x8, 802 HAL_PHYRESTART_CLR_WAR = 0x10, 803 HAL_MAC_HANG_DETECTED = 0x40000000, 804 HAL_BB_HANG_DETECTED = 0x80000000 805} hal_hw_hangs_t; 806 807/* 808 * Device revision information. 809 */ 810typedef struct { 811 uint16_t ah_devid; /* PCI device ID */ 812 uint16_t ah_subvendorid; /* PCI subvendor ID */ 813 uint32_t ah_macVersion; /* MAC version id */ 814 uint16_t ah_macRev; /* MAC revision */ 815 uint16_t ah_phyRev; /* PHY revision */ 816 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 817 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 818} HAL_REVS; 819 820/* 821 * Argument payload for HAL_DIAG_SETKEY. 822 */ 823typedef struct { 824 HAL_KEYVAL dk_keyval; 825 uint16_t dk_keyix; /* key index */ 826 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 827 int dk_xor; /* XOR key data */ 828} HAL_DIAG_KEYVAL; 829 830/* 831 * Argument payload for HAL_DIAG_EEWRITE. 832 */ 833typedef struct { 834 uint16_t ee_off; /* eeprom offset */ 835 uint16_t ee_data; /* write data */ 836} HAL_DIAG_EEVAL; 837 838 839typedef struct { 840 u_int offset; /* reg offset */ 841 uint32_t val; /* reg value */ 842} HAL_DIAG_REGVAL; 843 844/* 845 * 11n compatibility tweaks. 846 */ 847#define HAL_DIAG_11N_SERVICES 0x00000003 848#define HAL_DIAG_11N_SERVICES_S 0 849#define HAL_DIAG_11N_TXSTOMP 0x0000000c 850#define HAL_DIAG_11N_TXSTOMP_S 2 851 852typedef struct { 853 int maxNoiseImmunityLevel; /* [0..4] */ 854 int totalSizeDesired[5]; 855 int coarseHigh[5]; 856 int coarseLow[5]; 857 int firpwr[5]; 858 859 int maxSpurImmunityLevel; /* [0..7] */ 860 int cycPwrThr1[8]; 861 862 int maxFirstepLevel; /* [0..2] */ 863 int firstep[3]; 864 865 uint32_t ofdmTrigHigh; 866 uint32_t ofdmTrigLow; 867 int32_t cckTrigHigh; 868 int32_t cckTrigLow; 869 int32_t rssiThrLow; 870 int32_t rssiThrHigh; 871 872 int period; /* update listen period */ 873} HAL_ANI_PARAMS; 874 875extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 876 const void *args, uint32_t argsize, 877 void **result, uint32_t *resultsize); 878 879/* 880 * Setup a h/w rate table for use. 881 */ 882extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 883 884/* 885 * Common routine for implementing getChanNoise api. 886 */ 887int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 888 889/* 890 * Initialization support. 891 */ 892typedef struct { 893 const uint32_t *data; 894 int rows, cols; 895} HAL_INI_ARRAY; 896 897#define HAL_INI_INIT(_ia, _data, _cols) do { \ 898 (_ia)->data = (const uint32_t *)(_data); \ 899 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 900 (_ia)->cols = (_cols); \ 901} while (0) 902#define HAL_INI_VAL(_ia, _r, _c) \ 903 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 904 905/* 906 * OS_DELAY() does a PIO READ on the PCI bus which allows 907 * other cards' DMA reads to complete in the middle of our reset. 908 */ 909#define DMA_YIELD(x) do { \ 910 if ((++(x) % 64) == 0) \ 911 OS_DELAY(1); \ 912} while (0) 913 914#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 915 int r; \ 916 for (r = 0; r < N(regArray); r++) { \ 917 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 918 DMA_YIELD(regWr); \ 919 } \ 920} while (0) 921 922#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 923 int r; \ 924 for (r = 0; r < N(regArray); r++) { \ 925 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 926 DMA_YIELD(regWr); \ 927 } \ 928} while (0) 929 930extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 931 int col, int regWr); 932extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 933 int col); 934extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 935 const uint32_t data[], int regWr); 936 937#define CCK_SIFS_TIME 10 938#define CCK_PREAMBLE_BITS 144 939#define CCK_PLCP_BITS 48 940 941#define OFDM_SIFS_TIME 16 942#define OFDM_PREAMBLE_TIME 20 943#define OFDM_PLCP_BITS 22 944#define OFDM_SYMBOL_TIME 4 945 946#define OFDM_HALF_SIFS_TIME 32 947#define OFDM_HALF_PREAMBLE_TIME 40 948#define OFDM_HALF_PLCP_BITS 22 949#define OFDM_HALF_SYMBOL_TIME 8 950 951#define OFDM_QUARTER_SIFS_TIME 64 952#define OFDM_QUARTER_PREAMBLE_TIME 80 953#define OFDM_QUARTER_PLCP_BITS 22 954#define OFDM_QUARTER_SYMBOL_TIME 16 955 956#define TURBO_SIFS_TIME 8 957#define TURBO_PREAMBLE_TIME 14 958#define TURBO_PLCP_BITS 22 959#define TURBO_SYMBOL_TIME 4 960 961#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 962 963/* Generic EEPROM board value functions */ 964extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 965 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 966extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 967 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 968 uint8_t *pRetVpdList); 969extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 970 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 971 972/* Whether 5ghz fast clock is needed */ 973/* 974 * The chipset (Merlin, AR9300/later) should set the capability flag below; 975 * this flag simply says that the hardware can do it, not that the EEPROM 976 * says it can. 977 * 978 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 979 * if the relevant eeprom flag is set. 980 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 981 * by default. 982 */ 983#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 984 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 985 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 986 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 987 988/* 989 * Fetch the maximum regulatory domain power for the given channel 990 * in 1/2dBm steps. 991 */ 992static inline int 993ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp, 994 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan) 995{ 996 struct ath_hal *ah = &ahp->h; 997 998 if (! chan) { 999 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__); 1000 return (0); 1001 } 1002 return (chan->ic_maxpower); 1003} 1004 1005/* 1006 * Get the maximum antenna gain allowed, in 1/2dBm steps. 1007 */ 1008static inline int 1009ath_hal_getantennaallowed(struct ath_hal *ah, 1010 const struct ieee80211_channel *chan) 1011{ 1012 1013 if (! chan) 1014 return (0); 1015 1016 return (chan->ic_maxantgain); 1017} 1018 1019 1020#endif /* _ATH_AH_INTERAL_H_ */ 1021