ah_internal.h revision 239802
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 239802 2012-08-29 04:09:54Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_STATUS *error); 95}; 96#ifndef AH_CHIP 97#define AH_CHIP(_name, _probe, _attach) \ 98static struct ath_hal_chip _name##_chip = { \ 99 .name = #_name, \ 100 .probe = _probe, \ 101 .attach = _attach \ 102}; \ 103OS_DATA_SET(ah_chips, _name##_chip) 104#endif 105 106/* 107 * Each RF backend registers to offer support; this is mostly 108 * used by multi-chip 5212 solutions. Single-chip solutions 109 * have a fixed idea about which RF to use. 110 */ 111struct ath_hal_rf { 112 const char *name; 113 HAL_BOOL (*probe)(struct ath_hal *ah); 114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 115}; 116#ifndef AH_RF 117#define AH_RF(_name, _probe, _attach) \ 118static struct ath_hal_rf _name##_rf = { \ 119 .name = __STRING(_name), \ 120 .probe = _probe, \ 121 .attach = _attach \ 122}; \ 123OS_DATA_SET(ah_rfs, _name##_rf) 124#endif 125 126struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 127 128/* 129 * Maximum number of internal channels. Entries are per unique 130 * frequency so this might be need to be increased to handle all 131 * usage cases; typically no more than 32 are really needed but 132 * dynamically allocating the data structures is a bit painful 133 * right now. 134 */ 135#ifndef AH_MAXCHAN 136#define AH_MAXCHAN 96 137#endif 138 139/* 140 * Internal per-channel state. These are found 141 * using ic_devdata in the ieee80211_channel. 142 */ 143typedef struct { 144 uint16_t channel; /* h/w frequency, NB: may be mapped */ 145 uint8_t privFlags; 146#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 147#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 148#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 149#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 150 uint8_t calValid; /* bitmask of cal types */ 151 int8_t iCoff; 152 int8_t qCoff; 153 int16_t rawNoiseFloor; 154 int16_t noiseFloorAdjust; 155#ifdef AH_SUPPORT_AR5416 156 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 157 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 158#endif /* AH_SUPPORT_AR5416 */ 159 uint16_t mainSpur; /* cached spur value for this channel */ 160} HAL_CHANNEL_INTERNAL; 161 162/* channel requires noise floor check */ 163#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 164 165/* all full-width channels */ 166#define IEEE80211_CHAN_ALLFULL \ 167 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 168#define IEEE80211_CHAN_ALLTURBOFULL \ 169 (IEEE80211_CHAN_ALLTURBO - \ 170 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 171 172typedef struct { 173 uint32_t halChanSpreadSupport : 1, 174 halSleepAfterBeaconBroken : 1, 175 halCompressSupport : 1, 176 halBurstSupport : 1, 177 halFastFramesSupport : 1, 178 halChapTuningSupport : 1, 179 halTurboGSupport : 1, 180 halTurboPrimeSupport : 1, 181 halMicAesCcmSupport : 1, 182 halMicCkipSupport : 1, 183 halMicTkipSupport : 1, 184 halTkipMicTxRxKeySupport : 1, 185 halCipherAesCcmSupport : 1, 186 halCipherCkipSupport : 1, 187 halCipherTkipSupport : 1, 188 halPSPollBroken : 1, 189 halVEOLSupport : 1, 190 halBssIdMaskSupport : 1, 191 halMcastKeySrchSupport : 1, 192 halTsfAddSupport : 1, 193 halChanHalfRate : 1, 194 halChanQuarterRate : 1, 195 halHTSupport : 1, 196 halHTSGI20Support : 1, 197 halRfSilentSupport : 1, 198 halHwPhyCounterSupport : 1, 199 halWowSupport : 1, 200 halWowMatchPatternExact : 1, 201 halAutoSleepSupport : 1, 202 halFastCCSupport : 1, 203 halBtCoexSupport : 1; 204 uint32_t halRxStbcSupport : 1, 205 halTxStbcSupport : 1, 206 halGTTSupport : 1, 207 halCSTSupport : 1, 208 halRifsRxSupport : 1, 209 halRifsTxSupport : 1, 210 hal4AddrAggrSupport : 1, 211 halExtChanDfsSupport : 1, 212 halUseCombinedRadarRssi : 1, 213 halForcePpmSupport : 1, 214 halEnhancedPmSupport : 1, 215 halEnhancedDfsSupport : 1, 216 halMbssidAggrSupport : 1, 217 halBssidMatchSupport : 1, 218 hal4kbSplitTransSupport : 1, 219 halHasRxSelfLinkedTail : 1, 220 halSupportsFastClock5GHz : 1, 221 halHasLongRxDescTsf : 1, 222 halHasBBReadWar : 1, 223 halSerialiseRegWar : 1, 224 halMciSupport : 1, 225 halRxTxAbortSupport : 1, 226 halPaprdEnabled : 1, 227 halHasUapsdSupport : 1, 228 halWpsPushButtonSupport : 1, 229 halBtCoexApsmWar : 1, 230 halGenTimerSupport : 1, 231 halLDPCSupport : 1, 232 halHwBeaconProcSupport : 1, 233 halEnhancedDmaSupport : 1; 234 uint32_t halIsrRacSupport : 1, 235 halApmEnable : 1, 236 halIntrMitigation : 1, 237 hal49GhzSupport : 1, 238 halAntDivCombSupport : 1; 239 240 uint32_t halWirelessModes; 241 uint16_t halTotalQueues; 242 uint16_t halKeyCacheSize; 243 uint16_t halLow5GhzChan, halHigh5GhzChan; 244 uint16_t halLow2GhzChan, halHigh2GhzChan; 245 int halTstampPrecision; 246 int halRtsAggrLimit; 247 uint8_t halTxChainMask; 248 uint8_t halRxChainMask; 249 uint8_t halNumGpioPins; 250 uint8_t halNumAntCfg2GHz; 251 uint8_t halNumAntCfg5GHz; 252 uint32_t halIntrMask; 253 uint8_t halTxStreams; 254 uint8_t halRxStreams; 255 HAL_MFP_OPT_T halMfpSupport; 256 int halNumTxMaps; 257 int halTxDescLen; 258 int halTxStatusLen; 259 int halRxStatusLen; 260 int halRxHpFifoDepth; 261 int halRxLpFifoDepth; 262 int halNumMRRetries; 263} HAL_CAPABILITIES; 264 265struct regDomain; 266 267/* 268 * Definitions for ah_flags in ath_hal_private 269 */ 270#define AH_USE_EEPROM 0x1 271#define AH_IS_HB63 0x2 272 273/* 274 * The ``private area'' follows immediately after the ``public area'' 275 * in the data structure returned by ath_hal_attach. Private data are 276 * used by device-independent code such as the regulatory domain support. 277 * In general, code within the HAL should never depend on data in the 278 * public area. Instead any public data needed internally should be 279 * shadowed here. 280 * 281 * When declaring a device-specific ath_hal data structure this structure 282 * is assumed to at the front; e.g. 283 * 284 * struct ath_hal_5212 { 285 * struct ath_hal_private ah_priv; 286 * ... 287 * }; 288 * 289 * It might be better to manage the method pointers in this structure 290 * using an indirect pointer to a read-only data structure but this would 291 * disallow class-style method overriding. 292 */ 293struct ath_hal_private { 294 struct ath_hal h; /* public area */ 295 296 /* NB: all methods go first to simplify initialization */ 297 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 298 uint16_t channelFlags, 299 uint16_t *lowChannel, uint16_t *highChannel); 300 u_int (*ah_getWirelessModes)(struct ath_hal*); 301 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 302 uint16_t *data); 303 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 304 uint16_t data); 305 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 306 struct ieee80211_channel *); 307 int16_t (*ah_getNfAdjust)(struct ath_hal *, 308 const HAL_CHANNEL_INTERNAL*); 309 void (*ah_getNoiseFloor)(struct ath_hal *, 310 int16_t nfarray[]); 311 312 void *ah_eeprom; /* opaque EEPROM state */ 313 uint16_t ah_eeversion; /* EEPROM version */ 314 void (*ah_eepromDetach)(struct ath_hal *); 315 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 316 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 317 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 318 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 319 const void *args, uint32_t argsize, 320 void **result, uint32_t *resultsize); 321 322 /* 323 * Device revision information. 324 */ 325 uint16_t ah_devid; /* PCI device ID */ 326 uint16_t ah_subvendorid; /* PCI subvendor ID */ 327 uint32_t ah_macVersion; /* MAC version id */ 328 uint16_t ah_macRev; /* MAC revision */ 329 uint16_t ah_phyRev; /* PHY revision */ 330 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 331 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 332 uint32_t ah_flags; /* misc flags */ 333 uint8_t ah_ispcie; /* PCIE, special treatment */ 334 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 335 336 HAL_OPMODE ah_opmode; /* operating mode from reset */ 337 const struct ieee80211_channel *ah_curchan;/* operating channel */ 338 HAL_CAPABILITIES ah_caps; /* device capabilities */ 339 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 340 int16_t ah_powerLimit; /* tx power cap */ 341 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 342 u_int ah_tpScale; /* tx power scale factor */ 343 uint32_t ah_11nCompat; /* 11n compat controls */ 344 345 /* 346 * State for regulatory domain handling. 347 */ 348 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 349 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 350 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 351 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 352 u_int ah_nchan; /* valid items in ah_channels */ 353 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 354 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 355 356 uint8_t ah_coverageClass; /* coverage class */ 357 /* 358 * RF Silent handling; setup according to the EEPROM. 359 */ 360 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 361 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 362 /* 363 * Diagnostic support for discriminating HIUERR reports. 364 */ 365 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 366 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 367}; 368 369#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 370 371#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 372 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 373#define ath_hal_getWirelessModes(_ah) \ 374 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 375#define ath_hal_eepromRead(_ah, _off, _data) \ 376 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 377#define ath_hal_eepromWrite(_ah, _off, _data) \ 378 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 379#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 380 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 381#define ath_hal_gpioCfgInput(_ah, _gpio) \ 382 (_ah)->ah_gpioCfgInput(_ah, _gpio) 383#define ath_hal_gpioGet(_ah, _gpio) \ 384 (_ah)->ah_gpioGet(_ah, _gpio) 385#define ath_hal_gpioSet(_ah, _gpio, _val) \ 386 (_ah)->ah_gpioSet(_ah, _gpio, _val) 387#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 388 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 389#define ath_hal_getpowerlimits(_ah, _chan) \ 390 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 391#define ath_hal_getNfAdjust(_ah, _c) \ 392 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 393#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 394 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 395#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 396 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 397#define ath_hal_disablePCIE(_ah) \ 398 (_ah)->ah_disablePCIE(_ah) 399#define ath_hal_setInterrupts(_ah, _mask) \ 400 (_ah)->ah_setInterrupts(_ah, _mask) 401 402#define ath_hal_isrfkillenabled(_ah) \ 403 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 404#define ath_hal_enable_rfkill(_ah, _v) \ 405 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 406#define ath_hal_hasrfkill_int(_ah) \ 407 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 408 409#define ath_hal_eepromDetach(_ah) do { \ 410 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 411 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 412} while (0) 413#define ath_hal_eepromGet(_ah, _param, _val) \ 414 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 415#define ath_hal_eepromSet(_ah, _param, _val) \ 416 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 417#define ath_hal_eepromGetFlag(_ah, _param) \ 418 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 419#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 420 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 421#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 422 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 423 424#ifndef _NET_IF_IEEE80211_H_ 425/* 426 * Stuff that would naturally come from _ieee80211.h 427 */ 428#define IEEE80211_ADDR_LEN 6 429 430#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 431#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 432#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 433 434#define IEEE80211_CRC_LEN 4 435 436#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 437 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 438#endif /* _NET_IF_IEEE80211_H_ */ 439 440#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 441 442#define INIT_AIFS 2 443#define INIT_CWMIN 15 444#define INIT_CWMIN_11B 31 445#define INIT_CWMAX 1023 446#define INIT_SH_RETRY 10 447#define INIT_LG_RETRY 10 448#define INIT_SSH_RETRY 32 449#define INIT_SLG_RETRY 32 450 451typedef struct { 452 uint32_t tqi_ver; /* HAL TXQ verson */ 453 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 454 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 455 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 456 uint32_t tqi_priority; 457 uint32_t tqi_aifs; /* aifs */ 458 uint32_t tqi_cwmin; /* cwMin */ 459 uint32_t tqi_cwmax; /* cwMax */ 460 uint16_t tqi_shretry; /* frame short retry limit */ 461 uint16_t tqi_lgretry; /* frame long retry limit */ 462 uint32_t tqi_cbrPeriod; 463 uint32_t tqi_cbrOverflowLimit; 464 uint32_t tqi_burstTime; 465 uint32_t tqi_readyTime; 466 uint32_t tqi_physCompBuf; 467 uint32_t tqi_intFlags; /* flags for internal use */ 468} HAL_TX_QUEUE_INFO; 469 470extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 471 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 472extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 473 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 474 475#define HAL_SPUR_VAL_MASK 0x3FFF 476#define HAL_SPUR_CHAN_WIDTH 87 477#define HAL_BIN_WIDTH_BASE_100HZ 3125 478#define HAL_BIN_WIDTH_TURBO_100HZ 6250 479#define HAL_MAX_BINS_ALLOWED 28 480 481#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 482#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 483 484#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 485 486/* 487 * Deduce if the host cpu has big- or litt-endian byte order. 488 */ 489static __inline__ int 490isBigEndian(void) 491{ 492 union { 493 int32_t i; 494 char c[4]; 495 } u; 496 u.i = 1; 497 return (u.c[0] == 0); 498} 499 500/* unalligned little endian access */ 501#define LE_READ_2(p) \ 502 ((uint16_t) \ 503 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 504#define LE_READ_4(p) \ 505 ((uint32_t) \ 506 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 507 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 508 509/* 510 * Register manipulation macros that expect bit field defines 511 * to follow the convention that an _S suffix is appended for 512 * a shift count, while the field mask has no suffix. 513 */ 514#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 515#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 516#define OS_REG_RMW(_a, _r, _set, _clr) \ 517 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 518#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 519 OS_REG_WRITE(_a, _r, \ 520 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 521#define OS_REG_SET_BIT(_a, _r, _f) \ 522 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 523#define OS_REG_CLR_BIT(_a, _r, _f) \ 524 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 525#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 526 ((OS_REG_READ(_a, _r) & (_f)) != 0) 527 528/* Analog register writes may require a delay between each one (eg Merlin?) */ 529#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 530 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 531 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 532#define OS_A_REG_WRITE(_a, _r, _v) \ 533 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 534 535/* wait for the register contents to have the specified value */ 536extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 537 uint32_t mask, uint32_t val); 538extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 539 uint32_t mask, uint32_t val, uint32_t timeout); 540 541/* return the first n bits in val reversed */ 542extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 543 544/* printf interfaces */ 545extern void ath_hal_printf(struct ath_hal *, const char*, ...) 546 __printflike(2,3); 547extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 548 __printflike(2, 0); 549extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 550 551/* allocate and free memory */ 552extern void *ath_hal_malloc(size_t); 553extern void ath_hal_free(void *); 554 555/* common debugging interfaces */ 556#ifdef AH_DEBUG 557#include "ah_debug.h" 558extern int ath_hal_debug; /* Global debug flags */ 559 560/* 561 * The typecast is purely because some callers will pass in 562 * AH_NULL directly rather than using a NULL ath_hal pointer. 563 */ 564#define HALDEBUG(_ah, __m, ...) \ 565 do { \ 566 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 567 ath_hal_debug & (__m) || \ 568 ((_ah) != NULL && \ 569 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 570 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 571 } \ 572 } while(0); 573 574extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 575 __printflike(3,4); 576#else 577#define HALDEBUG(_ah, __m, ...) 578#endif /* AH_DEBUG */ 579 580/* 581 * Register logging definitions shared with ardecode. 582 */ 583#include "ah_decode.h" 584 585/* 586 * Common assertion interface. Note: it is a bad idea to generate 587 * an assertion failure for any recoverable event. Instead catch 588 * the violation and, if possible, fix it up or recover from it; either 589 * with an error return value or a diagnostic messages. System software 590 * does not panic unless the situation is hopeless. 591 */ 592#ifdef AH_ASSERT 593extern void ath_hal_assert_failed(const char* filename, 594 int lineno, const char* msg); 595 596#define HALASSERT(_x) do { \ 597 if (!(_x)) { \ 598 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 599 } \ 600} while (0) 601#else 602#define HALASSERT(_x) 603#endif /* AH_ASSERT */ 604 605/* 606 * Regulatory domain support. 607 */ 608 609/* 610 * Return the max allowed antenna gain and apply any regulatory 611 * domain specific changes. 612 */ 613u_int ath_hal_getantennareduction(struct ath_hal *ah, 614 const struct ieee80211_channel *chan, u_int twiceGain); 615 616/* 617 * Return the test group for the specific channel based on 618 * the current regulatory setup. 619 */ 620u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 621 622/* 623 * Map a public channel definition to the corresponding 624 * internal data structure. This implicitly specifies 625 * whether or not the specified channel is ok to use 626 * based on the current regulatory domain constraints. 627 */ 628#ifndef AH_DEBUG 629static OS_INLINE HAL_CHANNEL_INTERNAL * 630ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 631{ 632 HAL_CHANNEL_INTERNAL *cc; 633 634 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 635 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 636 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 637 return cc; 638} 639#else 640/* NB: non-inline version that checks state */ 641HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 642 const struct ieee80211_channel *); 643#endif /* AH_DEBUG */ 644 645/* 646 * Return the h/w frequency for a channel. This may be 647 * different from ic_freq if this is a GSM device that 648 * takes 2.4GHz frequencies and down-converts them. 649 */ 650static OS_INLINE uint16_t 651ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 652{ 653 return ath_hal_checkchannel(ah, c)->channel; 654} 655 656/* 657 * Convert between microseconds and core system clocks. 658 */ 659extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 660extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 661 662/* 663 * Generic get/set capability support. Each chip overrides 664 * this routine to support chip-specific capabilities. 665 */ 666extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 667 HAL_CAPABILITY_TYPE type, uint32_t capability, 668 uint32_t *result); 669extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 670 HAL_CAPABILITY_TYPE type, uint32_t capability, 671 uint32_t setting, HAL_STATUS *status); 672 673/* The diagnostic codes used to be internally defined here -adrian */ 674#include "ah_diagcodes.h" 675 676/* 677 * The AR5416 and later HALs have MAC and baseband hang checking. 678 */ 679typedef struct { 680 uint32_t hang_reg_offset; 681 uint32_t hang_val; 682 uint32_t hang_mask; 683 uint32_t hang_offset; 684} hal_hw_hang_check_t; 685 686typedef struct { 687 uint32_t dma_dbg_3; 688 uint32_t dma_dbg_4; 689 uint32_t dma_dbg_5; 690 uint32_t dma_dbg_6; 691} mac_dbg_regs_t; 692 693typedef enum { 694 dcu_chain_state = 0x1, 695 dcu_complete_state = 0x2, 696 qcu_state = 0x4, 697 qcu_fsp_ok = 0x8, 698 qcu_fsp_state = 0x10, 699 qcu_stitch_state = 0x20, 700 qcu_fetch_state = 0x40, 701 qcu_complete_state = 0x80 702} hal_mac_hangs_t; 703 704typedef struct { 705 int states; 706 uint8_t dcu_chain_state; 707 uint8_t dcu_complete_state; 708 uint8_t qcu_state; 709 uint8_t qcu_fsp_ok; 710 uint8_t qcu_fsp_state; 711 uint8_t qcu_stitch_state; 712 uint8_t qcu_fetch_state; 713 uint8_t qcu_complete_state; 714} hal_mac_hang_check_t; 715 716enum { 717 HAL_BB_HANG_DFS = 0x0001, 718 HAL_BB_HANG_RIFS = 0x0002, 719 HAL_BB_HANG_RX_CLEAR = 0x0004, 720 HAL_BB_HANG_UNKNOWN = 0x0080, 721 722 HAL_MAC_HANG_SIG1 = 0x0100, 723 HAL_MAC_HANG_SIG2 = 0x0200, 724 HAL_MAC_HANG_UNKNOWN = 0x8000, 725 726 HAL_BB_HANGS = HAL_BB_HANG_DFS 727 | HAL_BB_HANG_RIFS 728 | HAL_BB_HANG_RX_CLEAR 729 | HAL_BB_HANG_UNKNOWN, 730 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 731 | HAL_MAC_HANG_SIG2 732 | HAL_MAC_HANG_UNKNOWN, 733}; 734 735/* 736 * Device revision information. 737 */ 738typedef struct { 739 uint16_t ah_devid; /* PCI device ID */ 740 uint16_t ah_subvendorid; /* PCI subvendor ID */ 741 uint32_t ah_macVersion; /* MAC version id */ 742 uint16_t ah_macRev; /* MAC revision */ 743 uint16_t ah_phyRev; /* PHY revision */ 744 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 745 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 746} HAL_REVS; 747 748/* 749 * Argument payload for HAL_DIAG_SETKEY. 750 */ 751typedef struct { 752 HAL_KEYVAL dk_keyval; 753 uint16_t dk_keyix; /* key index */ 754 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 755 int dk_xor; /* XOR key data */ 756} HAL_DIAG_KEYVAL; 757 758/* 759 * Argument payload for HAL_DIAG_EEWRITE. 760 */ 761typedef struct { 762 uint16_t ee_off; /* eeprom offset */ 763 uint16_t ee_data; /* write data */ 764} HAL_DIAG_EEVAL; 765 766 767typedef struct { 768 u_int offset; /* reg offset */ 769 uint32_t val; /* reg value */ 770} HAL_DIAG_REGVAL; 771 772/* 773 * 11n compatibility tweaks. 774 */ 775#define HAL_DIAG_11N_SERVICES 0x00000003 776#define HAL_DIAG_11N_SERVICES_S 0 777#define HAL_DIAG_11N_TXSTOMP 0x0000000c 778#define HAL_DIAG_11N_TXSTOMP_S 2 779 780typedef struct { 781 int maxNoiseImmunityLevel; /* [0..4] */ 782 int totalSizeDesired[5]; 783 int coarseHigh[5]; 784 int coarseLow[5]; 785 int firpwr[5]; 786 787 int maxSpurImmunityLevel; /* [0..7] */ 788 int cycPwrThr1[8]; 789 790 int maxFirstepLevel; /* [0..2] */ 791 int firstep[3]; 792 793 uint32_t ofdmTrigHigh; 794 uint32_t ofdmTrigLow; 795 int32_t cckTrigHigh; 796 int32_t cckTrigLow; 797 int32_t rssiThrLow; 798 int32_t rssiThrHigh; 799 800 int period; /* update listen period */ 801} HAL_ANI_PARAMS; 802 803extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 804 const void *args, uint32_t argsize, 805 void **result, uint32_t *resultsize); 806 807/* 808 * Setup a h/w rate table for use. 809 */ 810extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 811 812/* 813 * Common routine for implementing getChanNoise api. 814 */ 815int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 816 817/* 818 * Initialization support. 819 */ 820typedef struct { 821 const uint32_t *data; 822 int rows, cols; 823} HAL_INI_ARRAY; 824 825#define HAL_INI_INIT(_ia, _data, _cols) do { \ 826 (_ia)->data = (const uint32_t *)(_data); \ 827 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 828 (_ia)->cols = (_cols); \ 829} while (0) 830#define HAL_INI_VAL(_ia, _r, _c) \ 831 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 832 833/* 834 * OS_DELAY() does a PIO READ on the PCI bus which allows 835 * other cards' DMA reads to complete in the middle of our reset. 836 */ 837#define DMA_YIELD(x) do { \ 838 if ((++(x) % 64) == 0) \ 839 OS_DELAY(1); \ 840} while (0) 841 842#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 843 int r; \ 844 for (r = 0; r < N(regArray); r++) { \ 845 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 846 DMA_YIELD(regWr); \ 847 } \ 848} while (0) 849 850#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 851 int r; \ 852 for (r = 0; r < N(regArray); r++) { \ 853 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 854 DMA_YIELD(regWr); \ 855 } \ 856} while (0) 857 858extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 859 int col, int regWr); 860extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 861 int col); 862extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 863 const uint32_t data[], int regWr); 864 865#define CCK_SIFS_TIME 10 866#define CCK_PREAMBLE_BITS 144 867#define CCK_PLCP_BITS 48 868 869#define OFDM_SIFS_TIME 16 870#define OFDM_PREAMBLE_TIME 20 871#define OFDM_PLCP_BITS 22 872#define OFDM_SYMBOL_TIME 4 873 874#define OFDM_HALF_SIFS_TIME 32 875#define OFDM_HALF_PREAMBLE_TIME 40 876#define OFDM_HALF_PLCP_BITS 22 877#define OFDM_HALF_SYMBOL_TIME 8 878 879#define OFDM_QUARTER_SIFS_TIME 64 880#define OFDM_QUARTER_PREAMBLE_TIME 80 881#define OFDM_QUARTER_PLCP_BITS 22 882#define OFDM_QUARTER_SYMBOL_TIME 16 883 884#define TURBO_SIFS_TIME 8 885#define TURBO_PREAMBLE_TIME 14 886#define TURBO_PLCP_BITS 22 887#define TURBO_SYMBOL_TIME 4 888 889#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 890 891/* Generic EEPROM board value functions */ 892extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 893 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 894extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 895 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 896 uint8_t *pRetVpdList); 897extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 898 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 899 900/* Whether 5ghz fast clock is needed */ 901/* 902 * The chipset (Merlin, AR9300/later) should set the capability flag below; 903 * this flag simply says that the hardware can do it, not that the EEPROM 904 * says it can. 905 * 906 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 907 * if the relevant eeprom flag is set. 908 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 909 * by default. 910 */ 911#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 912 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 913 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 914 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 915 916 917#endif /* _ATH_AH_INTERAL_H_ */ 918