ah_internal.h revision 239800
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 239800 2012-08-29 03:50:59Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Enable/disable strong signal fast diversity 83 */ 84#define HAL_CAP_STRONG_DIV 2 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 94 HAL_STATUS *error); 95}; 96#ifndef AH_CHIP 97#define AH_CHIP(_name, _probe, _attach) \ 98static struct ath_hal_chip _name##_chip = { \ 99 .name = #_name, \ 100 .probe = _probe, \ 101 .attach = _attach \ 102}; \ 103OS_DATA_SET(ah_chips, _name##_chip) 104#endif 105 106/* 107 * Each RF backend registers to offer support; this is mostly 108 * used by multi-chip 5212 solutions. Single-chip solutions 109 * have a fixed idea about which RF to use. 110 */ 111struct ath_hal_rf { 112 const char *name; 113 HAL_BOOL (*probe)(struct ath_hal *ah); 114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 115}; 116#ifndef AH_RF 117#define AH_RF(_name, _probe, _attach) \ 118static struct ath_hal_rf _name##_rf = { \ 119 .name = __STRING(_name), \ 120 .probe = _probe, \ 121 .attach = _attach \ 122}; \ 123OS_DATA_SET(ah_rfs, _name##_rf) 124#endif 125 126struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 127 128/* 129 * Maximum number of internal channels. Entries are per unique 130 * frequency so this might be need to be increased to handle all 131 * usage cases; typically no more than 32 are really needed but 132 * dynamically allocating the data structures is a bit painful 133 * right now. 134 */ 135#ifndef AH_MAXCHAN 136#define AH_MAXCHAN 96 137#endif 138 139/* 140 * Internal per-channel state. These are found 141 * using ic_devdata in the ieee80211_channel. 142 */ 143typedef struct { 144 uint16_t channel; /* h/w frequency, NB: may be mapped */ 145 uint8_t privFlags; 146#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 147#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 148#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 149#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 150 uint8_t calValid; /* bitmask of cal types */ 151 int8_t iCoff; 152 int8_t qCoff; 153 int16_t rawNoiseFloor; 154 int16_t noiseFloorAdjust; 155#ifdef AH_SUPPORT_AR5416 156 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 157 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 158#endif /* AH_SUPPORT_AR5416 */ 159 uint16_t mainSpur; /* cached spur value for this channel */ 160} HAL_CHANNEL_INTERNAL; 161 162/* channel requires noise floor check */ 163#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 164 165/* all full-width channels */ 166#define IEEE80211_CHAN_ALLFULL \ 167 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 168#define IEEE80211_CHAN_ALLTURBOFULL \ 169 (IEEE80211_CHAN_ALLTURBO - \ 170 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 171 172typedef struct { 173 uint32_t halChanSpreadSupport : 1, 174 halSleepAfterBeaconBroken : 1, 175 halCompressSupport : 1, 176 halBurstSupport : 1, 177 halFastFramesSupport : 1, 178 halChapTuningSupport : 1, 179 halTurboGSupport : 1, 180 halTurboPrimeSupport : 1, 181 halMicAesCcmSupport : 1, 182 halMicCkipSupport : 1, 183 halMicTkipSupport : 1, 184 halTkipMicTxRxKeySupport : 1, 185 halCipherAesCcmSupport : 1, 186 halCipherCkipSupport : 1, 187 halCipherTkipSupport : 1, 188 halPSPollBroken : 1, 189 halVEOLSupport : 1, 190 halBssIdMaskSupport : 1, 191 halMcastKeySrchSupport : 1, 192 halTsfAddSupport : 1, 193 halChanHalfRate : 1, 194 halChanQuarterRate : 1, 195 halHTSupport : 1, 196 halHTSGI20Support : 1, 197 halRfSilentSupport : 1, 198 halHwPhyCounterSupport : 1, 199 halWowSupport : 1, 200 halWowMatchPatternExact : 1, 201 halAutoSleepSupport : 1, 202 halFastCCSupport : 1, 203 halBtCoexSupport : 1; 204 uint32_t halRxStbcSupport : 1, 205 halTxStbcSupport : 1, 206 halGTTSupport : 1, 207 halCSTSupport : 1, 208 halRifsRxSupport : 1, 209 halRifsTxSupport : 1, 210 hal4AddrAggrSupport : 1, 211 halExtChanDfsSupport : 1, 212 halUseCombinedRadarRssi : 1, 213 halForcePpmSupport : 1, 214 halEnhancedPmSupport : 1, 215 halEnhancedDfsSupport : 1, 216 halMbssidAggrSupport : 1, 217 halBssidMatchSupport : 1, 218 hal4kbSplitTransSupport : 1, 219 halHasRxSelfLinkedTail : 1, 220 halSupportsFastClock5GHz : 1, 221 halHasLongRxDescTsf : 1, 222 halHasBBReadWar : 1, 223 halSerialiseRegWar : 1, 224 halMciSupport : 1, 225 halRxTxAbortSupport : 1, 226 halPaprdEnabled : 1, 227 halHasUapsdSupport : 1, 228 halWpsPushButtonSupport : 1, 229 halBtCoexApsmWar : 1, 230 halGenTimerSupport : 1, 231 halLDPCSupport : 1, 232 halHwBeaconProcSupport : 1, 233 halEnhancedDmaSupport : 1; 234 uint32_t halIsrRacSupport : 1, 235 halApmEnable : 1, 236 halIntrMitigation : 1, 237 hal49GhzSupport : 1; 238 239 uint32_t halWirelessModes; 240 uint16_t halTotalQueues; 241 uint16_t halKeyCacheSize; 242 uint16_t halLow5GhzChan, halHigh5GhzChan; 243 uint16_t halLow2GhzChan, halHigh2GhzChan; 244 int halTstampPrecision; 245 int halRtsAggrLimit; 246 uint8_t halTxChainMask; 247 uint8_t halRxChainMask; 248 uint8_t halNumGpioPins; 249 uint8_t halNumAntCfg2GHz; 250 uint8_t halNumAntCfg5GHz; 251 uint32_t halIntrMask; 252 uint8_t halTxStreams; 253 uint8_t halRxStreams; 254 HAL_MFP_OPT_T halMfpSupport; 255 int halNumTxMaps; 256 int halTxDescLen; 257 int halTxStatusLen; 258 int halRxStatusLen; 259 int halRxHpFifoDepth; 260 int halRxLpFifoDepth; 261 int halNumMRRetries; 262} HAL_CAPABILITIES; 263 264struct regDomain; 265 266/* 267 * Definitions for ah_flags in ath_hal_private 268 */ 269#define AH_USE_EEPROM 0x1 270#define AH_IS_HB63 0x2 271 272/* 273 * The ``private area'' follows immediately after the ``public area'' 274 * in the data structure returned by ath_hal_attach. Private data are 275 * used by device-independent code such as the regulatory domain support. 276 * In general, code within the HAL should never depend on data in the 277 * public area. Instead any public data needed internally should be 278 * shadowed here. 279 * 280 * When declaring a device-specific ath_hal data structure this structure 281 * is assumed to at the front; e.g. 282 * 283 * struct ath_hal_5212 { 284 * struct ath_hal_private ah_priv; 285 * ... 286 * }; 287 * 288 * It might be better to manage the method pointers in this structure 289 * using an indirect pointer to a read-only data structure but this would 290 * disallow class-style method overriding. 291 */ 292struct ath_hal_private { 293 struct ath_hal h; /* public area */ 294 295 /* NB: all methods go first to simplify initialization */ 296 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 297 uint16_t channelFlags, 298 uint16_t *lowChannel, uint16_t *highChannel); 299 u_int (*ah_getWirelessModes)(struct ath_hal*); 300 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 301 uint16_t *data); 302 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 303 uint16_t data); 304 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 305 struct ieee80211_channel *); 306 int16_t (*ah_getNfAdjust)(struct ath_hal *, 307 const HAL_CHANNEL_INTERNAL*); 308 void (*ah_getNoiseFloor)(struct ath_hal *, 309 int16_t nfarray[]); 310 311 void *ah_eeprom; /* opaque EEPROM state */ 312 uint16_t ah_eeversion; /* EEPROM version */ 313 void (*ah_eepromDetach)(struct ath_hal *); 314 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 315 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 316 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 317 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 318 const void *args, uint32_t argsize, 319 void **result, uint32_t *resultsize); 320 321 /* 322 * Device revision information. 323 */ 324 uint16_t ah_devid; /* PCI device ID */ 325 uint16_t ah_subvendorid; /* PCI subvendor ID */ 326 uint32_t ah_macVersion; /* MAC version id */ 327 uint16_t ah_macRev; /* MAC revision */ 328 uint16_t ah_phyRev; /* PHY revision */ 329 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 330 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 331 uint32_t ah_flags; /* misc flags */ 332 uint8_t ah_ispcie; /* PCIE, special treatment */ 333 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 334 335 HAL_OPMODE ah_opmode; /* operating mode from reset */ 336 const struct ieee80211_channel *ah_curchan;/* operating channel */ 337 HAL_CAPABILITIES ah_caps; /* device capabilities */ 338 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 339 int16_t ah_powerLimit; /* tx power cap */ 340 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 341 u_int ah_tpScale; /* tx power scale factor */ 342 uint32_t ah_11nCompat; /* 11n compat controls */ 343 344 /* 345 * State for regulatory domain handling. 346 */ 347 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 348 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 349 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 350 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 351 u_int ah_nchan; /* valid items in ah_channels */ 352 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 353 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 354 355 uint8_t ah_coverageClass; /* coverage class */ 356 /* 357 * RF Silent handling; setup according to the EEPROM. 358 */ 359 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 360 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 361 /* 362 * Diagnostic support for discriminating HIUERR reports. 363 */ 364 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 365 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 366}; 367 368#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 369 370#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 371 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 372#define ath_hal_getWirelessModes(_ah) \ 373 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 374#define ath_hal_eepromRead(_ah, _off, _data) \ 375 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 376#define ath_hal_eepromWrite(_ah, _off, _data) \ 377 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 378#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 379 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 380#define ath_hal_gpioCfgInput(_ah, _gpio) \ 381 (_ah)->ah_gpioCfgInput(_ah, _gpio) 382#define ath_hal_gpioGet(_ah, _gpio) \ 383 (_ah)->ah_gpioGet(_ah, _gpio) 384#define ath_hal_gpioSet(_ah, _gpio, _val) \ 385 (_ah)->ah_gpioSet(_ah, _gpio, _val) 386#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 387 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 388#define ath_hal_getpowerlimits(_ah, _chan) \ 389 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 390#define ath_hal_getNfAdjust(_ah, _c) \ 391 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 392#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 393 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 394#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 395 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 396#define ath_hal_disablePCIE(_ah) \ 397 (_ah)->ah_disablePCIE(_ah) 398#define ath_hal_setInterrupts(_ah, _mask) \ 399 (_ah)->ah_setInterrupts(_ah, _mask) 400 401#define ath_hal_isrfkillenabled(_ah) \ 402 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK) 403#define ath_hal_enable_rfkill(_ah, _v) \ 404 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL) 405#define ath_hal_hasrfkill_int(_ah) \ 406 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK) 407 408#define ath_hal_eepromDetach(_ah) do { \ 409 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 410 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 411} while (0) 412#define ath_hal_eepromGet(_ah, _param, _val) \ 413 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 414#define ath_hal_eepromSet(_ah, _param, _val) \ 415 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 416#define ath_hal_eepromGetFlag(_ah, _param) \ 417 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 418#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 419 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 420#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 421 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 422 423#ifndef _NET_IF_IEEE80211_H_ 424/* 425 * Stuff that would naturally come from _ieee80211.h 426 */ 427#define IEEE80211_ADDR_LEN 6 428 429#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 430#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 431#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 432 433#define IEEE80211_CRC_LEN 4 434 435#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 436 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 437#endif /* _NET_IF_IEEE80211_H_ */ 438 439#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 440 441#define INIT_AIFS 2 442#define INIT_CWMIN 15 443#define INIT_CWMIN_11B 31 444#define INIT_CWMAX 1023 445#define INIT_SH_RETRY 10 446#define INIT_LG_RETRY 10 447#define INIT_SSH_RETRY 32 448#define INIT_SLG_RETRY 32 449 450typedef struct { 451 uint32_t tqi_ver; /* HAL TXQ verson */ 452 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 453 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 454 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 455 uint32_t tqi_priority; 456 uint32_t tqi_aifs; /* aifs */ 457 uint32_t tqi_cwmin; /* cwMin */ 458 uint32_t tqi_cwmax; /* cwMax */ 459 uint16_t tqi_shretry; /* frame short retry limit */ 460 uint16_t tqi_lgretry; /* frame long retry limit */ 461 uint32_t tqi_cbrPeriod; 462 uint32_t tqi_cbrOverflowLimit; 463 uint32_t tqi_burstTime; 464 uint32_t tqi_readyTime; 465 uint32_t tqi_physCompBuf; 466 uint32_t tqi_intFlags; /* flags for internal use */ 467} HAL_TX_QUEUE_INFO; 468 469extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 470 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 471extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 472 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 473 474#define HAL_SPUR_VAL_MASK 0x3FFF 475#define HAL_SPUR_CHAN_WIDTH 87 476#define HAL_BIN_WIDTH_BASE_100HZ 3125 477#define HAL_BIN_WIDTH_TURBO_100HZ 6250 478#define HAL_MAX_BINS_ALLOWED 28 479 480#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 481#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 482 483#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 484 485/* 486 * Deduce if the host cpu has big- or litt-endian byte order. 487 */ 488static __inline__ int 489isBigEndian(void) 490{ 491 union { 492 int32_t i; 493 char c[4]; 494 } u; 495 u.i = 1; 496 return (u.c[0] == 0); 497} 498 499/* unalligned little endian access */ 500#define LE_READ_2(p) \ 501 ((uint16_t) \ 502 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 503#define LE_READ_4(p) \ 504 ((uint32_t) \ 505 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 506 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 507 508/* 509 * Register manipulation macros that expect bit field defines 510 * to follow the convention that an _S suffix is appended for 511 * a shift count, while the field mask has no suffix. 512 */ 513#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 514#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 515#define OS_REG_RMW(_a, _r, _set, _clr) \ 516 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 517#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 518 OS_REG_WRITE(_a, _r, \ 519 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 520#define OS_REG_SET_BIT(_a, _r, _f) \ 521 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 522#define OS_REG_CLR_BIT(_a, _r, _f) \ 523 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 524#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 525 ((OS_REG_READ(_a, _r) & (_f)) != 0) 526 527/* Analog register writes may require a delay between each one (eg Merlin?) */ 528#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 529 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 530 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 531#define OS_A_REG_WRITE(_a, _r, _v) \ 532 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 533 534/* wait for the register contents to have the specified value */ 535extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 536 uint32_t mask, uint32_t val); 537extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 538 uint32_t mask, uint32_t val, uint32_t timeout); 539 540/* return the first n bits in val reversed */ 541extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 542 543/* printf interfaces */ 544extern void ath_hal_printf(struct ath_hal *, const char*, ...) 545 __printflike(2,3); 546extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 547 __printflike(2, 0); 548extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 549 550/* allocate and free memory */ 551extern void *ath_hal_malloc(size_t); 552extern void ath_hal_free(void *); 553 554/* common debugging interfaces */ 555#ifdef AH_DEBUG 556#include "ah_debug.h" 557extern int ath_hal_debug; /* Global debug flags */ 558 559/* 560 * The typecast is purely because some callers will pass in 561 * AH_NULL directly rather than using a NULL ath_hal pointer. 562 */ 563#define HALDEBUG(_ah, __m, ...) \ 564 do { \ 565 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 566 ath_hal_debug & (__m) || \ 567 ((_ah) != NULL && \ 568 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 569 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 570 } \ 571 } while(0); 572 573extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 574 __printflike(3,4); 575#else 576#define HALDEBUG(_ah, __m, ...) 577#endif /* AH_DEBUG */ 578 579/* 580 * Register logging definitions shared with ardecode. 581 */ 582#include "ah_decode.h" 583 584/* 585 * Common assertion interface. Note: it is a bad idea to generate 586 * an assertion failure for any recoverable event. Instead catch 587 * the violation and, if possible, fix it up or recover from it; either 588 * with an error return value or a diagnostic messages. System software 589 * does not panic unless the situation is hopeless. 590 */ 591#ifdef AH_ASSERT 592extern void ath_hal_assert_failed(const char* filename, 593 int lineno, const char* msg); 594 595#define HALASSERT(_x) do { \ 596 if (!(_x)) { \ 597 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 598 } \ 599} while (0) 600#else 601#define HALASSERT(_x) 602#endif /* AH_ASSERT */ 603 604/* 605 * Regulatory domain support. 606 */ 607 608/* 609 * Return the max allowed antenna gain and apply any regulatory 610 * domain specific changes. 611 */ 612u_int ath_hal_getantennareduction(struct ath_hal *ah, 613 const struct ieee80211_channel *chan, u_int twiceGain); 614 615/* 616 * Return the test group for the specific channel based on 617 * the current regulatory setup. 618 */ 619u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 620 621/* 622 * Map a public channel definition to the corresponding 623 * internal data structure. This implicitly specifies 624 * whether or not the specified channel is ok to use 625 * based on the current regulatory domain constraints. 626 */ 627#ifndef AH_DEBUG 628static OS_INLINE HAL_CHANNEL_INTERNAL * 629ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 630{ 631 HAL_CHANNEL_INTERNAL *cc; 632 633 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 634 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 635 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 636 return cc; 637} 638#else 639/* NB: non-inline version that checks state */ 640HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 641 const struct ieee80211_channel *); 642#endif /* AH_DEBUG */ 643 644/* 645 * Return the h/w frequency for a channel. This may be 646 * different from ic_freq if this is a GSM device that 647 * takes 2.4GHz frequencies and down-converts them. 648 */ 649static OS_INLINE uint16_t 650ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 651{ 652 return ath_hal_checkchannel(ah, c)->channel; 653} 654 655/* 656 * Convert between microseconds and core system clocks. 657 */ 658extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 659extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 660 661/* 662 * Generic get/set capability support. Each chip overrides 663 * this routine to support chip-specific capabilities. 664 */ 665extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 666 HAL_CAPABILITY_TYPE type, uint32_t capability, 667 uint32_t *result); 668extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 669 HAL_CAPABILITY_TYPE type, uint32_t capability, 670 uint32_t setting, HAL_STATUS *status); 671 672/* The diagnostic codes used to be internally defined here -adrian */ 673#include "ah_diagcodes.h" 674 675/* 676 * The AR5416 and later HALs have MAC and baseband hang checking. 677 */ 678typedef struct { 679 uint32_t hang_reg_offset; 680 uint32_t hang_val; 681 uint32_t hang_mask; 682 uint32_t hang_offset; 683} hal_hw_hang_check_t; 684 685typedef struct { 686 uint32_t dma_dbg_3; 687 uint32_t dma_dbg_4; 688 uint32_t dma_dbg_5; 689 uint32_t dma_dbg_6; 690} mac_dbg_regs_t; 691 692typedef enum { 693 dcu_chain_state = 0x1, 694 dcu_complete_state = 0x2, 695 qcu_state = 0x4, 696 qcu_fsp_ok = 0x8, 697 qcu_fsp_state = 0x10, 698 qcu_stitch_state = 0x20, 699 qcu_fetch_state = 0x40, 700 qcu_complete_state = 0x80 701} hal_mac_hangs_t; 702 703typedef struct { 704 int states; 705 uint8_t dcu_chain_state; 706 uint8_t dcu_complete_state; 707 uint8_t qcu_state; 708 uint8_t qcu_fsp_ok; 709 uint8_t qcu_fsp_state; 710 uint8_t qcu_stitch_state; 711 uint8_t qcu_fetch_state; 712 uint8_t qcu_complete_state; 713} hal_mac_hang_check_t; 714 715enum { 716 HAL_BB_HANG_DFS = 0x0001, 717 HAL_BB_HANG_RIFS = 0x0002, 718 HAL_BB_HANG_RX_CLEAR = 0x0004, 719 HAL_BB_HANG_UNKNOWN = 0x0080, 720 721 HAL_MAC_HANG_SIG1 = 0x0100, 722 HAL_MAC_HANG_SIG2 = 0x0200, 723 HAL_MAC_HANG_UNKNOWN = 0x8000, 724 725 HAL_BB_HANGS = HAL_BB_HANG_DFS 726 | HAL_BB_HANG_RIFS 727 | HAL_BB_HANG_RX_CLEAR 728 | HAL_BB_HANG_UNKNOWN, 729 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 730 | HAL_MAC_HANG_SIG2 731 | HAL_MAC_HANG_UNKNOWN, 732}; 733 734/* 735 * Device revision information. 736 */ 737typedef struct { 738 uint16_t ah_devid; /* PCI device ID */ 739 uint16_t ah_subvendorid; /* PCI subvendor ID */ 740 uint32_t ah_macVersion; /* MAC version id */ 741 uint16_t ah_macRev; /* MAC revision */ 742 uint16_t ah_phyRev; /* PHY revision */ 743 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 744 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 745} HAL_REVS; 746 747/* 748 * Argument payload for HAL_DIAG_SETKEY. 749 */ 750typedef struct { 751 HAL_KEYVAL dk_keyval; 752 uint16_t dk_keyix; /* key index */ 753 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 754 int dk_xor; /* XOR key data */ 755} HAL_DIAG_KEYVAL; 756 757/* 758 * Argument payload for HAL_DIAG_EEWRITE. 759 */ 760typedef struct { 761 uint16_t ee_off; /* eeprom offset */ 762 uint16_t ee_data; /* write data */ 763} HAL_DIAG_EEVAL; 764 765 766typedef struct { 767 u_int offset; /* reg offset */ 768 uint32_t val; /* reg value */ 769} HAL_DIAG_REGVAL; 770 771/* 772 * 11n compatibility tweaks. 773 */ 774#define HAL_DIAG_11N_SERVICES 0x00000003 775#define HAL_DIAG_11N_SERVICES_S 0 776#define HAL_DIAG_11N_TXSTOMP 0x0000000c 777#define HAL_DIAG_11N_TXSTOMP_S 2 778 779typedef struct { 780 int maxNoiseImmunityLevel; /* [0..4] */ 781 int totalSizeDesired[5]; 782 int coarseHigh[5]; 783 int coarseLow[5]; 784 int firpwr[5]; 785 786 int maxSpurImmunityLevel; /* [0..7] */ 787 int cycPwrThr1[8]; 788 789 int maxFirstepLevel; /* [0..2] */ 790 int firstep[3]; 791 792 uint32_t ofdmTrigHigh; 793 uint32_t ofdmTrigLow; 794 int32_t cckTrigHigh; 795 int32_t cckTrigLow; 796 int32_t rssiThrLow; 797 int32_t rssiThrHigh; 798 799 int period; /* update listen period */ 800} HAL_ANI_PARAMS; 801 802extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 803 const void *args, uint32_t argsize, 804 void **result, uint32_t *resultsize); 805 806/* 807 * Setup a h/w rate table for use. 808 */ 809extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 810 811/* 812 * Common routine for implementing getChanNoise api. 813 */ 814int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 815 816/* 817 * Initialization support. 818 */ 819typedef struct { 820 const uint32_t *data; 821 int rows, cols; 822} HAL_INI_ARRAY; 823 824#define HAL_INI_INIT(_ia, _data, _cols) do { \ 825 (_ia)->data = (const uint32_t *)(_data); \ 826 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 827 (_ia)->cols = (_cols); \ 828} while (0) 829#define HAL_INI_VAL(_ia, _r, _c) \ 830 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 831 832/* 833 * OS_DELAY() does a PIO READ on the PCI bus which allows 834 * other cards' DMA reads to complete in the middle of our reset. 835 */ 836#define DMA_YIELD(x) do { \ 837 if ((++(x) % 64) == 0) \ 838 OS_DELAY(1); \ 839} while (0) 840 841#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 842 int r; \ 843 for (r = 0; r < N(regArray); r++) { \ 844 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 845 DMA_YIELD(regWr); \ 846 } \ 847} while (0) 848 849#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 850 int r; \ 851 for (r = 0; r < N(regArray); r++) { \ 852 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 853 DMA_YIELD(regWr); \ 854 } \ 855} while (0) 856 857extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 858 int col, int regWr); 859extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 860 int col); 861extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 862 const uint32_t data[], int regWr); 863 864#define CCK_SIFS_TIME 10 865#define CCK_PREAMBLE_BITS 144 866#define CCK_PLCP_BITS 48 867 868#define OFDM_SIFS_TIME 16 869#define OFDM_PREAMBLE_TIME 20 870#define OFDM_PLCP_BITS 22 871#define OFDM_SYMBOL_TIME 4 872 873#define OFDM_HALF_SIFS_TIME 32 874#define OFDM_HALF_PREAMBLE_TIME 40 875#define OFDM_HALF_PLCP_BITS 22 876#define OFDM_HALF_SYMBOL_TIME 8 877 878#define OFDM_QUARTER_SIFS_TIME 64 879#define OFDM_QUARTER_PREAMBLE_TIME 80 880#define OFDM_QUARTER_PLCP_BITS 22 881#define OFDM_QUARTER_SYMBOL_TIME 16 882 883#define TURBO_SIFS_TIME 8 884#define TURBO_PREAMBLE_TIME 14 885#define TURBO_PLCP_BITS 22 886#define TURBO_SYMBOL_TIME 4 887 888#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 889 890/* Generic EEPROM board value functions */ 891extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 892 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 893extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 894 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 895 uint8_t *pRetVpdList); 896extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 897 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 898 899/* Whether 5ghz fast clock is needed */ 900/* 901 * The chipset (Merlin, AR9300/later) should set the capability flag below; 902 * this flag simply says that the hardware can do it, not that the EEPROM 903 * says it can. 904 * 905 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 906 * if the relevant eeprom flag is set. 907 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 908 * by default. 909 */ 910#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 911 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 912 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 913 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 914 915 916#endif /* _ATH_AH_INTERAL_H_ */ 917