ah_internal.h revision 239628
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 239628 2012-08-24 00:15:26Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Each chip or class of chips registers to offer support. 83 */ 84struct ath_hal_chip { 85 const char *name; 86 const char *(*probe)(uint16_t vendorid, uint16_t devid); 87 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 88 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 89 HAL_STATUS *error); 90}; 91#ifndef AH_CHIP 92#define AH_CHIP(_name, _probe, _attach) \ 93static struct ath_hal_chip _name##_chip = { \ 94 .name = #_name, \ 95 .probe = _probe, \ 96 .attach = _attach \ 97}; \ 98OS_DATA_SET(ah_chips, _name##_chip) 99#endif 100 101/* 102 * Each RF backend registers to offer support; this is mostly 103 * used by multi-chip 5212 solutions. Single-chip solutions 104 * have a fixed idea about which RF to use. 105 */ 106struct ath_hal_rf { 107 const char *name; 108 HAL_BOOL (*probe)(struct ath_hal *ah); 109 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 110}; 111#ifndef AH_RF 112#define AH_RF(_name, _probe, _attach) \ 113static struct ath_hal_rf _name##_rf = { \ 114 .name = __STRING(_name), \ 115 .probe = _probe, \ 116 .attach = _attach \ 117}; \ 118OS_DATA_SET(ah_rfs, _name##_rf) 119#endif 120 121struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 122 123/* 124 * Maximum number of internal channels. Entries are per unique 125 * frequency so this might be need to be increased to handle all 126 * usage cases; typically no more than 32 are really needed but 127 * dynamically allocating the data structures is a bit painful 128 * right now. 129 */ 130#ifndef AH_MAXCHAN 131#define AH_MAXCHAN 96 132#endif 133 134/* 135 * Internal per-channel state. These are found 136 * using ic_devdata in the ieee80211_channel. 137 */ 138typedef struct { 139 uint16_t channel; /* h/w frequency, NB: may be mapped */ 140 uint8_t privFlags; 141#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 142#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 143#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 144#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 145 uint8_t calValid; /* bitmask of cal types */ 146 int8_t iCoff; 147 int8_t qCoff; 148 int16_t rawNoiseFloor; 149 int16_t noiseFloorAdjust; 150#ifdef AH_SUPPORT_AR5416 151 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 152 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 153#endif /* AH_SUPPORT_AR5416 */ 154 uint16_t mainSpur; /* cached spur value for this channel */ 155} HAL_CHANNEL_INTERNAL; 156 157/* channel requires noise floor check */ 158#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 159 160/* all full-width channels */ 161#define IEEE80211_CHAN_ALLFULL \ 162 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 163#define IEEE80211_CHAN_ALLTURBOFULL \ 164 (IEEE80211_CHAN_ALLTURBO - \ 165 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 166 167typedef struct { 168 uint32_t halChanSpreadSupport : 1, 169 halSleepAfterBeaconBroken : 1, 170 halCompressSupport : 1, 171 halBurstSupport : 1, 172 halFastFramesSupport : 1, 173 halChapTuningSupport : 1, 174 halTurboGSupport : 1, 175 halTurboPrimeSupport : 1, 176 halMicAesCcmSupport : 1, 177 halMicCkipSupport : 1, 178 halMicTkipSupport : 1, 179 halTkipMicTxRxKeySupport : 1, 180 halCipherAesCcmSupport : 1, 181 halCipherCkipSupport : 1, 182 halCipherTkipSupport : 1, 183 halPSPollBroken : 1, 184 halVEOLSupport : 1, 185 halBssIdMaskSupport : 1, 186 halMcastKeySrchSupport : 1, 187 halTsfAddSupport : 1, 188 halChanHalfRate : 1, 189 halChanQuarterRate : 1, 190 halHTSupport : 1, 191 halHTSGI20Support : 1, 192 halRfSilentSupport : 1, 193 halHwPhyCounterSupport : 1, 194 halWowSupport : 1, 195 halWowMatchPatternExact : 1, 196 halAutoSleepSupport : 1, 197 halFastCCSupport : 1, 198 halBtCoexSupport : 1; 199 uint32_t halRxStbcSupport : 1, 200 halTxStbcSupport : 1, 201 halGTTSupport : 1, 202 halCSTSupport : 1, 203 halRifsRxSupport : 1, 204 halRifsTxSupport : 1, 205 hal4AddrAggrSupport : 1, 206 halExtChanDfsSupport : 1, 207 halUseCombinedRadarRssi : 1, 208 halForcePpmSupport : 1, 209 halEnhancedPmSupport : 1, 210 halEnhancedDfsSupport : 1, 211 halMbssidAggrSupport : 1, 212 halBssidMatchSupport : 1, 213 hal4kbSplitTransSupport : 1, 214 halHasRxSelfLinkedTail : 1, 215 halSupportsFastClock5GHz : 1, 216 halHasLongRxDescTsf : 1, 217 halHasBBReadWar : 1, 218 halSerialiseRegWar : 1, 219 halMciSupport : 1, 220 halRxTxAbortSupport : 1, 221 halPaprdEnabled : 1, 222 halHasUapsdSupport : 1, 223 halWpsPushButtonSupport : 1, 224 halBtCoexApsmWar : 1, 225 halGenTimerSupport : 1, 226 halLDPCSupport : 1, 227 halHwBeaconProcSupport : 1, 228 halEnhancedDmaSupport : 1; 229 uint32_t halIsrRacSupport : 1, 230 halApmEnable : 1, 231 halIntrMitigation : 1, 232 hal49GhzSupport : 1; 233 234 uint32_t halWirelessModes; 235 uint16_t halTotalQueues; 236 uint16_t halKeyCacheSize; 237 uint16_t halLow5GhzChan, halHigh5GhzChan; 238 uint16_t halLow2GhzChan, halHigh2GhzChan; 239 int halTstampPrecision; 240 int halRtsAggrLimit; 241 uint8_t halTxChainMask; 242 uint8_t halRxChainMask; 243 uint8_t halNumGpioPins; 244 uint8_t halNumAntCfg2GHz; 245 uint8_t halNumAntCfg5GHz; 246 uint32_t halIntrMask; 247 uint8_t halTxStreams; 248 uint8_t halRxStreams; 249 HAL_MFP_OPT_T halMfpSupport; 250 int halNumTxMaps; 251 int halTxDescLen; 252 int halTxStatusLen; 253 int halRxStatusLen; 254 int halRxHpFifoDepth; 255 int halRxLpFifoDepth; 256 int halNumMRRetries; 257} HAL_CAPABILITIES; 258 259struct regDomain; 260 261/* 262 * Definitions for ah_flags in ath_hal_private 263 */ 264#define AH_USE_EEPROM 0x1 265#define AH_IS_HB63 0x2 266 267/* 268 * The ``private area'' follows immediately after the ``public area'' 269 * in the data structure returned by ath_hal_attach. Private data are 270 * used by device-independent code such as the regulatory domain support. 271 * In general, code within the HAL should never depend on data in the 272 * public area. Instead any public data needed internally should be 273 * shadowed here. 274 * 275 * When declaring a device-specific ath_hal data structure this structure 276 * is assumed to at the front; e.g. 277 * 278 * struct ath_hal_5212 { 279 * struct ath_hal_private ah_priv; 280 * ... 281 * }; 282 * 283 * It might be better to manage the method pointers in this structure 284 * using an indirect pointer to a read-only data structure but this would 285 * disallow class-style method overriding. 286 */ 287struct ath_hal_private { 288 struct ath_hal h; /* public area */ 289 290 /* NB: all methods go first to simplify initialization */ 291 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 292 uint16_t channelFlags, 293 uint16_t *lowChannel, uint16_t *highChannel); 294 u_int (*ah_getWirelessModes)(struct ath_hal*); 295 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 296 uint16_t *data); 297 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 298 uint16_t data); 299 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 300 struct ieee80211_channel *); 301 int16_t (*ah_getNfAdjust)(struct ath_hal *, 302 const HAL_CHANNEL_INTERNAL*); 303 void (*ah_getNoiseFloor)(struct ath_hal *, 304 int16_t nfarray[]); 305 306 void *ah_eeprom; /* opaque EEPROM state */ 307 uint16_t ah_eeversion; /* EEPROM version */ 308 void (*ah_eepromDetach)(struct ath_hal *); 309 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 310 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 311 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 312 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 313 const void *args, uint32_t argsize, 314 void **result, uint32_t *resultsize); 315 316 /* 317 * Device revision information. 318 */ 319 uint16_t ah_devid; /* PCI device ID */ 320 uint16_t ah_subvendorid; /* PCI subvendor ID */ 321 uint32_t ah_macVersion; /* MAC version id */ 322 uint16_t ah_macRev; /* MAC revision */ 323 uint16_t ah_phyRev; /* PHY revision */ 324 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 325 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 326 uint32_t ah_flags; /* misc flags */ 327 uint8_t ah_ispcie; /* PCIE, special treatment */ 328 uint8_t ah_devType; /* card type - CB, PCI, PCIe */ 329 330 HAL_OPMODE ah_opmode; /* operating mode from reset */ 331 const struct ieee80211_channel *ah_curchan;/* operating channel */ 332 HAL_CAPABILITIES ah_caps; /* device capabilities */ 333 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 334 int16_t ah_powerLimit; /* tx power cap */ 335 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 336 u_int ah_tpScale; /* tx power scale factor */ 337 uint32_t ah_11nCompat; /* 11n compat controls */ 338 339 /* 340 * State for regulatory domain handling. 341 */ 342 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 343 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 344 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 345 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 346 u_int ah_nchan; /* valid items in ah_channels */ 347 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 348 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 349 350 uint8_t ah_coverageClass; /* coverage class */ 351 /* 352 * RF Silent handling; setup according to the EEPROM. 353 */ 354 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 355 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 356 /* 357 * Diagnostic support for discriminating HIUERR reports. 358 */ 359 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 360 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 361}; 362 363#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 364 365#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 366 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 367#define ath_hal_getWirelessModes(_ah) \ 368 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 369#define ath_hal_eepromRead(_ah, _off, _data) \ 370 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 371#define ath_hal_eepromWrite(_ah, _off, _data) \ 372 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 373#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 374 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 375#define ath_hal_gpioCfgInput(_ah, _gpio) \ 376 (_ah)->ah_gpioCfgInput(_ah, _gpio) 377#define ath_hal_gpioGet(_ah, _gpio) \ 378 (_ah)->ah_gpioGet(_ah, _gpio) 379#define ath_hal_gpioSet(_ah, _gpio, _val) \ 380 (_ah)->ah_gpioSet(_ah, _gpio, _val) 381#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 382 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 383#define ath_hal_getpowerlimits(_ah, _chan) \ 384 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 385#define ath_hal_getNfAdjust(_ah, _c) \ 386 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 387#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 388 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 389#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 390 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 391#define ath_hal_disablePCIE(_ah) \ 392 (_ah)->ah_disablePCIE(_ah) 393#define ath_hal_setInterrupts(_ah, _mask) \ 394 (_ah)->ah_setInterrupts(_ah, _mask) 395 396#define ath_hal_eepromDetach(_ah) do { \ 397 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 398 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 399} while (0) 400#define ath_hal_eepromGet(_ah, _param, _val) \ 401 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 402#define ath_hal_eepromSet(_ah, _param, _val) \ 403 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 404#define ath_hal_eepromGetFlag(_ah, _param) \ 405 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 406#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 407 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 408#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 409 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 410 411#ifndef _NET_IF_IEEE80211_H_ 412/* 413 * Stuff that would naturally come from _ieee80211.h 414 */ 415#define IEEE80211_ADDR_LEN 6 416 417#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 418#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 419#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 420 421#define IEEE80211_CRC_LEN 4 422 423#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 424 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 425#endif /* _NET_IF_IEEE80211_H_ */ 426 427#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 428 429#define INIT_AIFS 2 430#define INIT_CWMIN 15 431#define INIT_CWMIN_11B 31 432#define INIT_CWMAX 1023 433#define INIT_SH_RETRY 10 434#define INIT_LG_RETRY 10 435#define INIT_SSH_RETRY 32 436#define INIT_SLG_RETRY 32 437 438typedef struct { 439 uint32_t tqi_ver; /* HAL TXQ verson */ 440 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 441 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 442 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 443 uint32_t tqi_priority; 444 uint32_t tqi_aifs; /* aifs */ 445 uint32_t tqi_cwmin; /* cwMin */ 446 uint32_t tqi_cwmax; /* cwMax */ 447 uint16_t tqi_shretry; /* frame short retry limit */ 448 uint16_t tqi_lgretry; /* frame long retry limit */ 449 uint32_t tqi_cbrPeriod; 450 uint32_t tqi_cbrOverflowLimit; 451 uint32_t tqi_burstTime; 452 uint32_t tqi_readyTime; 453 uint32_t tqi_physCompBuf; 454 uint32_t tqi_intFlags; /* flags for internal use */ 455} HAL_TX_QUEUE_INFO; 456 457extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 458 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 459extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 460 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 461 462#define HAL_SPUR_VAL_MASK 0x3FFF 463#define HAL_SPUR_CHAN_WIDTH 87 464#define HAL_BIN_WIDTH_BASE_100HZ 3125 465#define HAL_BIN_WIDTH_TURBO_100HZ 6250 466#define HAL_MAX_BINS_ALLOWED 28 467 468#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 469#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 470 471#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 472 473/* 474 * Deduce if the host cpu has big- or litt-endian byte order. 475 */ 476static __inline__ int 477isBigEndian(void) 478{ 479 union { 480 int32_t i; 481 char c[4]; 482 } u; 483 u.i = 1; 484 return (u.c[0] == 0); 485} 486 487/* unalligned little endian access */ 488#define LE_READ_2(p) \ 489 ((uint16_t) \ 490 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 491#define LE_READ_4(p) \ 492 ((uint32_t) \ 493 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 494 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 495 496/* 497 * Register manipulation macros that expect bit field defines 498 * to follow the convention that an _S suffix is appended for 499 * a shift count, while the field mask has no suffix. 500 */ 501#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 502#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 503#define OS_REG_RMW(_a, _r, _set, _clr) \ 504 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 505#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 506 OS_REG_WRITE(_a, _r, \ 507 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 508#define OS_REG_SET_BIT(_a, _r, _f) \ 509 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 510#define OS_REG_CLR_BIT(_a, _r, _f) \ 511 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 512#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 513 ((OS_REG_READ(_a, _r) & (_f)) != 0) 514 515/* Analog register writes may require a delay between each one (eg Merlin?) */ 516#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 517 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \ 518 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 519#define OS_A_REG_WRITE(_a, _r, _v) \ 520 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 521 522/* wait for the register contents to have the specified value */ 523extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 524 uint32_t mask, uint32_t val); 525extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 526 uint32_t mask, uint32_t val, uint32_t timeout); 527 528/* return the first n bits in val reversed */ 529extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 530 531/* printf interfaces */ 532extern void ath_hal_printf(struct ath_hal *, const char*, ...) 533 __printflike(2,3); 534extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 535 __printflike(2, 0); 536extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 537 538/* allocate and free memory */ 539extern void *ath_hal_malloc(size_t); 540extern void ath_hal_free(void *); 541 542/* common debugging interfaces */ 543#ifdef AH_DEBUG 544#include "ah_debug.h" 545extern int ath_hal_debug; /* Global debug flags */ 546 547/* 548 * The typecast is purely because some callers will pass in 549 * AH_NULL directly rather than using a NULL ath_hal pointer. 550 */ 551#define HALDEBUG(_ah, __m, ...) \ 552 do { \ 553 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 554 ath_hal_debug & (__m) || \ 555 ((_ah) != NULL && \ 556 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 557 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 558 } \ 559 } while(0); 560 561extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 562 __printflike(3,4); 563#else 564#define HALDEBUG(_ah, __m, ...) 565#endif /* AH_DEBUG */ 566 567/* 568 * Register logging definitions shared with ardecode. 569 */ 570#include "ah_decode.h" 571 572/* 573 * Common assertion interface. Note: it is a bad idea to generate 574 * an assertion failure for any recoverable event. Instead catch 575 * the violation and, if possible, fix it up or recover from it; either 576 * with an error return value or a diagnostic messages. System software 577 * does not panic unless the situation is hopeless. 578 */ 579#ifdef AH_ASSERT 580extern void ath_hal_assert_failed(const char* filename, 581 int lineno, const char* msg); 582 583#define HALASSERT(_x) do { \ 584 if (!(_x)) { \ 585 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 586 } \ 587} while (0) 588#else 589#define HALASSERT(_x) 590#endif /* AH_ASSERT */ 591 592/* 593 * Regulatory domain support. 594 */ 595 596/* 597 * Return the max allowed antenna gain and apply any regulatory 598 * domain specific changes. 599 */ 600u_int ath_hal_getantennareduction(struct ath_hal *ah, 601 const struct ieee80211_channel *chan, u_int twiceGain); 602 603/* 604 * Return the test group for the specific channel based on 605 * the current regulatory setup. 606 */ 607u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 608 609/* 610 * Map a public channel definition to the corresponding 611 * internal data structure. This implicitly specifies 612 * whether or not the specified channel is ok to use 613 * based on the current regulatory domain constraints. 614 */ 615#ifndef AH_DEBUG 616static OS_INLINE HAL_CHANNEL_INTERNAL * 617ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 618{ 619 HAL_CHANNEL_INTERNAL *cc; 620 621 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 622 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 623 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 624 return cc; 625} 626#else 627/* NB: non-inline version that checks state */ 628HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 629 const struct ieee80211_channel *); 630#endif /* AH_DEBUG */ 631 632/* 633 * Return the h/w frequency for a channel. This may be 634 * different from ic_freq if this is a GSM device that 635 * takes 2.4GHz frequencies and down-converts them. 636 */ 637static OS_INLINE uint16_t 638ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 639{ 640 return ath_hal_checkchannel(ah, c)->channel; 641} 642 643/* 644 * Convert between microseconds and core system clocks. 645 */ 646extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 647extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 648 649/* 650 * Generic get/set capability support. Each chip overrides 651 * this routine to support chip-specific capabilities. 652 */ 653extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 654 HAL_CAPABILITY_TYPE type, uint32_t capability, 655 uint32_t *result); 656extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 657 HAL_CAPABILITY_TYPE type, uint32_t capability, 658 uint32_t setting, HAL_STATUS *status); 659 660/* The diagnostic codes used to be internally defined here -adrian */ 661#include "ah_diagcodes.h" 662 663/* 664 * The AR5416 and later HALs have MAC and baseband hang checking. 665 */ 666typedef struct { 667 uint32_t hang_reg_offset; 668 uint32_t hang_val; 669 uint32_t hang_mask; 670 uint32_t hang_offset; 671} hal_hw_hang_check_t; 672 673typedef struct { 674 uint32_t dma_dbg_3; 675 uint32_t dma_dbg_4; 676 uint32_t dma_dbg_5; 677 uint32_t dma_dbg_6; 678} mac_dbg_regs_t; 679 680typedef enum { 681 dcu_chain_state = 0x1, 682 dcu_complete_state = 0x2, 683 qcu_state = 0x4, 684 qcu_fsp_ok = 0x8, 685 qcu_fsp_state = 0x10, 686 qcu_stitch_state = 0x20, 687 qcu_fetch_state = 0x40, 688 qcu_complete_state = 0x80 689} hal_mac_hangs_t; 690 691typedef struct { 692 int states; 693 uint8_t dcu_chain_state; 694 uint8_t dcu_complete_state; 695 uint8_t qcu_state; 696 uint8_t qcu_fsp_ok; 697 uint8_t qcu_fsp_state; 698 uint8_t qcu_stitch_state; 699 uint8_t qcu_fetch_state; 700 uint8_t qcu_complete_state; 701} hal_mac_hang_check_t; 702 703enum { 704 HAL_BB_HANG_DFS = 0x0001, 705 HAL_BB_HANG_RIFS = 0x0002, 706 HAL_BB_HANG_RX_CLEAR = 0x0004, 707 HAL_BB_HANG_UNKNOWN = 0x0080, 708 709 HAL_MAC_HANG_SIG1 = 0x0100, 710 HAL_MAC_HANG_SIG2 = 0x0200, 711 HAL_MAC_HANG_UNKNOWN = 0x8000, 712 713 HAL_BB_HANGS = HAL_BB_HANG_DFS 714 | HAL_BB_HANG_RIFS 715 | HAL_BB_HANG_RX_CLEAR 716 | HAL_BB_HANG_UNKNOWN, 717 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 718 | HAL_MAC_HANG_SIG2 719 | HAL_MAC_HANG_UNKNOWN, 720}; 721 722/* 723 * Device revision information. 724 */ 725typedef struct { 726 uint16_t ah_devid; /* PCI device ID */ 727 uint16_t ah_subvendorid; /* PCI subvendor ID */ 728 uint32_t ah_macVersion; /* MAC version id */ 729 uint16_t ah_macRev; /* MAC revision */ 730 uint16_t ah_phyRev; /* PHY revision */ 731 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 732 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 733} HAL_REVS; 734 735/* 736 * Argument payload for HAL_DIAG_SETKEY. 737 */ 738typedef struct { 739 HAL_KEYVAL dk_keyval; 740 uint16_t dk_keyix; /* key index */ 741 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 742 int dk_xor; /* XOR key data */ 743} HAL_DIAG_KEYVAL; 744 745/* 746 * Argument payload for HAL_DIAG_EEWRITE. 747 */ 748typedef struct { 749 uint16_t ee_off; /* eeprom offset */ 750 uint16_t ee_data; /* write data */ 751} HAL_DIAG_EEVAL; 752 753 754typedef struct { 755 u_int offset; /* reg offset */ 756 uint32_t val; /* reg value */ 757} HAL_DIAG_REGVAL; 758 759/* 760 * 11n compatibility tweaks. 761 */ 762#define HAL_DIAG_11N_SERVICES 0x00000003 763#define HAL_DIAG_11N_SERVICES_S 0 764#define HAL_DIAG_11N_TXSTOMP 0x0000000c 765#define HAL_DIAG_11N_TXSTOMP_S 2 766 767typedef struct { 768 int maxNoiseImmunityLevel; /* [0..4] */ 769 int totalSizeDesired[5]; 770 int coarseHigh[5]; 771 int coarseLow[5]; 772 int firpwr[5]; 773 774 int maxSpurImmunityLevel; /* [0..7] */ 775 int cycPwrThr1[8]; 776 777 int maxFirstepLevel; /* [0..2] */ 778 int firstep[3]; 779 780 uint32_t ofdmTrigHigh; 781 uint32_t ofdmTrigLow; 782 int32_t cckTrigHigh; 783 int32_t cckTrigLow; 784 int32_t rssiThrLow; 785 int32_t rssiThrHigh; 786 787 int period; /* update listen period */ 788} HAL_ANI_PARAMS; 789 790extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 791 const void *args, uint32_t argsize, 792 void **result, uint32_t *resultsize); 793 794/* 795 * Setup a h/w rate table for use. 796 */ 797extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 798 799/* 800 * Common routine for implementing getChanNoise api. 801 */ 802int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 803 804/* 805 * Initialization support. 806 */ 807typedef struct { 808 const uint32_t *data; 809 int rows, cols; 810} HAL_INI_ARRAY; 811 812#define HAL_INI_INIT(_ia, _data, _cols) do { \ 813 (_ia)->data = (const uint32_t *)(_data); \ 814 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 815 (_ia)->cols = (_cols); \ 816} while (0) 817#define HAL_INI_VAL(_ia, _r, _c) \ 818 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 819 820/* 821 * OS_DELAY() does a PIO READ on the PCI bus which allows 822 * other cards' DMA reads to complete in the middle of our reset. 823 */ 824#define DMA_YIELD(x) do { \ 825 if ((++(x) % 64) == 0) \ 826 OS_DELAY(1); \ 827} while (0) 828 829#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 830 int r; \ 831 for (r = 0; r < N(regArray); r++) { \ 832 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 833 DMA_YIELD(regWr); \ 834 } \ 835} while (0) 836 837#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 838 int r; \ 839 for (r = 0; r < N(regArray); r++) { \ 840 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 841 DMA_YIELD(regWr); \ 842 } \ 843} while (0) 844 845extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 846 int col, int regWr); 847extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 848 int col); 849extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 850 const uint32_t data[], int regWr); 851 852#define CCK_SIFS_TIME 10 853#define CCK_PREAMBLE_BITS 144 854#define CCK_PLCP_BITS 48 855 856#define OFDM_SIFS_TIME 16 857#define OFDM_PREAMBLE_TIME 20 858#define OFDM_PLCP_BITS 22 859#define OFDM_SYMBOL_TIME 4 860 861#define OFDM_HALF_SIFS_TIME 32 862#define OFDM_HALF_PREAMBLE_TIME 40 863#define OFDM_HALF_PLCP_BITS 22 864#define OFDM_HALF_SYMBOL_TIME 8 865 866#define OFDM_QUARTER_SIFS_TIME 64 867#define OFDM_QUARTER_PREAMBLE_TIME 80 868#define OFDM_QUARTER_PLCP_BITS 22 869#define OFDM_QUARTER_SYMBOL_TIME 16 870 871#define TURBO_SIFS_TIME 8 872#define TURBO_PREAMBLE_TIME 14 873#define TURBO_PLCP_BITS 22 874#define TURBO_SYMBOL_TIME 4 875 876#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 877 878/* Generic EEPROM board value functions */ 879extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 880 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 881extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 882 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 883 uint8_t *pRetVpdList); 884extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 885 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 886 887/* Whether 5ghz fast clock is needed */ 888/* 889 * The chipset (Merlin, AR9300/later) should set the capability flag below; 890 * this flag simply says that the hardware can do it, not that the EEPROM 891 * says it can. 892 * 893 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 894 * if the relevant eeprom flag is set. 895 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 896 * by default. 897 */ 898#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 899 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 900 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 901 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 902 903 904#endif /* _ATH_AH_INTERAL_H_ */ 905