ah_internal.h revision 237868
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 237868 2012-07-01 03:15:18Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Each chip or class of chips registers to offer support. 83 */ 84struct ath_hal_chip { 85 const char *name; 86 const char *(*probe)(uint16_t vendorid, uint16_t devid); 87 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 88 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 89 HAL_STATUS *error); 90}; 91#ifndef AH_CHIP 92#define AH_CHIP(_name, _probe, _attach) \ 93static struct ath_hal_chip _name##_chip = { \ 94 .name = #_name, \ 95 .probe = _probe, \ 96 .attach = _attach \ 97}; \ 98OS_DATA_SET(ah_chips, _name##_chip) 99#endif 100 101/* 102 * Each RF backend registers to offer support; this is mostly 103 * used by multi-chip 5212 solutions. Single-chip solutions 104 * have a fixed idea about which RF to use. 105 */ 106struct ath_hal_rf { 107 const char *name; 108 HAL_BOOL (*probe)(struct ath_hal *ah); 109 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 110}; 111#ifndef AH_RF 112#define AH_RF(_name, _probe, _attach) \ 113static struct ath_hal_rf _name##_rf = { \ 114 .name = __STRING(_name), \ 115 .probe = _probe, \ 116 .attach = _attach \ 117}; \ 118OS_DATA_SET(ah_rfs, _name##_rf) 119#endif 120 121struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 122 123/* 124 * Maximum number of internal channels. Entries are per unique 125 * frequency so this might be need to be increased to handle all 126 * usage cases; typically no more than 32 are really needed but 127 * dynamically allocating the data structures is a bit painful 128 * right now. 129 */ 130#ifndef AH_MAXCHAN 131#define AH_MAXCHAN 96 132#endif 133 134/* 135 * Internal per-channel state. These are found 136 * using ic_devdata in the ieee80211_channel. 137 */ 138typedef struct { 139 uint16_t channel; /* h/w frequency, NB: may be mapped */ 140 uint8_t privFlags; 141#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 142#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 143#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 144#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 145 uint8_t calValid; /* bitmask of cal types */ 146 int8_t iCoff; 147 int8_t qCoff; 148 int16_t rawNoiseFloor; 149 int16_t noiseFloorAdjust; 150#ifdef AH_SUPPORT_AR5416 151 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 152 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 153#endif /* AH_SUPPORT_AR5416 */ 154 uint16_t mainSpur; /* cached spur value for this channel */ 155} HAL_CHANNEL_INTERNAL; 156 157/* channel requires noise floor check */ 158#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 159 160/* all full-width channels */ 161#define IEEE80211_CHAN_ALLFULL \ 162 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 163#define IEEE80211_CHAN_ALLTURBOFULL \ 164 (IEEE80211_CHAN_ALLTURBO - \ 165 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 166 167typedef struct { 168 uint32_t halChanSpreadSupport : 1, 169 halSleepAfterBeaconBroken : 1, 170 halCompressSupport : 1, 171 halBurstSupport : 1, 172 halFastFramesSupport : 1, 173 halChapTuningSupport : 1, 174 halTurboGSupport : 1, 175 halTurboPrimeSupport : 1, 176 halMicAesCcmSupport : 1, 177 halMicCkipSupport : 1, 178 halMicTkipSupport : 1, 179 halTkipMicTxRxKeySupport : 1, 180 halCipherAesCcmSupport : 1, 181 halCipherCkipSupport : 1, 182 halCipherTkipSupport : 1, 183 halPSPollBroken : 1, 184 halVEOLSupport : 1, 185 halBssIdMaskSupport : 1, 186 halMcastKeySrchSupport : 1, 187 halTsfAddSupport : 1, 188 halChanHalfRate : 1, 189 halChanQuarterRate : 1, 190 halHTSupport : 1, 191 halHTSGI20Support : 1, 192 halRfSilentSupport : 1, 193 halHwPhyCounterSupport : 1, 194 halWowSupport : 1, 195 halWowMatchPatternExact : 1, 196 halAutoSleepSupport : 1, 197 halFastCCSupport : 1, 198 halBtCoexSupport : 1; 199 uint32_t halRxStbcSupport : 1, 200 halTxStbcSupport : 1, 201 halGTTSupport : 1, 202 halCSTSupport : 1, 203 halRifsRxSupport : 1, 204 halRifsTxSupport : 1, 205 hal4AddrAggrSupport : 1, 206 halExtChanDfsSupport : 1, 207 halUseCombinedRadarRssi : 1, 208 halForcePpmSupport : 1, 209 halEnhancedPmSupport : 1, 210 halEnhancedDfsSupport : 1, 211 halMbssidAggrSupport : 1, 212 halBssidMatchSupport : 1, 213 hal4kbSplitTransSupport : 1, 214 halHasRxSelfLinkedTail : 1, 215 halSupportsFastClock5GHz : 1, 216 halHasLongRxDescTsf : 1, 217 halHasBBReadWar : 1, 218 halSerialiseRegWar : 1, 219 halMciSupport : 1, 220 halRxTxAbortSupport : 1, 221 halPaprdEnabled : 1, 222 halHasUapsdSupport : 1, 223 halWpsPushButtonSupport : 1, 224 halBtCoexApsmWar : 1, 225 halGenTimerSupport : 1, 226 halLDPCSupport : 1, 227 halHwBeaconProcSupport : 1, 228 halEnhancedDmaSupport : 1; 229 uint32_t halIsrRacSupport : 1, 230 halApmEnable : 1, 231 halIntrMitigation : 1; 232 233 uint32_t halWirelessModes; 234 uint16_t halTotalQueues; 235 uint16_t halKeyCacheSize; 236 uint16_t halLow5GhzChan, halHigh5GhzChan; 237 uint16_t halLow2GhzChan, halHigh2GhzChan; 238 int halTstampPrecision; 239 int halRtsAggrLimit; 240 uint8_t halTxChainMask; 241 uint8_t halRxChainMask; 242 uint8_t halNumGpioPins; 243 uint8_t halNumAntCfg2GHz; 244 uint8_t halNumAntCfg5GHz; 245 uint32_t halIntrMask; 246 uint8_t halTxStreams; 247 uint8_t halRxStreams; 248 249 int halNumTxMaps; 250 int halTxDescLen; 251 int halTxStatusLen; 252 int halRxStatusLen; 253 int halRxHpFifoDepth; 254 int halRxLpFifoDepth; 255} HAL_CAPABILITIES; 256 257struct regDomain; 258 259/* 260 * The ``private area'' follows immediately after the ``public area'' 261 * in the data structure returned by ath_hal_attach. Private data are 262 * used by device-independent code such as the regulatory domain support. 263 * In general, code within the HAL should never depend on data in the 264 * public area. Instead any public data needed internally should be 265 * shadowed here. 266 * 267 * When declaring a device-specific ath_hal data structure this structure 268 * is assumed to at the front; e.g. 269 * 270 * struct ath_hal_5212 { 271 * struct ath_hal_private ah_priv; 272 * ... 273 * }; 274 * 275 * It might be better to manage the method pointers in this structure 276 * using an indirect pointer to a read-only data structure but this would 277 * disallow class-style method overriding. 278 */ 279struct ath_hal_private { 280 struct ath_hal h; /* public area */ 281 282 /* NB: all methods go first to simplify initialization */ 283 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 284 uint16_t channelFlags, 285 uint16_t *lowChannel, uint16_t *highChannel); 286 u_int (*ah_getWirelessModes)(struct ath_hal*); 287 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 288 uint16_t *data); 289 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 290 uint16_t data); 291 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 292 struct ieee80211_channel *); 293 int16_t (*ah_getNfAdjust)(struct ath_hal *, 294 const HAL_CHANNEL_INTERNAL*); 295 void (*ah_getNoiseFloor)(struct ath_hal *, 296 int16_t nfarray[]); 297 298 void *ah_eeprom; /* opaque EEPROM state */ 299 uint16_t ah_eeversion; /* EEPROM version */ 300 void (*ah_eepromDetach)(struct ath_hal *); 301 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 302 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 303 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 304 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 305 const void *args, uint32_t argsize, 306 void **result, uint32_t *resultsize); 307 308 /* 309 * Device revision information. 310 */ 311 uint16_t ah_devid; /* PCI device ID */ 312 uint16_t ah_subvendorid; /* PCI subvendor ID */ 313 uint32_t ah_macVersion; /* MAC version id */ 314 uint16_t ah_macRev; /* MAC revision */ 315 uint16_t ah_phyRev; /* PHY revision */ 316 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 317 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 318 uint8_t ah_ispcie; /* PCIE, special treatment */ 319 320 HAL_OPMODE ah_opmode; /* operating mode from reset */ 321 const struct ieee80211_channel *ah_curchan;/* operating channel */ 322 HAL_CAPABILITIES ah_caps; /* device capabilities */ 323 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 324 int16_t ah_powerLimit; /* tx power cap */ 325 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 326 u_int ah_tpScale; /* tx power scale factor */ 327 uint32_t ah_11nCompat; /* 11n compat controls */ 328 329 /* 330 * State for regulatory domain handling. 331 */ 332 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 333 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 334 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 335 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 336 u_int ah_nchan; /* valid items in ah_channels */ 337 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 338 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 339 340 uint8_t ah_coverageClass; /* coverage class */ 341 /* 342 * RF Silent handling; setup according to the EEPROM. 343 */ 344 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 345 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 346 /* 347 * Diagnostic support for discriminating HIUERR reports. 348 */ 349 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 350 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 351}; 352 353#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 354 355#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 356 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 357#define ath_hal_getWirelessModes(_ah) \ 358 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 359#define ath_hal_eepromRead(_ah, _off, _data) \ 360 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 361#define ath_hal_eepromWrite(_ah, _off, _data) \ 362 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 363#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 364 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 365#define ath_hal_gpioCfgInput(_ah, _gpio) \ 366 (_ah)->ah_gpioCfgInput(_ah, _gpio) 367#define ath_hal_gpioGet(_ah, _gpio) \ 368 (_ah)->ah_gpioGet(_ah, _gpio) 369#define ath_hal_gpioSet(_ah, _gpio, _val) \ 370 (_ah)->ah_gpioSet(_ah, _gpio, _val) 371#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 372 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 373#define ath_hal_getpowerlimits(_ah, _chan) \ 374 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 375#define ath_hal_getNfAdjust(_ah, _c) \ 376 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 377#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 378 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 379#define ath_hal_configPCIE(_ah, _reset, _poweroff) \ 380 (_ah)->ah_configPCIE(_ah, _reset, _poweroff) 381#define ath_hal_disablePCIE(_ah) \ 382 (_ah)->ah_disablePCIE(_ah) 383#define ath_hal_setInterrupts(_ah, _mask) \ 384 (_ah)->ah_setInterrupts(_ah, _mask) 385 386#define ath_hal_eepromDetach(_ah) do { \ 387 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 388 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 389} while (0) 390#define ath_hal_eepromGet(_ah, _param, _val) \ 391 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 392#define ath_hal_eepromSet(_ah, _param, _val) \ 393 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 394#define ath_hal_eepromGetFlag(_ah, _param) \ 395 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 396#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 397 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 398#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 399 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 400 401#ifndef _NET_IF_IEEE80211_H_ 402/* 403 * Stuff that would naturally come from _ieee80211.h 404 */ 405#define IEEE80211_ADDR_LEN 6 406 407#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 408#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 409#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 410 411#define IEEE80211_CRC_LEN 4 412 413#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 414 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 415#endif /* _NET_IF_IEEE80211_H_ */ 416 417#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 418 419#define INIT_AIFS 2 420#define INIT_CWMIN 15 421#define INIT_CWMIN_11B 31 422#define INIT_CWMAX 1023 423#define INIT_SH_RETRY 10 424#define INIT_LG_RETRY 10 425#define INIT_SSH_RETRY 32 426#define INIT_SLG_RETRY 32 427 428typedef struct { 429 uint32_t tqi_ver; /* HAL TXQ verson */ 430 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 431 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 432 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 433 uint32_t tqi_priority; 434 uint32_t tqi_aifs; /* aifs */ 435 uint32_t tqi_cwmin; /* cwMin */ 436 uint32_t tqi_cwmax; /* cwMax */ 437 uint16_t tqi_shretry; /* frame short retry limit */ 438 uint16_t tqi_lgretry; /* frame long retry limit */ 439 uint32_t tqi_cbrPeriod; 440 uint32_t tqi_cbrOverflowLimit; 441 uint32_t tqi_burstTime; 442 uint32_t tqi_readyTime; 443 uint32_t tqi_physCompBuf; 444 uint32_t tqi_intFlags; /* flags for internal use */ 445} HAL_TX_QUEUE_INFO; 446 447extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 448 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 449extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 450 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 451 452#define HAL_SPUR_VAL_MASK 0x3FFF 453#define HAL_SPUR_CHAN_WIDTH 87 454#define HAL_BIN_WIDTH_BASE_100HZ 3125 455#define HAL_BIN_WIDTH_TURBO_100HZ 6250 456#define HAL_MAX_BINS_ALLOWED 28 457 458#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 459#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 460 461#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 462 463/* 464 * Deduce if the host cpu has big- or litt-endian byte order. 465 */ 466static __inline__ int 467isBigEndian(void) 468{ 469 union { 470 int32_t i; 471 char c[4]; 472 } u; 473 u.i = 1; 474 return (u.c[0] == 0); 475} 476 477/* unalligned little endian access */ 478#define LE_READ_2(p) \ 479 ((uint16_t) \ 480 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 481#define LE_READ_4(p) \ 482 ((uint32_t) \ 483 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 484 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 485 486/* 487 * Register manipulation macros that expect bit field defines 488 * to follow the convention that an _S suffix is appended for 489 * a shift count, while the field mask has no suffix. 490 */ 491#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 492#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 493#define OS_REG_RMW(_a, _r, _set, _clr) \ 494 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 495#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 496 OS_REG_WRITE(_a, _r, \ 497 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 498#define OS_REG_SET_BIT(_a, _r, _f) \ 499 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 500#define OS_REG_CLR_BIT(_a, _r, _f) \ 501 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 502#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 503 ((OS_REG_READ(_a, _r) & (_f)) != 0) 504 505/* Analog register writes may require a delay between each one (eg Merlin?) */ 506#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 507 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 508#define OS_A_REG_WRITE(_a, _r, _v) \ 509 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0) 510 511/* wait for the register contents to have the specified value */ 512extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 513 uint32_t mask, uint32_t val); 514extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 515 uint32_t mask, uint32_t val, uint32_t timeout); 516 517/* return the first n bits in val reversed */ 518extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 519 520/* printf interfaces */ 521extern void ath_hal_printf(struct ath_hal *, const char*, ...) 522 __printflike(2,3); 523extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 524 __printflike(2, 0); 525extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 526 527/* allocate and free memory */ 528extern void *ath_hal_malloc(size_t); 529extern void ath_hal_free(void *); 530 531/* common debugging interfaces */ 532#ifdef AH_DEBUG 533#include "ah_debug.h" 534extern int ath_hal_debug; /* Global debug flags */ 535 536/* 537 * The typecast is purely because some callers will pass in 538 * AH_NULL directly rather than using a NULL ath_hal pointer. 539 */ 540#define HALDEBUG(_ah, __m, ...) \ 541 do { \ 542 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 543 ath_hal_debug & (__m) || \ 544 ((_ah) != NULL && \ 545 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 546 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 547 } \ 548 } while(0); 549 550extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 551 __printflike(3,4); 552#else 553#define HALDEBUG(_ah, __m, ...) 554#endif /* AH_DEBUG */ 555 556/* 557 * Register logging definitions shared with ardecode. 558 */ 559#include "ah_decode.h" 560 561/* 562 * Common assertion interface. Note: it is a bad idea to generate 563 * an assertion failure for any recoverable event. Instead catch 564 * the violation and, if possible, fix it up or recover from it; either 565 * with an error return value or a diagnostic messages. System software 566 * does not panic unless the situation is hopeless. 567 */ 568#ifdef AH_ASSERT 569extern void ath_hal_assert_failed(const char* filename, 570 int lineno, const char* msg); 571 572#define HALASSERT(_x) do { \ 573 if (!(_x)) { \ 574 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 575 } \ 576} while (0) 577#else 578#define HALASSERT(_x) 579#endif /* AH_ASSERT */ 580 581/* 582 * Regulatory domain support. 583 */ 584 585/* 586 * Return the max allowed antenna gain and apply any regulatory 587 * domain specific changes. 588 */ 589u_int ath_hal_getantennareduction(struct ath_hal *ah, 590 const struct ieee80211_channel *chan, u_int twiceGain); 591 592/* 593 * Return the test group for the specific channel based on 594 * the current regulatory setup. 595 */ 596u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 597 598/* 599 * Map a public channel definition to the corresponding 600 * internal data structure. This implicitly specifies 601 * whether or not the specified channel is ok to use 602 * based on the current regulatory domain constraints. 603 */ 604#ifndef AH_DEBUG 605static OS_INLINE HAL_CHANNEL_INTERNAL * 606ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 607{ 608 HAL_CHANNEL_INTERNAL *cc; 609 610 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 611 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 612 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 613 return cc; 614} 615#else 616/* NB: non-inline version that checks state */ 617HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 618 const struct ieee80211_channel *); 619#endif /* AH_DEBUG */ 620 621/* 622 * Return the h/w frequency for a channel. This may be 623 * different from ic_freq if this is a GSM device that 624 * takes 2.4GHz frequencies and down-converts them. 625 */ 626static OS_INLINE uint16_t 627ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 628{ 629 return ath_hal_checkchannel(ah, c)->channel; 630} 631 632/* 633 * Convert between microseconds and core system clocks. 634 */ 635extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 636extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 637 638/* 639 * Generic get/set capability support. Each chip overrides 640 * this routine to support chip-specific capabilities. 641 */ 642extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 643 HAL_CAPABILITY_TYPE type, uint32_t capability, 644 uint32_t *result); 645extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 646 HAL_CAPABILITY_TYPE type, uint32_t capability, 647 uint32_t setting, HAL_STATUS *status); 648 649/* The diagnostic codes used to be internally defined here -adrian */ 650#include "ah_diagcodes.h" 651 652/* 653 * The AR5416 and later HALs have MAC and baseband hang checking. 654 */ 655typedef struct { 656 uint32_t hang_reg_offset; 657 uint32_t hang_val; 658 uint32_t hang_mask; 659 uint32_t hang_offset; 660} hal_hw_hang_check_t; 661 662typedef struct { 663 uint32_t dma_dbg_3; 664 uint32_t dma_dbg_4; 665 uint32_t dma_dbg_5; 666 uint32_t dma_dbg_6; 667} mac_dbg_regs_t; 668 669typedef enum { 670 dcu_chain_state = 0x1, 671 dcu_complete_state = 0x2, 672 qcu_state = 0x4, 673 qcu_fsp_ok = 0x8, 674 qcu_fsp_state = 0x10, 675 qcu_stitch_state = 0x20, 676 qcu_fetch_state = 0x40, 677 qcu_complete_state = 0x80 678} hal_mac_hangs_t; 679 680typedef struct { 681 int states; 682 uint8_t dcu_chain_state; 683 uint8_t dcu_complete_state; 684 uint8_t qcu_state; 685 uint8_t qcu_fsp_ok; 686 uint8_t qcu_fsp_state; 687 uint8_t qcu_stitch_state; 688 uint8_t qcu_fetch_state; 689 uint8_t qcu_complete_state; 690} hal_mac_hang_check_t; 691 692enum { 693 HAL_BB_HANG_DFS = 0x0001, 694 HAL_BB_HANG_RIFS = 0x0002, 695 HAL_BB_HANG_RX_CLEAR = 0x0004, 696 HAL_BB_HANG_UNKNOWN = 0x0080, 697 698 HAL_MAC_HANG_SIG1 = 0x0100, 699 HAL_MAC_HANG_SIG2 = 0x0200, 700 HAL_MAC_HANG_UNKNOWN = 0x8000, 701 702 HAL_BB_HANGS = HAL_BB_HANG_DFS 703 | HAL_BB_HANG_RIFS 704 | HAL_BB_HANG_RX_CLEAR 705 | HAL_BB_HANG_UNKNOWN, 706 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 707 | HAL_MAC_HANG_SIG2 708 | HAL_MAC_HANG_UNKNOWN, 709}; 710 711/* 712 * Device revision information. 713 */ 714typedef struct { 715 uint16_t ah_devid; /* PCI device ID */ 716 uint16_t ah_subvendorid; /* PCI subvendor ID */ 717 uint32_t ah_macVersion; /* MAC version id */ 718 uint16_t ah_macRev; /* MAC revision */ 719 uint16_t ah_phyRev; /* PHY revision */ 720 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 721 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 722} HAL_REVS; 723 724/* 725 * Argument payload for HAL_DIAG_SETKEY. 726 */ 727typedef struct { 728 HAL_KEYVAL dk_keyval; 729 uint16_t dk_keyix; /* key index */ 730 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 731 int dk_xor; /* XOR key data */ 732} HAL_DIAG_KEYVAL; 733 734/* 735 * Argument payload for HAL_DIAG_EEWRITE. 736 */ 737typedef struct { 738 uint16_t ee_off; /* eeprom offset */ 739 uint16_t ee_data; /* write data */ 740} HAL_DIAG_EEVAL; 741 742 743typedef struct { 744 u_int offset; /* reg offset */ 745 uint32_t val; /* reg value */ 746} HAL_DIAG_REGVAL; 747 748/* 749 * 11n compatibility tweaks. 750 */ 751#define HAL_DIAG_11N_SERVICES 0x00000003 752#define HAL_DIAG_11N_SERVICES_S 0 753#define HAL_DIAG_11N_TXSTOMP 0x0000000c 754#define HAL_DIAG_11N_TXSTOMP_S 2 755 756typedef struct { 757 int maxNoiseImmunityLevel; /* [0..4] */ 758 int totalSizeDesired[5]; 759 int coarseHigh[5]; 760 int coarseLow[5]; 761 int firpwr[5]; 762 763 int maxSpurImmunityLevel; /* [0..7] */ 764 int cycPwrThr1[8]; 765 766 int maxFirstepLevel; /* [0..2] */ 767 int firstep[3]; 768 769 uint32_t ofdmTrigHigh; 770 uint32_t ofdmTrigLow; 771 int32_t cckTrigHigh; 772 int32_t cckTrigLow; 773 int32_t rssiThrLow; 774 int32_t rssiThrHigh; 775 776 int period; /* update listen period */ 777} HAL_ANI_PARAMS; 778 779extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 780 const void *args, uint32_t argsize, 781 void **result, uint32_t *resultsize); 782 783/* 784 * Setup a h/w rate table for use. 785 */ 786extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 787 788/* 789 * Common routine for implementing getChanNoise api. 790 */ 791int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 792 793/* 794 * Initialization support. 795 */ 796typedef struct { 797 const uint32_t *data; 798 int rows, cols; 799} HAL_INI_ARRAY; 800 801#define HAL_INI_INIT(_ia, _data, _cols) do { \ 802 (_ia)->data = (const uint32_t *)(_data); \ 803 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 804 (_ia)->cols = (_cols); \ 805} while (0) 806#define HAL_INI_VAL(_ia, _r, _c) \ 807 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 808 809/* 810 * OS_DELAY() does a PIO READ on the PCI bus which allows 811 * other cards' DMA reads to complete in the middle of our reset. 812 */ 813#define DMA_YIELD(x) do { \ 814 if ((++(x) % 64) == 0) \ 815 OS_DELAY(1); \ 816} while (0) 817 818#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 819 int r; \ 820 for (r = 0; r < N(regArray); r++) { \ 821 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 822 DMA_YIELD(regWr); \ 823 } \ 824} while (0) 825 826#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 827 int r; \ 828 for (r = 0; r < N(regArray); r++) { \ 829 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 830 DMA_YIELD(regWr); \ 831 } \ 832} while (0) 833 834extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 835 int col, int regWr); 836extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 837 int col); 838extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 839 const uint32_t data[], int regWr); 840 841#define CCK_SIFS_TIME 10 842#define CCK_PREAMBLE_BITS 144 843#define CCK_PLCP_BITS 48 844 845#define OFDM_SIFS_TIME 16 846#define OFDM_PREAMBLE_TIME 20 847#define OFDM_PLCP_BITS 22 848#define OFDM_SYMBOL_TIME 4 849 850#define OFDM_HALF_SIFS_TIME 32 851#define OFDM_HALF_PREAMBLE_TIME 40 852#define OFDM_HALF_PLCP_BITS 22 853#define OFDM_HALF_SYMBOL_TIME 8 854 855#define OFDM_QUARTER_SIFS_TIME 64 856#define OFDM_QUARTER_PREAMBLE_TIME 80 857#define OFDM_QUARTER_PLCP_BITS 22 858#define OFDM_QUARTER_SYMBOL_TIME 16 859 860#define TURBO_SIFS_TIME 8 861#define TURBO_PREAMBLE_TIME 14 862#define TURBO_PLCP_BITS 22 863#define TURBO_SYMBOL_TIME 4 864 865#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 866 867/* Generic EEPROM board value functions */ 868extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 869 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 870extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 871 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 872 uint8_t *pRetVpdList); 873extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 874 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 875 876/* Whether 5ghz fast clock is needed */ 877/* 878 * The chipset (Merlin, AR9300/later) should set the capability flag below; 879 * this flag simply says that the hardware can do it, not that the EEPROM 880 * says it can. 881 * 882 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 883 * if the relevant eeprom flag is set. 884 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 885 * by default. 886 */ 887#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 888 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 889 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 890 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 891 892 893#endif /* _ATH_AH_INTERAL_H_ */ 894