ah_internal.h revision 229791
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 229791 2012-01-07 20:23:05Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef AH_SUPPORT_AR5416 34#define AH_SUPPORT_AR5416 1 35#endif 36 37#ifndef NBBY 38#define NBBY 8 /* number of bits/byte */ 39#endif 40 41#ifndef roundup 42#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 43#endif 44#ifndef howmany 45#define howmany(x, y) (((x)+((y)-1))/(y)) 46#endif 47 48#ifndef offsetof 49#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 50#endif 51 52typedef struct { 53 uint16_t start; /* first register */ 54 uint16_t end; /* ending register or zero */ 55} HAL_REGRANGE; 56 57typedef struct { 58 uint32_t addr; /* regiser address/offset */ 59 uint32_t value; /* value to write */ 60} HAL_REGWRITE; 61 62/* 63 * Transmit power scale factor. 64 * 65 * NB: This is not public because we want to discourage the use of 66 * scaling; folks should use the tx power limit interface. 67 */ 68typedef enum { 69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 73 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 74} HAL_TP_SCALE; 75 76typedef enum { 77 HAL_CAP_RADAR = 0, /* Radar capability */ 78 HAL_CAP_AR = 1, /* AR capability */ 79} HAL_PHYDIAG_CAPS; 80 81/* 82 * Each chip or class of chips registers to offer support. 83 */ 84struct ath_hal_chip { 85 const char *name; 86 const char *(*probe)(uint16_t vendorid, uint16_t devid); 87 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 88 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 89 HAL_STATUS *error); 90}; 91#ifndef AH_CHIP 92#define AH_CHIP(_name, _probe, _attach) \ 93static struct ath_hal_chip _name##_chip = { \ 94 .name = #_name, \ 95 .probe = _probe, \ 96 .attach = _attach \ 97}; \ 98OS_DATA_SET(ah_chips, _name##_chip) 99#endif 100 101/* 102 * Each RF backend registers to offer support; this is mostly 103 * used by multi-chip 5212 solutions. Single-chip solutions 104 * have a fixed idea about which RF to use. 105 */ 106struct ath_hal_rf { 107 const char *name; 108 HAL_BOOL (*probe)(struct ath_hal *ah); 109 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 110}; 111#ifndef AH_RF 112#define AH_RF(_name, _probe, _attach) \ 113static struct ath_hal_rf _name##_rf = { \ 114 .name = __STRING(_name), \ 115 .probe = _probe, \ 116 .attach = _attach \ 117}; \ 118OS_DATA_SET(ah_rfs, _name##_rf) 119#endif 120 121struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 122 123/* 124 * Maximum number of internal channels. Entries are per unique 125 * frequency so this might be need to be increased to handle all 126 * usage cases; typically no more than 32 are really needed but 127 * dynamically allocating the data structures is a bit painful 128 * right now. 129 */ 130#ifndef AH_MAXCHAN 131#define AH_MAXCHAN 96 132#endif 133 134/* 135 * Internal per-channel state. These are found 136 * using ic_devdata in the ieee80211_channel. 137 */ 138typedef struct { 139 uint16_t channel; /* h/w frequency, NB: may be mapped */ 140 uint8_t privFlags; 141#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 142#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 143#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 144#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 145 uint8_t calValid; /* bitmask of cal types */ 146 int8_t iCoff; 147 int8_t qCoff; 148 int16_t rawNoiseFloor; 149 int16_t noiseFloorAdjust; 150#ifdef AH_SUPPORT_AR5416 151 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 152 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 153#endif /* AH_SUPPORT_AR5416 */ 154 uint16_t mainSpur; /* cached spur value for this channel */ 155} HAL_CHANNEL_INTERNAL; 156 157/* channel requires noise floor check */ 158#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 159 160/* all full-width channels */ 161#define IEEE80211_CHAN_ALLFULL \ 162 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 163#define IEEE80211_CHAN_ALLTURBOFULL \ 164 (IEEE80211_CHAN_ALLTURBO - \ 165 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 166 167typedef struct { 168 uint32_t halChanSpreadSupport : 1, 169 halSleepAfterBeaconBroken : 1, 170 halCompressSupport : 1, 171 halBurstSupport : 1, 172 halFastFramesSupport : 1, 173 halChapTuningSupport : 1, 174 halTurboGSupport : 1, 175 halTurboPrimeSupport : 1, 176 halMicAesCcmSupport : 1, 177 halMicCkipSupport : 1, 178 halMicTkipSupport : 1, 179 halTkipMicTxRxKeySupport : 1, 180 halCipherAesCcmSupport : 1, 181 halCipherCkipSupport : 1, 182 halCipherTkipSupport : 1, 183 halPSPollBroken : 1, 184 halVEOLSupport : 1, 185 halBssIdMaskSupport : 1, 186 halMcastKeySrchSupport : 1, 187 halTsfAddSupport : 1, 188 halChanHalfRate : 1, 189 halChanQuarterRate : 1, 190 halHTSupport : 1, 191 halHTSGI20Support : 1, 192 halRfSilentSupport : 1, 193 halHwPhyCounterSupport : 1, 194 halWowSupport : 1, 195 halWowMatchPatternExact : 1, 196 halAutoSleepSupport : 1, 197 halFastCCSupport : 1, 198 halBtCoexSupport : 1; 199 uint32_t halRxStbcSupport : 1, 200 halTxStbcSupport : 1, 201 halGTTSupport : 1, 202 halCSTSupport : 1, 203 halRifsRxSupport : 1, 204 halRifsTxSupport : 1, 205 hal4AddrAggrSupport : 1, 206 halExtChanDfsSupport : 1, 207 halUseCombinedRadarRssi : 1, 208 halForcePpmSupport : 1, 209 halEnhancedPmSupport : 1, 210 halEnhancedDfsSupport : 1, 211 halMbssidAggrSupport : 1, 212 halBssidMatchSupport : 1, 213 hal4kbSplitTransSupport : 1, 214 halHasRxSelfLinkedTail : 1, 215 halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 216 halHasLongRxDescTsf : 1, 217 halHasBBReadWar : 1, 218 halSerialiseRegWar : 1; 219 uint32_t halWirelessModes; 220 uint16_t halTotalQueues; 221 uint16_t halKeyCacheSize; 222 uint16_t halLow5GhzChan, halHigh5GhzChan; 223 uint16_t halLow2GhzChan, halHigh2GhzChan; 224 int halTstampPrecision; 225 int halRtsAggrLimit; 226 uint8_t halTxChainMask; 227 uint8_t halRxChainMask; 228 uint8_t halNumGpioPins; 229 uint8_t halNumAntCfg2GHz; 230 uint8_t halNumAntCfg5GHz; 231 uint32_t halIntrMask; 232 uint8_t halTxStreams; 233 uint8_t halRxStreams; 234} HAL_CAPABILITIES; 235 236struct regDomain; 237 238/* 239 * The ``private area'' follows immediately after the ``public area'' 240 * in the data structure returned by ath_hal_attach. Private data are 241 * used by device-independent code such as the regulatory domain support. 242 * In general, code within the HAL should never depend on data in the 243 * public area. Instead any public data needed internally should be 244 * shadowed here. 245 * 246 * When declaring a device-specific ath_hal data structure this structure 247 * is assumed to at the front; e.g. 248 * 249 * struct ath_hal_5212 { 250 * struct ath_hal_private ah_priv; 251 * ... 252 * }; 253 * 254 * It might be better to manage the method pointers in this structure 255 * using an indirect pointer to a read-only data structure but this would 256 * disallow class-style method overriding. 257 */ 258struct ath_hal_private { 259 struct ath_hal h; /* public area */ 260 261 /* NB: all methods go first to simplify initialization */ 262 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 263 uint16_t channelFlags, 264 uint16_t *lowChannel, uint16_t *highChannel); 265 u_int (*ah_getWirelessModes)(struct ath_hal*); 266 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 267 uint16_t *data); 268 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 269 uint16_t data); 270 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 271 struct ieee80211_channel *); 272 int16_t (*ah_getNfAdjust)(struct ath_hal *, 273 const HAL_CHANNEL_INTERNAL*); 274 void (*ah_getNoiseFloor)(struct ath_hal *, 275 int16_t nfarray[]); 276 277 void *ah_eeprom; /* opaque EEPROM state */ 278 uint16_t ah_eeversion; /* EEPROM version */ 279 void (*ah_eepromDetach)(struct ath_hal *); 280 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 281 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 282 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 283 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 284 const void *args, uint32_t argsize, 285 void **result, uint32_t *resultsize); 286 287 /* 288 * Device revision information. 289 */ 290 uint16_t ah_devid; /* PCI device ID */ 291 uint16_t ah_subvendorid; /* PCI subvendor ID */ 292 uint32_t ah_macVersion; /* MAC version id */ 293 uint16_t ah_macRev; /* MAC revision */ 294 uint16_t ah_phyRev; /* PHY revision */ 295 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 296 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 297 uint8_t ah_ispcie; /* PCIE, special treatment */ 298 299 HAL_OPMODE ah_opmode; /* operating mode from reset */ 300 const struct ieee80211_channel *ah_curchan;/* operating channel */ 301 HAL_CAPABILITIES ah_caps; /* device capabilities */ 302 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 303 int16_t ah_powerLimit; /* tx power cap */ 304 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 305 u_int ah_tpScale; /* tx power scale factor */ 306 uint32_t ah_11nCompat; /* 11n compat controls */ 307 308 /* 309 * State for regulatory domain handling. 310 */ 311 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 312 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 313 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 314 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 315 u_int ah_nchan; /* valid items in ah_channels */ 316 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 317 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 318 319 uint8_t ah_coverageClass; /* coverage class */ 320 /* 321 * RF Silent handling; setup according to the EEPROM. 322 */ 323 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 324 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 325 /* 326 * Diagnostic support for discriminating HIUERR reports. 327 */ 328 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 329 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 330}; 331 332#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 333 334#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 335 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 336#define ath_hal_getWirelessModes(_ah) \ 337 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 338#define ath_hal_eepromRead(_ah, _off, _data) \ 339 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 340#define ath_hal_eepromWrite(_ah, _off, _data) \ 341 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 342#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 343 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 344#define ath_hal_gpioCfgInput(_ah, _gpio) \ 345 (_ah)->ah_gpioCfgInput(_ah, _gpio) 346#define ath_hal_gpioGet(_ah, _gpio) \ 347 (_ah)->ah_gpioGet(_ah, _gpio) 348#define ath_hal_gpioSet(_ah, _gpio, _val) \ 349 (_ah)->ah_gpioSet(_ah, _gpio, _val) 350#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 351 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 352#define ath_hal_getpowerlimits(_ah, _chan) \ 353 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 354#define ath_hal_getNfAdjust(_ah, _c) \ 355 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 356#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 357 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 358#define ath_hal_configPCIE(_ah, _reset) \ 359 (_ah)->ah_configPCIE(_ah, _reset) 360#define ath_hal_disablePCIE(_ah) \ 361 (_ah)->ah_disablePCIE(_ah) 362#define ath_hal_setInterrupts(_ah, _mask) \ 363 (_ah)->ah_setInterrupts(_ah, _mask) 364 365#define ath_hal_eepromDetach(_ah) do { \ 366 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 367 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 368} while (0) 369#define ath_hal_eepromGet(_ah, _param, _val) \ 370 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 371#define ath_hal_eepromSet(_ah, _param, _val) \ 372 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 373#define ath_hal_eepromGetFlag(_ah, _param) \ 374 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 375#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 376 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 377#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 378 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 379 380#ifndef _NET_IF_IEEE80211_H_ 381/* 382 * Stuff that would naturally come from _ieee80211.h 383 */ 384#define IEEE80211_ADDR_LEN 6 385 386#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 387#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 388#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 389 390#define IEEE80211_CRC_LEN 4 391 392#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 393 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 394#endif /* _NET_IF_IEEE80211_H_ */ 395 396#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 397 398#define INIT_AIFS 2 399#define INIT_CWMIN 15 400#define INIT_CWMIN_11B 31 401#define INIT_CWMAX 1023 402#define INIT_SH_RETRY 10 403#define INIT_LG_RETRY 10 404#define INIT_SSH_RETRY 32 405#define INIT_SLG_RETRY 32 406 407typedef struct { 408 uint32_t tqi_ver; /* HAL TXQ verson */ 409 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 410 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 411 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 412 uint32_t tqi_priority; 413 uint32_t tqi_aifs; /* aifs */ 414 uint32_t tqi_cwmin; /* cwMin */ 415 uint32_t tqi_cwmax; /* cwMax */ 416 uint16_t tqi_shretry; /* frame short retry limit */ 417 uint16_t tqi_lgretry; /* frame long retry limit */ 418 uint32_t tqi_cbrPeriod; 419 uint32_t tqi_cbrOverflowLimit; 420 uint32_t tqi_burstTime; 421 uint32_t tqi_readyTime; 422 uint32_t tqi_physCompBuf; 423 uint32_t tqi_intFlags; /* flags for internal use */ 424} HAL_TX_QUEUE_INFO; 425 426extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 427 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 428extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 429 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 430 431#define HAL_SPUR_VAL_MASK 0x3FFF 432#define HAL_SPUR_CHAN_WIDTH 87 433#define HAL_BIN_WIDTH_BASE_100HZ 3125 434#define HAL_BIN_WIDTH_TURBO_100HZ 6250 435#define HAL_MAX_BINS_ALLOWED 28 436 437#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 438#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 439 440#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 441 442/* 443 * Deduce if the host cpu has big- or litt-endian byte order. 444 */ 445static __inline__ int 446isBigEndian(void) 447{ 448 union { 449 int32_t i; 450 char c[4]; 451 } u; 452 u.i = 1; 453 return (u.c[0] == 0); 454} 455 456/* unalligned little endian access */ 457#define LE_READ_2(p) \ 458 ((uint16_t) \ 459 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 460#define LE_READ_4(p) \ 461 ((uint32_t) \ 462 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 463 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 464 465/* 466 * Register manipulation macros that expect bit field defines 467 * to follow the convention that an _S suffix is appended for 468 * a shift count, while the field mask has no suffix. 469 */ 470#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 471#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 472#define OS_REG_RMW(_a, _r, _set, _clr) \ 473 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 474#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 475 OS_REG_WRITE(_a, _r, \ 476 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 477#define OS_REG_SET_BIT(_a, _r, _f) \ 478 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 479#define OS_REG_CLR_BIT(_a, _r, _f) \ 480 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 481#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 482 ((OS_REG_READ(_a, _r) & (_f)) != 0) 483 484/* Analog register writes may require a delay between each one (eg Merlin?) */ 485#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 486 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 487 488/* wait for the register contents to have the specified value */ 489extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 490 uint32_t mask, uint32_t val); 491extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 492 uint32_t mask, uint32_t val, uint32_t timeout); 493 494/* return the first n bits in val reversed */ 495extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 496 497/* printf interfaces */ 498extern void ath_hal_printf(struct ath_hal *, const char*, ...) 499 __printflike(2,3); 500extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 501 __printflike(2, 0); 502extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 503 504/* allocate and free memory */ 505extern void *ath_hal_malloc(size_t); 506extern void ath_hal_free(void *); 507 508/* common debugging interfaces */ 509#ifdef AH_DEBUG 510#include "ah_debug.h" 511extern int ath_hal_debug; /* Global debug flags */ 512 513/* 514 * The typecast is purely because some callers will pass in 515 * AH_NULL directly rather than using a NULL ath_hal pointer. 516 */ 517#define HALDEBUG(_ah, __m, ...) \ 518 do { \ 519 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 520 ath_hal_debug & (__m) || \ 521 ((_ah) != NULL && \ 522 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 523 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 524 } \ 525 } while(0); 526 527extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 528 __printflike(3,4); 529#else 530#define HALDEBUG(_ah, __m, ...) 531#endif /* AH_DEBUG */ 532 533/* 534 * Register logging definitions shared with ardecode. 535 */ 536#include "ah_decode.h" 537 538/* 539 * Common assertion interface. Note: it is a bad idea to generate 540 * an assertion failure for any recoverable event. Instead catch 541 * the violation and, if possible, fix it up or recover from it; either 542 * with an error return value or a diagnostic messages. System software 543 * does not panic unless the situation is hopeless. 544 */ 545#ifdef AH_ASSERT 546extern void ath_hal_assert_failed(const char* filename, 547 int lineno, const char* msg); 548 549#define HALASSERT(_x) do { \ 550 if (!(_x)) { \ 551 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 552 } \ 553} while (0) 554#else 555#define HALASSERT(_x) 556#endif /* AH_ASSERT */ 557 558/* 559 * Regulatory domain support. 560 */ 561 562/* 563 * Return the max allowed antenna gain and apply any regulatory 564 * domain specific changes. 565 */ 566u_int ath_hal_getantennareduction(struct ath_hal *ah, 567 const struct ieee80211_channel *chan, u_int twiceGain); 568 569/* 570 * Return the test group for the specific channel based on 571 * the current regulatory setup. 572 */ 573u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 574 575/* 576 * Map a public channel definition to the corresponding 577 * internal data structure. This implicitly specifies 578 * whether or not the specified channel is ok to use 579 * based on the current regulatory domain constraints. 580 */ 581#ifndef AH_DEBUG 582static OS_INLINE HAL_CHANNEL_INTERNAL * 583ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 584{ 585 HAL_CHANNEL_INTERNAL *cc; 586 587 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 588 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 589 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 590 return cc; 591} 592#else 593/* NB: non-inline version that checks state */ 594HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 595 const struct ieee80211_channel *); 596#endif /* AH_DEBUG */ 597 598/* 599 * Return the h/w frequency for a channel. This may be 600 * different from ic_freq if this is a GSM device that 601 * takes 2.4GHz frequencies and down-converts them. 602 */ 603static OS_INLINE uint16_t 604ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 605{ 606 return ath_hal_checkchannel(ah, c)->channel; 607} 608 609/* 610 * Convert between microseconds and core system clocks. 611 */ 612extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 613extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 614 615/* 616 * Generic get/set capability support. Each chip overrides 617 * this routine to support chip-specific capabilities. 618 */ 619extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 620 HAL_CAPABILITY_TYPE type, uint32_t capability, 621 uint32_t *result); 622extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 623 HAL_CAPABILITY_TYPE type, uint32_t capability, 624 uint32_t setting, HAL_STATUS *status); 625 626/* The diagnostic codes used to be internally defined here -adrian */ 627#include "ah_diagcodes.h" 628 629enum { 630 HAL_BB_HANG_DFS = 0x0001, 631 HAL_BB_HANG_RIFS = 0x0002, 632 HAL_BB_HANG_RX_CLEAR = 0x0004, 633 HAL_BB_HANG_UNKNOWN = 0x0080, 634 635 HAL_MAC_HANG_SIG1 = 0x0100, 636 HAL_MAC_HANG_SIG2 = 0x0200, 637 HAL_MAC_HANG_UNKNOWN = 0x8000, 638 639 HAL_BB_HANGS = HAL_BB_HANG_DFS 640 | HAL_BB_HANG_RIFS 641 | HAL_BB_HANG_RX_CLEAR 642 | HAL_BB_HANG_UNKNOWN, 643 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 644 | HAL_MAC_HANG_SIG2 645 | HAL_MAC_HANG_UNKNOWN, 646}; 647 648/* 649 * Device revision information. 650 */ 651typedef struct { 652 uint16_t ah_devid; /* PCI device ID */ 653 uint16_t ah_subvendorid; /* PCI subvendor ID */ 654 uint32_t ah_macVersion; /* MAC version id */ 655 uint16_t ah_macRev; /* MAC revision */ 656 uint16_t ah_phyRev; /* PHY revision */ 657 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 658 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 659} HAL_REVS; 660 661/* 662 * Argument payload for HAL_DIAG_SETKEY. 663 */ 664typedef struct { 665 HAL_KEYVAL dk_keyval; 666 uint16_t dk_keyix; /* key index */ 667 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 668 int dk_xor; /* XOR key data */ 669} HAL_DIAG_KEYVAL; 670 671/* 672 * Argument payload for HAL_DIAG_EEWRITE. 673 */ 674typedef struct { 675 uint16_t ee_off; /* eeprom offset */ 676 uint16_t ee_data; /* write data */ 677} HAL_DIAG_EEVAL; 678 679 680typedef struct { 681 u_int offset; /* reg offset */ 682 uint32_t val; /* reg value */ 683} HAL_DIAG_REGVAL; 684 685/* 686 * 11n compatibility tweaks. 687 */ 688#define HAL_DIAG_11N_SERVICES 0x00000003 689#define HAL_DIAG_11N_SERVICES_S 0 690#define HAL_DIAG_11N_TXSTOMP 0x0000000c 691#define HAL_DIAG_11N_TXSTOMP_S 2 692 693typedef struct { 694 int maxNoiseImmunityLevel; /* [0..4] */ 695 int totalSizeDesired[5]; 696 int coarseHigh[5]; 697 int coarseLow[5]; 698 int firpwr[5]; 699 700 int maxSpurImmunityLevel; /* [0..7] */ 701 int cycPwrThr1[8]; 702 703 int maxFirstepLevel; /* [0..2] */ 704 int firstep[3]; 705 706 uint32_t ofdmTrigHigh; 707 uint32_t ofdmTrigLow; 708 int32_t cckTrigHigh; 709 int32_t cckTrigLow; 710 int32_t rssiThrLow; 711 int32_t rssiThrHigh; 712 713 int period; /* update listen period */ 714} HAL_ANI_PARAMS; 715 716extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 717 const void *args, uint32_t argsize, 718 void **result, uint32_t *resultsize); 719 720/* 721 * Setup a h/w rate table for use. 722 */ 723extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 724 725/* 726 * Common routine for implementing getChanNoise api. 727 */ 728int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 729 730/* 731 * Initialization support. 732 */ 733typedef struct { 734 const uint32_t *data; 735 int rows, cols; 736} HAL_INI_ARRAY; 737 738#define HAL_INI_INIT(_ia, _data, _cols) do { \ 739 (_ia)->data = (const uint32_t *)(_data); \ 740 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 741 (_ia)->cols = (_cols); \ 742} while (0) 743#define HAL_INI_VAL(_ia, _r, _c) \ 744 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 745 746/* 747 * OS_DELAY() does a PIO READ on the PCI bus which allows 748 * other cards' DMA reads to complete in the middle of our reset. 749 */ 750#define DMA_YIELD(x) do { \ 751 if ((++(x) % 64) == 0) \ 752 OS_DELAY(1); \ 753} while (0) 754 755#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 756 int r; \ 757 for (r = 0; r < N(regArray); r++) { \ 758 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 759 DMA_YIELD(regWr); \ 760 } \ 761} while (0) 762 763#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 764 int r; \ 765 for (r = 0; r < N(regArray); r++) { \ 766 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 767 DMA_YIELD(regWr); \ 768 } \ 769} while (0) 770 771extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 772 int col, int regWr); 773extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 774 int col); 775extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 776 const uint32_t data[], int regWr); 777 778#define CCK_SIFS_TIME 10 779#define CCK_PREAMBLE_BITS 144 780#define CCK_PLCP_BITS 48 781 782#define OFDM_SIFS_TIME 16 783#define OFDM_PREAMBLE_TIME 20 784#define OFDM_PLCP_BITS 22 785#define OFDM_SYMBOL_TIME 4 786 787#define OFDM_HALF_SIFS_TIME 32 788#define OFDM_HALF_PREAMBLE_TIME 40 789#define OFDM_HALF_PLCP_BITS 22 790#define OFDM_HALF_SYMBOL_TIME 8 791 792#define OFDM_QUARTER_SIFS_TIME 64 793#define OFDM_QUARTER_PREAMBLE_TIME 80 794#define OFDM_QUARTER_PLCP_BITS 22 795#define OFDM_QUARTER_SYMBOL_TIME 16 796 797#define TURBO_SIFS_TIME 8 798#define TURBO_PREAMBLE_TIME 14 799#define TURBO_PLCP_BITS 22 800#define TURBO_SYMBOL_TIME 4 801 802#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 803 804/* Generic EEPROM board value functions */ 805extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 806 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 807extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 808 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 809 uint8_t *pRetVpdList); 810extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 811 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 812 813/* Whether 5ghz fast clock is needed */ 814/* 815 * The chipset (Merlin, AR9300/later) should set the capability flag below; 816 * this flag simply says that the hardware can do it, not that the EEPROM 817 * says it can. 818 * 819 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 820 * if the relevant eeprom flag is set. 821 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 822 * by default. 823 */ 824#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 825 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 826 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 827 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 828 829 830#endif /* _ATH_AH_INTERAL_H_ */ 831