ah_internal.h revision 227410
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 227410 2011-11-09 22:39:44Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halUseCombinedRadarRssi : 1, 204 halForcePpmSupport : 1, 205 halEnhancedPmSupport : 1, 206 halEnhancedDfsSupport : 1, 207 halMbssidAggrSupport : 1, 208 halBssidMatchSupport : 1, 209 hal4kbSplitTransSupport : 1, 210 halHasRxSelfLinkedTail : 1, 211 halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 212 halHasLongRxDescTsf : 1, 213 halHasBBReadWar : 1, 214 halSerialiseRegWar : 1; 215 uint32_t halWirelessModes; 216 uint16_t halTotalQueues; 217 uint16_t halKeyCacheSize; 218 uint16_t halLow5GhzChan, halHigh5GhzChan; 219 uint16_t halLow2GhzChan, halHigh2GhzChan; 220 int halTstampPrecision; 221 int halRtsAggrLimit; 222 uint8_t halTxChainMask; 223 uint8_t halRxChainMask; 224 uint8_t halNumGpioPins; 225 uint8_t halNumAntCfg2GHz; 226 uint8_t halNumAntCfg5GHz; 227 uint32_t halIntrMask; 228 uint8_t halTxStreams; 229 uint8_t halRxStreams; 230} HAL_CAPABILITIES; 231 232struct regDomain; 233 234/* 235 * The ``private area'' follows immediately after the ``public area'' 236 * in the data structure returned by ath_hal_attach. Private data are 237 * used by device-independent code such as the regulatory domain support. 238 * In general, code within the HAL should never depend on data in the 239 * public area. Instead any public data needed internally should be 240 * shadowed here. 241 * 242 * When declaring a device-specific ath_hal data structure this structure 243 * is assumed to at the front; e.g. 244 * 245 * struct ath_hal_5212 { 246 * struct ath_hal_private ah_priv; 247 * ... 248 * }; 249 * 250 * It might be better to manage the method pointers in this structure 251 * using an indirect pointer to a read-only data structure but this would 252 * disallow class-style method overriding. 253 */ 254struct ath_hal_private { 255 struct ath_hal h; /* public area */ 256 257 /* NB: all methods go first to simplify initialization */ 258 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 259 uint16_t channelFlags, 260 uint16_t *lowChannel, uint16_t *highChannel); 261 u_int (*ah_getWirelessModes)(struct ath_hal*); 262 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 263 uint16_t *data); 264 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 265 uint16_t data); 266 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 267 struct ieee80211_channel *); 268 int16_t (*ah_getNfAdjust)(struct ath_hal *, 269 const HAL_CHANNEL_INTERNAL*); 270 void (*ah_getNoiseFloor)(struct ath_hal *, 271 int16_t nfarray[]); 272 273 void *ah_eeprom; /* opaque EEPROM state */ 274 uint16_t ah_eeversion; /* EEPROM version */ 275 void (*ah_eepromDetach)(struct ath_hal *); 276 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 277 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 278 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 279 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 280 const void *args, uint32_t argsize, 281 void **result, uint32_t *resultsize); 282 283 /* 284 * Device revision information. 285 */ 286 uint16_t ah_devid; /* PCI device ID */ 287 uint16_t ah_subvendorid; /* PCI subvendor ID */ 288 uint32_t ah_macVersion; /* MAC version id */ 289 uint16_t ah_macRev; /* MAC revision */ 290 uint16_t ah_phyRev; /* PHY revision */ 291 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 292 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 293 uint8_t ah_ispcie; /* PCIE, special treatment */ 294 295 HAL_OPMODE ah_opmode; /* operating mode from reset */ 296 const struct ieee80211_channel *ah_curchan;/* operating channel */ 297 HAL_CAPABILITIES ah_caps; /* device capabilities */ 298 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 299 int16_t ah_powerLimit; /* tx power cap */ 300 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 301 u_int ah_tpScale; /* tx power scale factor */ 302 uint32_t ah_11nCompat; /* 11n compat controls */ 303 304 /* 305 * State for regulatory domain handling. 306 */ 307 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 308 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 309 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 310 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 311 u_int ah_nchan; /* valid items in ah_channels */ 312 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 313 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 314 315 uint8_t ah_coverageClass; /* coverage class */ 316 /* 317 * RF Silent handling; setup according to the EEPROM. 318 */ 319 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 320 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 321 /* 322 * Diagnostic support for discriminating HIUERR reports. 323 */ 324 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 325 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 326}; 327 328#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 329 330#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 331 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 332#define ath_hal_getWirelessModes(_ah) \ 333 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 334#define ath_hal_eepromRead(_ah, _off, _data) \ 335 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 336#define ath_hal_eepromWrite(_ah, _off, _data) \ 337 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 338#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 339 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 340#define ath_hal_gpioCfgInput(_ah, _gpio) \ 341 (_ah)->ah_gpioCfgInput(_ah, _gpio) 342#define ath_hal_gpioGet(_ah, _gpio) \ 343 (_ah)->ah_gpioGet(_ah, _gpio) 344#define ath_hal_gpioSet(_ah, _gpio, _val) \ 345 (_ah)->ah_gpioSet(_ah, _gpio, _val) 346#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 347 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 348#define ath_hal_getpowerlimits(_ah, _chan) \ 349 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 350#define ath_hal_getNfAdjust(_ah, _c) \ 351 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 352#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 353 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 354#define ath_hal_configPCIE(_ah, _reset) \ 355 (_ah)->ah_configPCIE(_ah, _reset) 356#define ath_hal_disablePCIE(_ah) \ 357 (_ah)->ah_disablePCIE(_ah) 358#define ath_hal_setInterrupts(_ah, _mask) \ 359 (_ah)->ah_setInterrupts(_ah, _mask) 360 361#define ath_hal_eepromDetach(_ah) do { \ 362 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 363 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 364} while (0) 365#define ath_hal_eepromGet(_ah, _param, _val) \ 366 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 367#define ath_hal_eepromSet(_ah, _param, _val) \ 368 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 369#define ath_hal_eepromGetFlag(_ah, _param) \ 370 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 371#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 372 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 373#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 374 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 375 376#ifndef _NET_IF_IEEE80211_H_ 377/* 378 * Stuff that would naturally come from _ieee80211.h 379 */ 380#define IEEE80211_ADDR_LEN 6 381 382#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 383#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 384#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 385 386#define IEEE80211_CRC_LEN 4 387 388#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 389 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 390#endif /* _NET_IF_IEEE80211_H_ */ 391 392#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 393 394#define INIT_AIFS 2 395#define INIT_CWMIN 15 396#define INIT_CWMIN_11B 31 397#define INIT_CWMAX 1023 398#define INIT_SH_RETRY 10 399#define INIT_LG_RETRY 10 400#define INIT_SSH_RETRY 32 401#define INIT_SLG_RETRY 32 402 403typedef struct { 404 uint32_t tqi_ver; /* HAL TXQ verson */ 405 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 406 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 407 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 408 uint32_t tqi_priority; 409 uint32_t tqi_aifs; /* aifs */ 410 uint32_t tqi_cwmin; /* cwMin */ 411 uint32_t tqi_cwmax; /* cwMax */ 412 uint16_t tqi_shretry; /* frame short retry limit */ 413 uint16_t tqi_lgretry; /* frame long retry limit */ 414 uint32_t tqi_cbrPeriod; 415 uint32_t tqi_cbrOverflowLimit; 416 uint32_t tqi_burstTime; 417 uint32_t tqi_readyTime; 418 uint32_t tqi_physCompBuf; 419 uint32_t tqi_intFlags; /* flags for internal use */ 420} HAL_TX_QUEUE_INFO; 421 422extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 423 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 424extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 425 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 426 427#define HAL_SPUR_VAL_MASK 0x3FFF 428#define HAL_SPUR_CHAN_WIDTH 87 429#define HAL_BIN_WIDTH_BASE_100HZ 3125 430#define HAL_BIN_WIDTH_TURBO_100HZ 6250 431#define HAL_MAX_BINS_ALLOWED 28 432 433#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 434#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 435 436#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 437 438/* 439 * Deduce if the host cpu has big- or litt-endian byte order. 440 */ 441static __inline__ int 442isBigEndian(void) 443{ 444 union { 445 int32_t i; 446 char c[4]; 447 } u; 448 u.i = 1; 449 return (u.c[0] == 0); 450} 451 452/* unalligned little endian access */ 453#define LE_READ_2(p) \ 454 ((uint16_t) \ 455 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 456#define LE_READ_4(p) \ 457 ((uint32_t) \ 458 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 459 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 460 461/* 462 * Register manipulation macros that expect bit field defines 463 * to follow the convention that an _S suffix is appended for 464 * a shift count, while the field mask has no suffix. 465 */ 466#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 467#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 468#define OS_REG_RMW(_a, _r, _set, _clr) \ 469 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 470#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 471 OS_REG_WRITE(_a, _r, \ 472 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 473#define OS_REG_SET_BIT(_a, _r, _f) \ 474 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 475#define OS_REG_CLR_BIT(_a, _r, _f) \ 476 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 477#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 478 ((OS_REG_READ(_a, _r) & (_f)) != 0) 479 480/* Analog register writes may require a delay between each one (eg Merlin?) */ 481#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 482 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 483 484/* wait for the register contents to have the specified value */ 485extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 486 uint32_t mask, uint32_t val); 487extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 488 uint32_t mask, uint32_t val, uint32_t timeout); 489 490/* return the first n bits in val reversed */ 491extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 492 493/* printf interfaces */ 494extern void ath_hal_printf(struct ath_hal *, const char*, ...) 495 __printflike(2,3); 496extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 497 __printflike(2, 0); 498extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 499 500/* allocate and free memory */ 501extern void *ath_hal_malloc(size_t); 502extern void ath_hal_free(void *); 503 504/* common debugging interfaces */ 505#ifdef AH_DEBUG 506#include "ah_debug.h" 507extern int ath_hal_debug; /* Global debug flags */ 508 509/* 510 * The typecast is purely because some callers will pass in 511 * AH_NULL directly rather than using a NULL ath_hal pointer. 512 */ 513#define HALDEBUG(_ah, __m, ...) \ 514 do { \ 515 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 516 ath_hal_debug & (__m) || \ 517 ((_ah) != NULL && \ 518 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 519 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 520 } \ 521 } while(0); 522 523extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 524 __printflike(3,4); 525#else 526#define HALDEBUG(_ah, __m, ...) 527#endif /* AH_DEBUG */ 528 529/* 530 * Register logging definitions shared with ardecode. 531 */ 532#include "ah_decode.h" 533 534/* 535 * Common assertion interface. Note: it is a bad idea to generate 536 * an assertion failure for any recoverable event. Instead catch 537 * the violation and, if possible, fix it up or recover from it; either 538 * with an error return value or a diagnostic messages. System software 539 * does not panic unless the situation is hopeless. 540 */ 541#ifdef AH_ASSERT 542extern void ath_hal_assert_failed(const char* filename, 543 int lineno, const char* msg); 544 545#define HALASSERT(_x) do { \ 546 if (!(_x)) { \ 547 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 548 } \ 549} while (0) 550#else 551#define HALASSERT(_x) 552#endif /* AH_ASSERT */ 553 554/* 555 * Regulatory domain support. 556 */ 557 558/* 559 * Return the max allowed antenna gain and apply any regulatory 560 * domain specific changes. 561 */ 562u_int ath_hal_getantennareduction(struct ath_hal *ah, 563 const struct ieee80211_channel *chan, u_int twiceGain); 564 565/* 566 * Return the test group for the specific channel based on 567 * the current regulatory setup. 568 */ 569u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 570 571/* 572 * Map a public channel definition to the corresponding 573 * internal data structure. This implicitly specifies 574 * whether or not the specified channel is ok to use 575 * based on the current regulatory domain constraints. 576 */ 577#ifndef AH_DEBUG 578static OS_INLINE HAL_CHANNEL_INTERNAL * 579ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 580{ 581 HAL_CHANNEL_INTERNAL *cc; 582 583 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 584 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 585 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 586 return cc; 587} 588#else 589/* NB: non-inline version that checks state */ 590HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 591 const struct ieee80211_channel *); 592#endif /* AH_DEBUG */ 593 594/* 595 * Return the h/w frequency for a channel. This may be 596 * different from ic_freq if this is a GSM device that 597 * takes 2.4GHz frequencies and down-converts them. 598 */ 599static OS_INLINE uint16_t 600ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 601{ 602 return ath_hal_checkchannel(ah, c)->channel; 603} 604 605/* 606 * Convert between microseconds and core system clocks. 607 */ 608extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 609extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 610 611/* 612 * Generic get/set capability support. Each chip overrides 613 * this routine to support chip-specific capabilities. 614 */ 615extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 616 HAL_CAPABILITY_TYPE type, uint32_t capability, 617 uint32_t *result); 618extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 619 HAL_CAPABILITY_TYPE type, uint32_t capability, 620 uint32_t setting, HAL_STATUS *status); 621 622/* The diagnostic codes used to be internally defined here -adrian */ 623#include "ah_diagcodes.h" 624 625enum { 626 HAL_BB_HANG_DFS = 0x0001, 627 HAL_BB_HANG_RIFS = 0x0002, 628 HAL_BB_HANG_RX_CLEAR = 0x0004, 629 HAL_BB_HANG_UNKNOWN = 0x0080, 630 631 HAL_MAC_HANG_SIG1 = 0x0100, 632 HAL_MAC_HANG_SIG2 = 0x0200, 633 HAL_MAC_HANG_UNKNOWN = 0x8000, 634 635 HAL_BB_HANGS = HAL_BB_HANG_DFS 636 | HAL_BB_HANG_RIFS 637 | HAL_BB_HANG_RX_CLEAR 638 | HAL_BB_HANG_UNKNOWN, 639 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 640 | HAL_MAC_HANG_SIG2 641 | HAL_MAC_HANG_UNKNOWN, 642}; 643 644/* 645 * Device revision information. 646 */ 647typedef struct { 648 uint16_t ah_devid; /* PCI device ID */ 649 uint16_t ah_subvendorid; /* PCI subvendor ID */ 650 uint32_t ah_macVersion; /* MAC version id */ 651 uint16_t ah_macRev; /* MAC revision */ 652 uint16_t ah_phyRev; /* PHY revision */ 653 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 654 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 655} HAL_REVS; 656 657/* 658 * Argument payload for HAL_DIAG_SETKEY. 659 */ 660typedef struct { 661 HAL_KEYVAL dk_keyval; 662 uint16_t dk_keyix; /* key index */ 663 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 664 int dk_xor; /* XOR key data */ 665} HAL_DIAG_KEYVAL; 666 667/* 668 * Argument payload for HAL_DIAG_EEWRITE. 669 */ 670typedef struct { 671 uint16_t ee_off; /* eeprom offset */ 672 uint16_t ee_data; /* write data */ 673} HAL_DIAG_EEVAL; 674 675 676typedef struct { 677 u_int offset; /* reg offset */ 678 uint32_t val; /* reg value */ 679} HAL_DIAG_REGVAL; 680 681/* 682 * 11n compatibility tweaks. 683 */ 684#define HAL_DIAG_11N_SERVICES 0x00000003 685#define HAL_DIAG_11N_SERVICES_S 0 686#define HAL_DIAG_11N_TXSTOMP 0x0000000c 687#define HAL_DIAG_11N_TXSTOMP_S 2 688 689typedef struct { 690 int maxNoiseImmunityLevel; /* [0..4] */ 691 int totalSizeDesired[5]; 692 int coarseHigh[5]; 693 int coarseLow[5]; 694 int firpwr[5]; 695 696 int maxSpurImmunityLevel; /* [0..7] */ 697 int cycPwrThr1[8]; 698 699 int maxFirstepLevel; /* [0..2] */ 700 int firstep[3]; 701 702 uint32_t ofdmTrigHigh; 703 uint32_t ofdmTrigLow; 704 int32_t cckTrigHigh; 705 int32_t cckTrigLow; 706 int32_t rssiThrLow; 707 int32_t rssiThrHigh; 708 709 int period; /* update listen period */ 710} HAL_ANI_PARAMS; 711 712extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 713 const void *args, uint32_t argsize, 714 void **result, uint32_t *resultsize); 715 716/* 717 * Setup a h/w rate table for use. 718 */ 719extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 720 721/* 722 * Common routine for implementing getChanNoise api. 723 */ 724int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 725 726/* 727 * Initialization support. 728 */ 729typedef struct { 730 const uint32_t *data; 731 int rows, cols; 732} HAL_INI_ARRAY; 733 734#define HAL_INI_INIT(_ia, _data, _cols) do { \ 735 (_ia)->data = (const uint32_t *)(_data); \ 736 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 737 (_ia)->cols = (_cols); \ 738} while (0) 739#define HAL_INI_VAL(_ia, _r, _c) \ 740 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 741 742/* 743 * OS_DELAY() does a PIO READ on the PCI bus which allows 744 * other cards' DMA reads to complete in the middle of our reset. 745 */ 746#define DMA_YIELD(x) do { \ 747 if ((++(x) % 64) == 0) \ 748 OS_DELAY(1); \ 749} while (0) 750 751#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 752 int r; \ 753 for (r = 0; r < N(regArray); r++) { \ 754 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 755 DMA_YIELD(regWr); \ 756 } \ 757} while (0) 758 759#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 760 int r; \ 761 for (r = 0; r < N(regArray); r++) { \ 762 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 763 DMA_YIELD(regWr); \ 764 } \ 765} while (0) 766 767extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 768 int col, int regWr); 769extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 770 int col); 771extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 772 const uint32_t data[], int regWr); 773 774#define CCK_SIFS_TIME 10 775#define CCK_PREAMBLE_BITS 144 776#define CCK_PLCP_BITS 48 777 778#define OFDM_SIFS_TIME 16 779#define OFDM_PREAMBLE_TIME 20 780#define OFDM_PLCP_BITS 22 781#define OFDM_SYMBOL_TIME 4 782 783#define OFDM_HALF_SIFS_TIME 32 784#define OFDM_HALF_PREAMBLE_TIME 40 785#define OFDM_HALF_PLCP_BITS 22 786#define OFDM_HALF_SYMBOL_TIME 8 787 788#define OFDM_QUARTER_SIFS_TIME 64 789#define OFDM_QUARTER_PREAMBLE_TIME 80 790#define OFDM_QUARTER_PLCP_BITS 22 791#define OFDM_QUARTER_SYMBOL_TIME 16 792 793#define TURBO_SIFS_TIME 8 794#define TURBO_PREAMBLE_TIME 14 795#define TURBO_PLCP_BITS 22 796#define TURBO_SYMBOL_TIME 4 797 798#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 799 800/* Generic EEPROM board value functions */ 801extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 802 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 803extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 804 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 805 uint8_t *pRetVpdList); 806extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 807 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 808 809/* Whether 5ghz fast clock is needed */ 810/* 811 * The chipset (Merlin, AR9300/later) should set the capability flag below; 812 * this flag simply says that the hardware can do it, not that the EEPROM 813 * says it can. 814 * 815 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 816 * if the relevant eeprom flag is set. 817 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 818 * by default. 819 */ 820#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 821 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 822 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 823 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 824 825 826#endif /* _ATH_AH_INTERAL_H_ */ 827