ah_internal.h revision 226488
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 226488 2011-10-18 03:01:41Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halUseCombinedRadarRssi : 1, 204 halForcePpmSupport : 1, 205 halEnhancedPmSupport : 1, 206 halEnhancedDfsSupport : 1, 207 halMbssidAggrSupport : 1, 208 halBssidMatchSupport : 1, 209 hal4kbSplitTransSupport : 1, 210 halHasRxSelfLinkedTail : 1, 211 halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 212 halHasLongRxDescTsf : 1, 213 halHasBBReadWar : 1; 214 uint32_t halWirelessModes; 215 uint16_t halTotalQueues; 216 uint16_t halKeyCacheSize; 217 uint16_t halLow5GhzChan, halHigh5GhzChan; 218 uint16_t halLow2GhzChan, halHigh2GhzChan; 219 int halTstampPrecision; 220 int halRtsAggrLimit; 221 uint8_t halTxChainMask; 222 uint8_t halRxChainMask; 223 uint8_t halNumGpioPins; 224 uint8_t halNumAntCfg2GHz; 225 uint8_t halNumAntCfg5GHz; 226 uint32_t halIntrMask; 227 uint8_t halTxStreams; 228 uint8_t halRxStreams; 229} HAL_CAPABILITIES; 230 231struct regDomain; 232 233/* 234 * The ``private area'' follows immediately after the ``public area'' 235 * in the data structure returned by ath_hal_attach. Private data are 236 * used by device-independent code such as the regulatory domain support. 237 * In general, code within the HAL should never depend on data in the 238 * public area. Instead any public data needed internally should be 239 * shadowed here. 240 * 241 * When declaring a device-specific ath_hal data structure this structure 242 * is assumed to at the front; e.g. 243 * 244 * struct ath_hal_5212 { 245 * struct ath_hal_private ah_priv; 246 * ... 247 * }; 248 * 249 * It might be better to manage the method pointers in this structure 250 * using an indirect pointer to a read-only data structure but this would 251 * disallow class-style method overriding. 252 */ 253struct ath_hal_private { 254 struct ath_hal h; /* public area */ 255 256 /* NB: all methods go first to simplify initialization */ 257 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 258 uint16_t channelFlags, 259 uint16_t *lowChannel, uint16_t *highChannel); 260 u_int (*ah_getWirelessModes)(struct ath_hal*); 261 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 262 uint16_t *data); 263 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 264 uint16_t data); 265 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 266 struct ieee80211_channel *); 267 int16_t (*ah_getNfAdjust)(struct ath_hal *, 268 const HAL_CHANNEL_INTERNAL*); 269 void (*ah_getNoiseFloor)(struct ath_hal *, 270 int16_t nfarray[]); 271 272 void *ah_eeprom; /* opaque EEPROM state */ 273 uint16_t ah_eeversion; /* EEPROM version */ 274 void (*ah_eepromDetach)(struct ath_hal *); 275 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 276 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 277 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 278 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 279 const void *args, uint32_t argsize, 280 void **result, uint32_t *resultsize); 281 282 /* 283 * Device revision information. 284 */ 285 uint16_t ah_devid; /* PCI device ID */ 286 uint16_t ah_subvendorid; /* PCI subvendor ID */ 287 uint32_t ah_macVersion; /* MAC version id */ 288 uint16_t ah_macRev; /* MAC revision */ 289 uint16_t ah_phyRev; /* PHY revision */ 290 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 291 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 292 uint8_t ah_ispcie; /* PCIE, special treatment */ 293 294 HAL_OPMODE ah_opmode; /* operating mode from reset */ 295 const struct ieee80211_channel *ah_curchan;/* operating channel */ 296 HAL_CAPABILITIES ah_caps; /* device capabilities */ 297 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 298 int16_t ah_powerLimit; /* tx power cap */ 299 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 300 u_int ah_tpScale; /* tx power scale factor */ 301 uint32_t ah_11nCompat; /* 11n compat controls */ 302 303 /* 304 * State for regulatory domain handling. 305 */ 306 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 307 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 308 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 309 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 310 u_int ah_nchan; /* valid items in ah_channels */ 311 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 312 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 313 314 uint8_t ah_coverageClass; /* coverage class */ 315 /* 316 * RF Silent handling; setup according to the EEPROM. 317 */ 318 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 319 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 320 /* 321 * Diagnostic support for discriminating HIUERR reports. 322 */ 323 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 324 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 325}; 326 327#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 328 329#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 330 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 331#define ath_hal_getWirelessModes(_ah) \ 332 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 333#define ath_hal_eepromRead(_ah, _off, _data) \ 334 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 335#define ath_hal_eepromWrite(_ah, _off, _data) \ 336 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 337#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 338 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 339#define ath_hal_gpioCfgInput(_ah, _gpio) \ 340 (_ah)->ah_gpioCfgInput(_ah, _gpio) 341#define ath_hal_gpioGet(_ah, _gpio) \ 342 (_ah)->ah_gpioGet(_ah, _gpio) 343#define ath_hal_gpioSet(_ah, _gpio, _val) \ 344 (_ah)->ah_gpioSet(_ah, _gpio, _val) 345#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 346 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 347#define ath_hal_getpowerlimits(_ah, _chan) \ 348 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 349#define ath_hal_getNfAdjust(_ah, _c) \ 350 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 351#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 352 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 353#define ath_hal_configPCIE(_ah, _reset) \ 354 (_ah)->ah_configPCIE(_ah, _reset) 355#define ath_hal_disablePCIE(_ah) \ 356 (_ah)->ah_disablePCIE(_ah) 357#define ath_hal_setInterrupts(_ah, _mask) \ 358 (_ah)->ah_setInterrupts(_ah, _mask) 359 360#define ath_hal_eepromDetach(_ah) do { \ 361 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 362 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 363} while (0) 364#define ath_hal_eepromGet(_ah, _param, _val) \ 365 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 366#define ath_hal_eepromSet(_ah, _param, _val) \ 367 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 368#define ath_hal_eepromGetFlag(_ah, _param) \ 369 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 370#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 371 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 372#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 373 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 374 375#ifndef _NET_IF_IEEE80211_H_ 376/* 377 * Stuff that would naturally come from _ieee80211.h 378 */ 379#define IEEE80211_ADDR_LEN 6 380 381#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 382#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 383#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 384 385#define IEEE80211_CRC_LEN 4 386 387#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 388 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 389#endif /* _NET_IF_IEEE80211_H_ */ 390 391#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 392 393#define INIT_AIFS 2 394#define INIT_CWMIN 15 395#define INIT_CWMIN_11B 31 396#define INIT_CWMAX 1023 397#define INIT_SH_RETRY 10 398#define INIT_LG_RETRY 10 399#define INIT_SSH_RETRY 32 400#define INIT_SLG_RETRY 32 401 402typedef struct { 403 uint32_t tqi_ver; /* HAL TXQ verson */ 404 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 405 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 406 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 407 uint32_t tqi_priority; 408 uint32_t tqi_aifs; /* aifs */ 409 uint32_t tqi_cwmin; /* cwMin */ 410 uint32_t tqi_cwmax; /* cwMax */ 411 uint16_t tqi_shretry; /* frame short retry limit */ 412 uint16_t tqi_lgretry; /* frame long retry limit */ 413 uint32_t tqi_cbrPeriod; 414 uint32_t tqi_cbrOverflowLimit; 415 uint32_t tqi_burstTime; 416 uint32_t tqi_readyTime; 417 uint32_t tqi_physCompBuf; 418 uint32_t tqi_intFlags; /* flags for internal use */ 419} HAL_TX_QUEUE_INFO; 420 421extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 422 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 423extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 424 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 425 426#define HAL_SPUR_VAL_MASK 0x3FFF 427#define HAL_SPUR_CHAN_WIDTH 87 428#define HAL_BIN_WIDTH_BASE_100HZ 3125 429#define HAL_BIN_WIDTH_TURBO_100HZ 6250 430#define HAL_MAX_BINS_ALLOWED 28 431 432#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 433#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 434 435#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 436 437/* 438 * Deduce if the host cpu has big- or litt-endian byte order. 439 */ 440static __inline__ int 441isBigEndian(void) 442{ 443 union { 444 int32_t i; 445 char c[4]; 446 } u; 447 u.i = 1; 448 return (u.c[0] == 0); 449} 450 451/* unalligned little endian access */ 452#define LE_READ_2(p) \ 453 ((uint16_t) \ 454 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 455#define LE_READ_4(p) \ 456 ((uint32_t) \ 457 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 458 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 459 460/* 461 * Register manipulation macros that expect bit field defines 462 * to follow the convention that an _S suffix is appended for 463 * a shift count, while the field mask has no suffix. 464 */ 465#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 466#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 467#define OS_REG_RMW(_a, _r, _set, _clr) \ 468 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 469#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 470 OS_REG_WRITE(_a, _r, \ 471 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 472#define OS_REG_SET_BIT(_a, _r, _f) \ 473 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 474#define OS_REG_CLR_BIT(_a, _r, _f) \ 475 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 476#define OS_REG_IS_BIT_SET(_a, _r, _f) \ 477 ((OS_REG_READ(_a, _r) & (_f)) != 0) 478 479/* Analog register writes may require a delay between each one (eg Merlin?) */ 480#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 481 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 482 483/* wait for the register contents to have the specified value */ 484extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 485 uint32_t mask, uint32_t val); 486extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 487 uint32_t mask, uint32_t val, uint32_t timeout); 488 489/* return the first n bits in val reversed */ 490extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 491 492/* printf interfaces */ 493extern void ath_hal_printf(struct ath_hal *, const char*, ...) 494 __printflike(2,3); 495extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 496 __printflike(2, 0); 497extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 498 499/* allocate and free memory */ 500extern void *ath_hal_malloc(size_t); 501extern void ath_hal_free(void *); 502 503/* common debugging interfaces */ 504#ifdef AH_DEBUG 505#include "ah_debug.h" 506extern int ath_hal_debug; /* Global debug flags */ 507 508/* 509 * The typecast is purely because some callers will pass in 510 * AH_NULL directly rather than using a NULL ath_hal pointer. 511 */ 512#define HALDEBUG(_ah, __m, ...) \ 513 do { \ 514 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 515 ath_hal_debug & (__m) || \ 516 ((_ah) != NULL && \ 517 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \ 518 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 519 } \ 520 } while(0); 521 522extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 523 __printflike(3,4); 524#else 525#define HALDEBUG(_ah, __m, ...) 526#endif /* AH_DEBUG */ 527 528/* 529 * Register logging definitions shared with ardecode. 530 */ 531#include "ah_decode.h" 532 533/* 534 * Common assertion interface. Note: it is a bad idea to generate 535 * an assertion failure for any recoverable event. Instead catch 536 * the violation and, if possible, fix it up or recover from it; either 537 * with an error return value or a diagnostic messages. System software 538 * does not panic unless the situation is hopeless. 539 */ 540#ifdef AH_ASSERT 541extern void ath_hal_assert_failed(const char* filename, 542 int lineno, const char* msg); 543 544#define HALASSERT(_x) do { \ 545 if (!(_x)) { \ 546 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 547 } \ 548} while (0) 549#else 550#define HALASSERT(_x) 551#endif /* AH_ASSERT */ 552 553/* 554 * Regulatory domain support. 555 */ 556 557/* 558 * Return the max allowed antenna gain and apply any regulatory 559 * domain specific changes. 560 */ 561u_int ath_hal_getantennareduction(struct ath_hal *ah, 562 const struct ieee80211_channel *chan, u_int twiceGain); 563 564/* 565 * Return the test group for the specific channel based on 566 * the current regulatory setup. 567 */ 568u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 569 570/* 571 * Map a public channel definition to the corresponding 572 * internal data structure. This implicitly specifies 573 * whether or not the specified channel is ok to use 574 * based on the current regulatory domain constraints. 575 */ 576#ifndef AH_DEBUG 577static OS_INLINE HAL_CHANNEL_INTERNAL * 578ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 579{ 580 HAL_CHANNEL_INTERNAL *cc; 581 582 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 583 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 584 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 585 return cc; 586} 587#else 588/* NB: non-inline version that checks state */ 589HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 590 const struct ieee80211_channel *); 591#endif /* AH_DEBUG */ 592 593/* 594 * Return the h/w frequency for a channel. This may be 595 * different from ic_freq if this is a GSM device that 596 * takes 2.4GHz frequencies and down-converts them. 597 */ 598static OS_INLINE uint16_t 599ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 600{ 601 return ath_hal_checkchannel(ah, c)->channel; 602} 603 604/* 605 * Convert between microseconds and core system clocks. 606 */ 607extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 608extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 609 610/* 611 * Generic get/set capability support. Each chip overrides 612 * this routine to support chip-specific capabilities. 613 */ 614extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 615 HAL_CAPABILITY_TYPE type, uint32_t capability, 616 uint32_t *result); 617extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 618 HAL_CAPABILITY_TYPE type, uint32_t capability, 619 uint32_t setting, HAL_STATUS *status); 620 621/* The diagnostic codes used to be internally defined here -adrian */ 622#include "ah_diagcodes.h" 623 624enum { 625 HAL_BB_HANG_DFS = 0x0001, 626 HAL_BB_HANG_RIFS = 0x0002, 627 HAL_BB_HANG_RX_CLEAR = 0x0004, 628 HAL_BB_HANG_UNKNOWN = 0x0080, 629 630 HAL_MAC_HANG_SIG1 = 0x0100, 631 HAL_MAC_HANG_SIG2 = 0x0200, 632 HAL_MAC_HANG_UNKNOWN = 0x8000, 633 634 HAL_BB_HANGS = HAL_BB_HANG_DFS 635 | HAL_BB_HANG_RIFS 636 | HAL_BB_HANG_RX_CLEAR 637 | HAL_BB_HANG_UNKNOWN, 638 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 639 | HAL_MAC_HANG_SIG2 640 | HAL_MAC_HANG_UNKNOWN, 641}; 642 643/* 644 * Device revision information. 645 */ 646typedef struct { 647 uint16_t ah_devid; /* PCI device ID */ 648 uint16_t ah_subvendorid; /* PCI subvendor ID */ 649 uint32_t ah_macVersion; /* MAC version id */ 650 uint16_t ah_macRev; /* MAC revision */ 651 uint16_t ah_phyRev; /* PHY revision */ 652 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 653 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 654} HAL_REVS; 655 656/* 657 * Argument payload for HAL_DIAG_SETKEY. 658 */ 659typedef struct { 660 HAL_KEYVAL dk_keyval; 661 uint16_t dk_keyix; /* key index */ 662 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 663 int dk_xor; /* XOR key data */ 664} HAL_DIAG_KEYVAL; 665 666/* 667 * Argument payload for HAL_DIAG_EEWRITE. 668 */ 669typedef struct { 670 uint16_t ee_off; /* eeprom offset */ 671 uint16_t ee_data; /* write data */ 672} HAL_DIAG_EEVAL; 673 674 675typedef struct { 676 u_int offset; /* reg offset */ 677 uint32_t val; /* reg value */ 678} HAL_DIAG_REGVAL; 679 680/* 681 * 11n compatibility tweaks. 682 */ 683#define HAL_DIAG_11N_SERVICES 0x00000003 684#define HAL_DIAG_11N_SERVICES_S 0 685#define HAL_DIAG_11N_TXSTOMP 0x0000000c 686#define HAL_DIAG_11N_TXSTOMP_S 2 687 688typedef struct { 689 int maxNoiseImmunityLevel; /* [0..4] */ 690 int totalSizeDesired[5]; 691 int coarseHigh[5]; 692 int coarseLow[5]; 693 int firpwr[5]; 694 695 int maxSpurImmunityLevel; /* [0..7] */ 696 int cycPwrThr1[8]; 697 698 int maxFirstepLevel; /* [0..2] */ 699 int firstep[3]; 700 701 uint32_t ofdmTrigHigh; 702 uint32_t ofdmTrigLow; 703 int32_t cckTrigHigh; 704 int32_t cckTrigLow; 705 int32_t rssiThrLow; 706 int32_t rssiThrHigh; 707 708 int period; /* update listen period */ 709} HAL_ANI_PARAMS; 710 711extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 712 const void *args, uint32_t argsize, 713 void **result, uint32_t *resultsize); 714 715/* 716 * Setup a h/w rate table for use. 717 */ 718extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 719 720/* 721 * Common routine for implementing getChanNoise api. 722 */ 723int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 724 725/* 726 * Initialization support. 727 */ 728typedef struct { 729 const uint32_t *data; 730 int rows, cols; 731} HAL_INI_ARRAY; 732 733#define HAL_INI_INIT(_ia, _data, _cols) do { \ 734 (_ia)->data = (const uint32_t *)(_data); \ 735 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 736 (_ia)->cols = (_cols); \ 737} while (0) 738#define HAL_INI_VAL(_ia, _r, _c) \ 739 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 740 741/* 742 * OS_DELAY() does a PIO READ on the PCI bus which allows 743 * other cards' DMA reads to complete in the middle of our reset. 744 */ 745#define DMA_YIELD(x) do { \ 746 if ((++(x) % 64) == 0) \ 747 OS_DELAY(1); \ 748} while (0) 749 750#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 751 int r; \ 752 for (r = 0; r < N(regArray); r++) { \ 753 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 754 DMA_YIELD(regWr); \ 755 } \ 756} while (0) 757 758#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 759 int r; \ 760 for (r = 0; r < N(regArray); r++) { \ 761 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 762 DMA_YIELD(regWr); \ 763 } \ 764} while (0) 765 766extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 767 int col, int regWr); 768extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 769 int col); 770extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 771 const uint32_t data[], int regWr); 772 773#define CCK_SIFS_TIME 10 774#define CCK_PREAMBLE_BITS 144 775#define CCK_PLCP_BITS 48 776 777#define OFDM_SIFS_TIME 16 778#define OFDM_PREAMBLE_TIME 20 779#define OFDM_PLCP_BITS 22 780#define OFDM_SYMBOL_TIME 4 781 782#define OFDM_HALF_SIFS_TIME 32 783#define OFDM_HALF_PREAMBLE_TIME 40 784#define OFDM_HALF_PLCP_BITS 22 785#define OFDM_HALF_SYMBOL_TIME 8 786 787#define OFDM_QUARTER_SIFS_TIME 64 788#define OFDM_QUARTER_PREAMBLE_TIME 80 789#define OFDM_QUARTER_PLCP_BITS 22 790#define OFDM_QUARTER_SYMBOL_TIME 16 791 792#define TURBO_SIFS_TIME 8 793#define TURBO_PREAMBLE_TIME 14 794#define TURBO_PLCP_BITS 22 795#define TURBO_SYMBOL_TIME 4 796 797#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 798 799/* Generic EEPROM board value functions */ 800extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 801 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 802extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 803 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 804 uint8_t *pRetVpdList); 805extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 806 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 807 808/* Whether 5ghz fast clock is needed */ 809/* 810 * The chipset (Merlin, AR9300/later) should set the capability flag below; 811 * this flag simply says that the hardware can do it, not that the EEPROM 812 * says it can. 813 * 814 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 815 * if the relevant eeprom flag is set. 816 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 817 * by default. 818 */ 819#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 820 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 821 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 822 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 823 824 825#endif /* _ATH_AH_INTERAL_H_ */ 826