ah_internal.h revision 225444
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 225444 2011-09-08 01:23:05Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halUseCombinedRadarRssi : 1, 204 halForcePpmSupport : 1, 205 halEnhancedPmSupport : 1, 206 halEnhancedDfsSupport : 1, 207 halMbssidAggrSupport : 1, 208 halBssidMatchSupport : 1, 209 hal4kbSplitTransSupport : 1, 210 halHasRxSelfLinkedTail : 1, 211 halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 212 halHasLongRxDescTsf : 1; 213 uint32_t halWirelessModes; 214 uint16_t halTotalQueues; 215 uint16_t halKeyCacheSize; 216 uint16_t halLow5GhzChan, halHigh5GhzChan; 217 uint16_t halLow2GhzChan, halHigh2GhzChan; 218 int halTstampPrecision; 219 int halRtsAggrLimit; 220 uint8_t halTxChainMask; 221 uint8_t halRxChainMask; 222 uint8_t halNumGpioPins; 223 uint8_t halNumAntCfg2GHz; 224 uint8_t halNumAntCfg5GHz; 225 uint32_t halIntrMask; 226 uint8_t halTxStreams; 227 uint8_t halRxStreams; 228} HAL_CAPABILITIES; 229 230struct regDomain; 231 232/* 233 * The ``private area'' follows immediately after the ``public area'' 234 * in the data structure returned by ath_hal_attach. Private data are 235 * used by device-independent code such as the regulatory domain support. 236 * In general, code within the HAL should never depend on data in the 237 * public area. Instead any public data needed internally should be 238 * shadowed here. 239 * 240 * When declaring a device-specific ath_hal data structure this structure 241 * is assumed to at the front; e.g. 242 * 243 * struct ath_hal_5212 { 244 * struct ath_hal_private ah_priv; 245 * ... 246 * }; 247 * 248 * It might be better to manage the method pointers in this structure 249 * using an indirect pointer to a read-only data structure but this would 250 * disallow class-style method overriding. 251 */ 252struct ath_hal_private { 253 struct ath_hal h; /* public area */ 254 255 /* NB: all methods go first to simplify initialization */ 256 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 257 uint16_t channelFlags, 258 uint16_t *lowChannel, uint16_t *highChannel); 259 u_int (*ah_getWirelessModes)(struct ath_hal*); 260 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 261 uint16_t *data); 262 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 263 uint16_t data); 264 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 265 struct ieee80211_channel *); 266 int16_t (*ah_getNfAdjust)(struct ath_hal *, 267 const HAL_CHANNEL_INTERNAL*); 268 void (*ah_getNoiseFloor)(struct ath_hal *, 269 int16_t nfarray[]); 270 271 void *ah_eeprom; /* opaque EEPROM state */ 272 uint16_t ah_eeversion; /* EEPROM version */ 273 void (*ah_eepromDetach)(struct ath_hal *); 274 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 275 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 276 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 277 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 278 const void *args, uint32_t argsize, 279 void **result, uint32_t *resultsize); 280 281 /* 282 * Device revision information. 283 */ 284 uint16_t ah_devid; /* PCI device ID */ 285 uint16_t ah_subvendorid; /* PCI subvendor ID */ 286 uint32_t ah_macVersion; /* MAC version id */ 287 uint16_t ah_macRev; /* MAC revision */ 288 uint16_t ah_phyRev; /* PHY revision */ 289 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 290 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 291 uint8_t ah_ispcie; /* PCIE, special treatment */ 292 293 HAL_OPMODE ah_opmode; /* operating mode from reset */ 294 const struct ieee80211_channel *ah_curchan;/* operating channel */ 295 HAL_CAPABILITIES ah_caps; /* device capabilities */ 296 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 297 int16_t ah_powerLimit; /* tx power cap */ 298 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 299 u_int ah_tpScale; /* tx power scale factor */ 300 uint32_t ah_11nCompat; /* 11n compat controls */ 301 302 /* 303 * State for regulatory domain handling. 304 */ 305 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 306 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 307 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */ 308 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 309 u_int ah_nchan; /* valid items in ah_channels */ 310 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 311 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 312 313 uint8_t ah_coverageClass; /* coverage class */ 314 /* 315 * RF Silent handling; setup according to the EEPROM. 316 */ 317 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 318 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 319 /* 320 * Diagnostic support for discriminating HIUERR reports. 321 */ 322 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 323 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 324}; 325 326#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 327 328#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 329 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 330#define ath_hal_getWirelessModes(_ah) \ 331 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 332#define ath_hal_eepromRead(_ah, _off, _data) \ 333 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 334#define ath_hal_eepromWrite(_ah, _off, _data) \ 335 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 336#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 337 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 338#define ath_hal_gpioCfgInput(_ah, _gpio) \ 339 (_ah)->ah_gpioCfgInput(_ah, _gpio) 340#define ath_hal_gpioGet(_ah, _gpio) \ 341 (_ah)->ah_gpioGet(_ah, _gpio) 342#define ath_hal_gpioSet(_ah, _gpio, _val) \ 343 (_ah)->ah_gpioSet(_ah, _gpio, _val) 344#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 345 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 346#define ath_hal_getpowerlimits(_ah, _chan) \ 347 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 348#define ath_hal_getNfAdjust(_ah, _c) \ 349 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 350#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 351 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 352#define ath_hal_configPCIE(_ah, _reset) \ 353 (_ah)->ah_configPCIE(_ah, _reset) 354#define ath_hal_disablePCIE(_ah) \ 355 (_ah)->ah_disablePCIE(_ah) 356#define ath_hal_setInterrupts(_ah, _mask) \ 357 (_ah)->ah_setInterrupts(_ah, _mask) 358 359#define ath_hal_eepromDetach(_ah) do { \ 360 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 361 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 362} while (0) 363#define ath_hal_eepromGet(_ah, _param, _val) \ 364 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 365#define ath_hal_eepromSet(_ah, _param, _val) \ 366 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 367#define ath_hal_eepromGetFlag(_ah, _param) \ 368 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 369#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 370 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 371#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 372 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 373 374#ifndef _NET_IF_IEEE80211_H_ 375/* 376 * Stuff that would naturally come from _ieee80211.h 377 */ 378#define IEEE80211_ADDR_LEN 6 379 380#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 381#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 382#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 383 384#define IEEE80211_CRC_LEN 4 385 386#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 387 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 388#endif /* _NET_IF_IEEE80211_H_ */ 389 390#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 391 392#define INIT_AIFS 2 393#define INIT_CWMIN 15 394#define INIT_CWMIN_11B 31 395#define INIT_CWMAX 1023 396#define INIT_SH_RETRY 10 397#define INIT_LG_RETRY 10 398#define INIT_SSH_RETRY 32 399#define INIT_SLG_RETRY 32 400 401typedef struct { 402 uint32_t tqi_ver; /* HAL TXQ verson */ 403 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 404 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 405 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 406 uint32_t tqi_priority; 407 uint32_t tqi_aifs; /* aifs */ 408 uint32_t tqi_cwmin; /* cwMin */ 409 uint32_t tqi_cwmax; /* cwMax */ 410 uint16_t tqi_shretry; /* frame short retry limit */ 411 uint16_t tqi_lgretry; /* frame long retry limit */ 412 uint32_t tqi_cbrPeriod; 413 uint32_t tqi_cbrOverflowLimit; 414 uint32_t tqi_burstTime; 415 uint32_t tqi_readyTime; 416 uint32_t tqi_physCompBuf; 417 uint32_t tqi_intFlags; /* flags for internal use */ 418} HAL_TX_QUEUE_INFO; 419 420extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 421 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 422extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 423 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 424 425#define HAL_SPUR_VAL_MASK 0x3FFF 426#define HAL_SPUR_CHAN_WIDTH 87 427#define HAL_BIN_WIDTH_BASE_100HZ 3125 428#define HAL_BIN_WIDTH_TURBO_100HZ 6250 429#define HAL_MAX_BINS_ALLOWED 28 430 431#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 432#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 433 434#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 435 436/* 437 * Deduce if the host cpu has big- or litt-endian byte order. 438 */ 439static __inline__ int 440isBigEndian(void) 441{ 442 union { 443 int32_t i; 444 char c[4]; 445 } u; 446 u.i = 1; 447 return (u.c[0] == 0); 448} 449 450/* unalligned little endian access */ 451#define LE_READ_2(p) \ 452 ((uint16_t) \ 453 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 454#define LE_READ_4(p) \ 455 ((uint32_t) \ 456 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 457 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 458 459/* 460 * Register manipulation macros that expect bit field defines 461 * to follow the convention that an _S suffix is appended for 462 * a shift count, while the field mask has no suffix. 463 */ 464#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 465#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 466#define OS_REG_RMW(_a, _r, _set, _clr) \ 467 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 468#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 469 OS_REG_WRITE(_a, _r, \ 470 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 471#define OS_REG_SET_BIT(_a, _r, _f) \ 472 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 473#define OS_REG_CLR_BIT(_a, _r, _f) \ 474 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 475 476/* Analog register writes may require a delay between each one (eg Merlin?) */ 477#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 478 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 479 480/* wait for the register contents to have the specified value */ 481extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 482 uint32_t mask, uint32_t val); 483extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 484 uint32_t mask, uint32_t val, uint32_t timeout); 485 486/* return the first n bits in val reversed */ 487extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 488 489/* printf interfaces */ 490extern void ath_hal_printf(struct ath_hal *, const char*, ...) 491 __printflike(2,3); 492extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 493 __printflike(2, 0); 494extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 495 496/* allocate and free memory */ 497extern void *ath_hal_malloc(size_t); 498extern void ath_hal_free(void *); 499 500/* common debugging interfaces */ 501#ifdef AH_DEBUG 502#include "ah_debug.h" 503extern int ath_hal_debug; /* Global debug flags */ 504 505/* 506 * This is used for global debugging, when ahp doesn't yet have the 507 * related debugging state. For example, during probe/attach. 508 */ 509#define HALDEBUG_G(_ah, __m, ...) \ 510 do { \ 511 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 512 ath_hal_debug & (__m)) { \ 513 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 514 } \ 515 } while (0); 516 517/* 518 * This is used for local debugging, when ahp isn't NULL and 519 * thus may have debug flags set. 520 */ 521#define HALDEBUG(_ah, __m, ...) \ 522 do { \ 523 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 524 ath_hal_debug & (__m) || \ 525 (_ah)->ah_config.ah_debug & (__m)) { \ 526 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 527 } \ 528 } while(0); 529 530extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 531 __printflike(3,4); 532#else 533#define HALDEBUG(_ah, __m, ...) 534#define HALDEBUG_G(_ah, __m, ...) 535#endif /* AH_DEBUG */ 536 537/* 538 * Register logging definitions shared with ardecode. 539 */ 540#include "ah_decode.h" 541 542/* 543 * Common assertion interface. Note: it is a bad idea to generate 544 * an assertion failure for any recoverable event. Instead catch 545 * the violation and, if possible, fix it up or recover from it; either 546 * with an error return value or a diagnostic messages. System software 547 * does not panic unless the situation is hopeless. 548 */ 549#ifdef AH_ASSERT 550extern void ath_hal_assert_failed(const char* filename, 551 int lineno, const char* msg); 552 553#define HALASSERT(_x) do { \ 554 if (!(_x)) { \ 555 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 556 } \ 557} while (0) 558#else 559#define HALASSERT(_x) 560#endif /* AH_ASSERT */ 561 562/* 563 * Regulatory domain support. 564 */ 565 566/* 567 * Return the max allowed antenna gain and apply any regulatory 568 * domain specific changes. 569 */ 570u_int ath_hal_getantennareduction(struct ath_hal *ah, 571 const struct ieee80211_channel *chan, u_int twiceGain); 572 573/* 574 * Return the test group for the specific channel based on 575 * the current regulatory setup. 576 */ 577u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 578 579/* 580 * Map a public channel definition to the corresponding 581 * internal data structure. This implicitly specifies 582 * whether or not the specified channel is ok to use 583 * based on the current regulatory domain constraints. 584 */ 585#ifndef AH_DEBUG 586static OS_INLINE HAL_CHANNEL_INTERNAL * 587ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 588{ 589 HAL_CHANNEL_INTERNAL *cc; 590 591 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 592 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 593 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 594 return cc; 595} 596#else 597/* NB: non-inline version that checks state */ 598HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 599 const struct ieee80211_channel *); 600#endif /* AH_DEBUG */ 601 602/* 603 * Return the h/w frequency for a channel. This may be 604 * different from ic_freq if this is a GSM device that 605 * takes 2.4GHz frequencies and down-converts them. 606 */ 607static OS_INLINE uint16_t 608ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 609{ 610 return ath_hal_checkchannel(ah, c)->channel; 611} 612 613/* 614 * Convert between microseconds and core system clocks. 615 */ 616extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 617extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 618 619/* 620 * Generic get/set capability support. Each chip overrides 621 * this routine to support chip-specific capabilities. 622 */ 623extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 624 HAL_CAPABILITY_TYPE type, uint32_t capability, 625 uint32_t *result); 626extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 627 HAL_CAPABILITY_TYPE type, uint32_t capability, 628 uint32_t setting, HAL_STATUS *status); 629 630/* The diagnostic codes used to be internally defined here -adrian */ 631#include "ah_diagcodes.h" 632 633enum { 634 HAL_BB_HANG_DFS = 0x0001, 635 HAL_BB_HANG_RIFS = 0x0002, 636 HAL_BB_HANG_RX_CLEAR = 0x0004, 637 HAL_BB_HANG_UNKNOWN = 0x0080, 638 639 HAL_MAC_HANG_SIG1 = 0x0100, 640 HAL_MAC_HANG_SIG2 = 0x0200, 641 HAL_MAC_HANG_UNKNOWN = 0x8000, 642 643 HAL_BB_HANGS = HAL_BB_HANG_DFS 644 | HAL_BB_HANG_RIFS 645 | HAL_BB_HANG_RX_CLEAR 646 | HAL_BB_HANG_UNKNOWN, 647 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 648 | HAL_MAC_HANG_SIG2 649 | HAL_MAC_HANG_UNKNOWN, 650}; 651 652/* 653 * Device revision information. 654 */ 655typedef struct { 656 uint16_t ah_devid; /* PCI device ID */ 657 uint16_t ah_subvendorid; /* PCI subvendor ID */ 658 uint32_t ah_macVersion; /* MAC version id */ 659 uint16_t ah_macRev; /* MAC revision */ 660 uint16_t ah_phyRev; /* PHY revision */ 661 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 662 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 663} HAL_REVS; 664 665/* 666 * Argument payload for HAL_DIAG_SETKEY. 667 */ 668typedef struct { 669 HAL_KEYVAL dk_keyval; 670 uint16_t dk_keyix; /* key index */ 671 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 672 int dk_xor; /* XOR key data */ 673} HAL_DIAG_KEYVAL; 674 675/* 676 * Argument payload for HAL_DIAG_EEWRITE. 677 */ 678typedef struct { 679 uint16_t ee_off; /* eeprom offset */ 680 uint16_t ee_data; /* write data */ 681} HAL_DIAG_EEVAL; 682 683 684typedef struct { 685 u_int offset; /* reg offset */ 686 uint32_t val; /* reg value */ 687} HAL_DIAG_REGVAL; 688 689/* 690 * 11n compatibility tweaks. 691 */ 692#define HAL_DIAG_11N_SERVICES 0x00000003 693#define HAL_DIAG_11N_SERVICES_S 0 694#define HAL_DIAG_11N_TXSTOMP 0x0000000c 695#define HAL_DIAG_11N_TXSTOMP_S 2 696 697typedef struct { 698 int maxNoiseImmunityLevel; /* [0..4] */ 699 int totalSizeDesired[5]; 700 int coarseHigh[5]; 701 int coarseLow[5]; 702 int firpwr[5]; 703 704 int maxSpurImmunityLevel; /* [0..7] */ 705 int cycPwrThr1[8]; 706 707 int maxFirstepLevel; /* [0..2] */ 708 int firstep[3]; 709 710 uint32_t ofdmTrigHigh; 711 uint32_t ofdmTrigLow; 712 int32_t cckTrigHigh; 713 int32_t cckTrigLow; 714 int32_t rssiThrLow; 715 int32_t rssiThrHigh; 716 717 int period; /* update listen period */ 718} HAL_ANI_PARAMS; 719 720extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 721 const void *args, uint32_t argsize, 722 void **result, uint32_t *resultsize); 723 724/* 725 * Setup a h/w rate table for use. 726 */ 727extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 728 729/* 730 * Common routine for implementing getChanNoise api. 731 */ 732int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 733 734/* 735 * Initialization support. 736 */ 737typedef struct { 738 const uint32_t *data; 739 int rows, cols; 740} HAL_INI_ARRAY; 741 742#define HAL_INI_INIT(_ia, _data, _cols) do { \ 743 (_ia)->data = (const uint32_t *)(_data); \ 744 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 745 (_ia)->cols = (_cols); \ 746} while (0) 747#define HAL_INI_VAL(_ia, _r, _c) \ 748 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 749 750/* 751 * OS_DELAY() does a PIO READ on the PCI bus which allows 752 * other cards' DMA reads to complete in the middle of our reset. 753 */ 754#define DMA_YIELD(x) do { \ 755 if ((++(x) % 64) == 0) \ 756 OS_DELAY(1); \ 757} while (0) 758 759#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 760 int r; \ 761 for (r = 0; r < N(regArray); r++) { \ 762 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 763 DMA_YIELD(regWr); \ 764 } \ 765} while (0) 766 767#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 768 int r; \ 769 for (r = 0; r < N(regArray); r++) { \ 770 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 771 DMA_YIELD(regWr); \ 772 } \ 773} while (0) 774 775extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 776 int col, int regWr); 777extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 778 int col); 779extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 780 const uint32_t data[], int regWr); 781 782#define CCK_SIFS_TIME 10 783#define CCK_PREAMBLE_BITS 144 784#define CCK_PLCP_BITS 48 785 786#define OFDM_SIFS_TIME 16 787#define OFDM_PREAMBLE_TIME 20 788#define OFDM_PLCP_BITS 22 789#define OFDM_SYMBOL_TIME 4 790 791#define OFDM_HALF_SIFS_TIME 32 792#define OFDM_HALF_PREAMBLE_TIME 40 793#define OFDM_HALF_PLCP_BITS 22 794#define OFDM_HALF_SYMBOL_TIME 8 795 796#define OFDM_QUARTER_SIFS_TIME 64 797#define OFDM_QUARTER_PREAMBLE_TIME 80 798#define OFDM_QUARTER_PLCP_BITS 22 799#define OFDM_QUARTER_SYMBOL_TIME 16 800 801#define TURBO_SIFS_TIME 8 802#define TURBO_PREAMBLE_TIME 14 803#define TURBO_PLCP_BITS 22 804#define TURBO_SYMBOL_TIME 4 805 806#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 807 808/* Generic EEPROM board value functions */ 809extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 810 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 811extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 812 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 813 uint8_t *pRetVpdList); 814extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 815 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 816 817/* Whether 5ghz fast clock is needed */ 818/* 819 * The chipset (Merlin, AR9300/later) should set the capability flag below; 820 * this flag simply says that the hardware can do it, not that the EEPROM 821 * says it can. 822 * 823 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 824 * if the relevant eeprom flag is set. 825 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 826 * by default. 827 */ 828#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 829 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 830 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 831 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 832 833 834#endif /* _ATH_AH_INTERAL_H_ */ 835