ah_internal.h revision 223466
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 223466 2011-06-23 06:55:29Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halUseCombinedRadarRssi : 1, 204 halForcePpmSupport : 1, 205 halEnhancedPmSupport : 1, 206 halEnhancedDfsSupport : 1, 207 halMbssidAggrSupport : 1, 208 halBssidMatchSupport : 1, 209 hal4kbSplitTransSupport : 1, 210 halHasRxSelfLinkedTail : 1, 211 halSupportsFastClock5GHz : 1; /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 212 uint32_t halWirelessModes; 213 uint16_t halTotalQueues; 214 uint16_t halKeyCacheSize; 215 uint16_t halLow5GhzChan, halHigh5GhzChan; 216 uint16_t halLow2GhzChan, halHigh2GhzChan; 217 int halTstampPrecision; 218 int halRtsAggrLimit; 219 uint8_t halTxChainMask; 220 uint8_t halRxChainMask; 221 uint8_t halNumGpioPins; 222 uint8_t halNumAntCfg2GHz; 223 uint8_t halNumAntCfg5GHz; 224 uint32_t halIntrMask; 225 uint8_t halTxStreams; 226 uint8_t halRxStreams; 227} HAL_CAPABILITIES; 228 229struct regDomain; 230 231/* 232 * The ``private area'' follows immediately after the ``public area'' 233 * in the data structure returned by ath_hal_attach. Private data are 234 * used by device-independent code such as the regulatory domain support. 235 * In general, code within the HAL should never depend on data in the 236 * public area. Instead any public data needed internally should be 237 * shadowed here. 238 * 239 * When declaring a device-specific ath_hal data structure this structure 240 * is assumed to at the front; e.g. 241 * 242 * struct ath_hal_5212 { 243 * struct ath_hal_private ah_priv; 244 * ... 245 * }; 246 * 247 * It might be better to manage the method pointers in this structure 248 * using an indirect pointer to a read-only data structure but this would 249 * disallow class-style method overriding. 250 */ 251struct ath_hal_private { 252 struct ath_hal h; /* public area */ 253 254 /* NB: all methods go first to simplify initialization */ 255 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 256 uint16_t channelFlags, 257 uint16_t *lowChannel, uint16_t *highChannel); 258 u_int (*ah_getWirelessModes)(struct ath_hal*); 259 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 260 uint16_t *data); 261 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 262 uint16_t data); 263 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 264 struct ieee80211_channel *); 265 int16_t (*ah_getNfAdjust)(struct ath_hal *, 266 const HAL_CHANNEL_INTERNAL*); 267 void (*ah_getNoiseFloor)(struct ath_hal *, 268 int16_t nfarray[]); 269 270 void *ah_eeprom; /* opaque EEPROM state */ 271 uint16_t ah_eeversion; /* EEPROM version */ 272 void (*ah_eepromDetach)(struct ath_hal *); 273 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 274 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 275 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 276 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 277 const void *args, uint32_t argsize, 278 void **result, uint32_t *resultsize); 279 280 /* 281 * Device revision information. 282 */ 283 uint16_t ah_devid; /* PCI device ID */ 284 uint16_t ah_subvendorid; /* PCI subvendor ID */ 285 uint32_t ah_macVersion; /* MAC version id */ 286 uint16_t ah_macRev; /* MAC revision */ 287 uint16_t ah_phyRev; /* PHY revision */ 288 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 289 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 290 uint8_t ah_ispcie; /* PCIE, special treatment */ 291 292 HAL_OPMODE ah_opmode; /* operating mode from reset */ 293 const struct ieee80211_channel *ah_curchan;/* operating channel */ 294 HAL_CAPABILITIES ah_caps; /* device capabilities */ 295 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 296 int16_t ah_powerLimit; /* tx power cap */ 297 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 298 u_int ah_tpScale; /* tx power scale factor */ 299 uint32_t ah_11nCompat; /* 11n compat controls */ 300 301 /* 302 * State for regulatory domain handling. 303 */ 304 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 305 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 306 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 307 u_int ah_nchan; /* valid items in ah_channels */ 308 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 309 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 310 311 uint8_t ah_coverageClass; /* coverage class */ 312 /* 313 * RF Silent handling; setup according to the EEPROM. 314 */ 315 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 316 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 317 /* 318 * Diagnostic support for discriminating HIUERR reports. 319 */ 320 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 321 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 322}; 323 324#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 325 326#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 327 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 328#define ath_hal_getWirelessModes(_ah) \ 329 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 330#define ath_hal_eepromRead(_ah, _off, _data) \ 331 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 332#define ath_hal_eepromWrite(_ah, _off, _data) \ 333 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 334#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 335 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 336#define ath_hal_gpioCfgInput(_ah, _gpio) \ 337 (_ah)->ah_gpioCfgInput(_ah, _gpio) 338#define ath_hal_gpioGet(_ah, _gpio) \ 339 (_ah)->ah_gpioGet(_ah, _gpio) 340#define ath_hal_gpioSet(_ah, _gpio, _val) \ 341 (_ah)->ah_gpioSet(_ah, _gpio, _val) 342#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 343 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 344#define ath_hal_getpowerlimits(_ah, _chan) \ 345 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 346#define ath_hal_getNfAdjust(_ah, _c) \ 347 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 348#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 349 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 350#define ath_hal_configPCIE(_ah, _reset) \ 351 (_ah)->ah_configPCIE(_ah, _reset) 352#define ath_hal_disablePCIE(_ah) \ 353 (_ah)->ah_disablePCIE(_ah) 354#define ath_hal_setInterrupts(_ah, _mask) \ 355 (_ah)->ah_setInterrupts(_ah, _mask) 356 357#define ath_hal_eepromDetach(_ah) do { \ 358 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 359 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 360} while (0) 361#define ath_hal_eepromGet(_ah, _param, _val) \ 362 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 363#define ath_hal_eepromSet(_ah, _param, _val) \ 364 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 365#define ath_hal_eepromGetFlag(_ah, _param) \ 366 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 367#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 368 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 369#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 370 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 371 372#ifndef _NET_IF_IEEE80211_H_ 373/* 374 * Stuff that would naturally come from _ieee80211.h 375 */ 376#define IEEE80211_ADDR_LEN 6 377 378#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 379#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 380#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 381 382#define IEEE80211_CRC_LEN 4 383 384#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 385 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 386#endif /* _NET_IF_IEEE80211_H_ */ 387 388#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 389 390#define INIT_AIFS 2 391#define INIT_CWMIN 15 392#define INIT_CWMIN_11B 31 393#define INIT_CWMAX 1023 394#define INIT_SH_RETRY 10 395#define INIT_LG_RETRY 10 396#define INIT_SSH_RETRY 32 397#define INIT_SLG_RETRY 32 398 399typedef struct { 400 uint32_t tqi_ver; /* HAL TXQ verson */ 401 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 402 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 403 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 404 uint32_t tqi_priority; 405 uint32_t tqi_aifs; /* aifs */ 406 uint32_t tqi_cwmin; /* cwMin */ 407 uint32_t tqi_cwmax; /* cwMax */ 408 uint16_t tqi_shretry; /* frame short retry limit */ 409 uint16_t tqi_lgretry; /* frame long retry limit */ 410 uint32_t tqi_cbrPeriod; 411 uint32_t tqi_cbrOverflowLimit; 412 uint32_t tqi_burstTime; 413 uint32_t tqi_readyTime; 414 uint32_t tqi_physCompBuf; 415 uint32_t tqi_intFlags; /* flags for internal use */ 416} HAL_TX_QUEUE_INFO; 417 418extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 419 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 420extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 421 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 422 423#define HAL_SPUR_VAL_MASK 0x3FFF 424#define HAL_SPUR_CHAN_WIDTH 87 425#define HAL_BIN_WIDTH_BASE_100HZ 3125 426#define HAL_BIN_WIDTH_TURBO_100HZ 6250 427#define HAL_MAX_BINS_ALLOWED 28 428 429#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 430#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 431 432#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 433 434/* 435 * Deduce if the host cpu has big- or litt-endian byte order. 436 */ 437static __inline__ int 438isBigEndian(void) 439{ 440 union { 441 int32_t i; 442 char c[4]; 443 } u; 444 u.i = 1; 445 return (u.c[0] == 0); 446} 447 448/* unalligned little endian access */ 449#define LE_READ_2(p) \ 450 ((uint16_t) \ 451 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 452#define LE_READ_4(p) \ 453 ((uint32_t) \ 454 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 455 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 456 457/* 458 * Register manipulation macros that expect bit field defines 459 * to follow the convention that an _S suffix is appended for 460 * a shift count, while the field mask has no suffix. 461 */ 462#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 463#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 464#define OS_REG_RMW(_a, _r, _set, _clr) \ 465 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 466#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 467 OS_REG_WRITE(_a, _r, \ 468 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 469#define OS_REG_SET_BIT(_a, _r, _f) \ 470 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 471#define OS_REG_CLR_BIT(_a, _r, _f) \ 472 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 473 474/* Analog register writes may require a delay between each one (eg Merlin?) */ 475#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 476 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 477 478/* wait for the register contents to have the specified value */ 479extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 480 uint32_t mask, uint32_t val); 481extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 482 uint32_t mask, uint32_t val, uint32_t timeout); 483 484/* return the first n bits in val reversed */ 485extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 486 487/* printf interfaces */ 488extern void ath_hal_printf(struct ath_hal *, const char*, ...) 489 __printflike(2,3); 490extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 491 __printflike(2, 0); 492extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 493 494/* allocate and free memory */ 495extern void *ath_hal_malloc(size_t); 496extern void ath_hal_free(void *); 497 498/* common debugging interfaces */ 499#ifdef AH_DEBUG 500#include "ah_debug.h" 501extern int ath_hal_debug; /* Global debug flags */ 502 503/* 504 * This is used for global debugging, when ahp doesn't yet have the 505 * related debugging state. For example, during probe/attach. 506 */ 507#define HALDEBUG_G(_ah, __m, ...) \ 508 do { \ 509 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 510 ath_hal_debug & (__m)) { \ 511 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 512 } \ 513 } while (0); 514 515/* 516 * This is used for local debugging, when ahp isn't NULL and 517 * thus may have debug flags set. 518 */ 519#define HALDEBUG(_ah, __m, ...) \ 520 do { \ 521 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 522 ath_hal_debug & (__m) || \ 523 (_ah)->ah_config.ah_debug & (__m)) { \ 524 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 525 } \ 526 } while(0); 527 528extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 529 __printflike(3,4); 530#else 531#define HALDEBUG(_ah, __m, _fmt, ...) 532#endif /* AH_DEBUG */ 533 534/* 535 * Register logging definitions shared with ardecode. 536 */ 537#include "ah_decode.h" 538 539/* 540 * Common assertion interface. Note: it is a bad idea to generate 541 * an assertion failure for any recoverable event. Instead catch 542 * the violation and, if possible, fix it up or recover from it; either 543 * with an error return value or a diagnostic messages. System software 544 * does not panic unless the situation is hopeless. 545 */ 546#ifdef AH_ASSERT 547extern void ath_hal_assert_failed(const char* filename, 548 int lineno, const char* msg); 549 550#define HALASSERT(_x) do { \ 551 if (!(_x)) { \ 552 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 553 } \ 554} while (0) 555#else 556#define HALASSERT(_x) 557#endif /* AH_ASSERT */ 558 559/* 560 * Regulatory domain support. 561 */ 562 563/* 564 * Return the max allowed antenna gain and apply any regulatory 565 * domain specific changes. 566 */ 567u_int ath_hal_getantennareduction(struct ath_hal *ah, 568 const struct ieee80211_channel *chan, u_int twiceGain); 569 570/* 571 * Return the test group for the specific channel based on 572 * the current regulatory setup. 573 */ 574u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 575 576/* 577 * Map a public channel definition to the corresponding 578 * internal data structure. This implicitly specifies 579 * whether or not the specified channel is ok to use 580 * based on the current regulatory domain constraints. 581 */ 582#ifndef AH_DEBUG 583static OS_INLINE HAL_CHANNEL_INTERNAL * 584ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 585{ 586 HAL_CHANNEL_INTERNAL *cc; 587 588 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 589 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 590 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 591 return cc; 592} 593#else 594/* NB: non-inline version that checks state */ 595HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 596 const struct ieee80211_channel *); 597#endif /* AH_DEBUG */ 598 599/* 600 * Return the h/w frequency for a channel. This may be 601 * different from ic_freq if this is a GSM device that 602 * takes 2.4GHz frequencies and down-converts them. 603 */ 604static OS_INLINE uint16_t 605ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 606{ 607 return ath_hal_checkchannel(ah, c)->channel; 608} 609 610/* 611 * Convert between microseconds and core system clocks. 612 */ 613extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 614extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 615 616/* 617 * Generic get/set capability support. Each chip overrides 618 * this routine to support chip-specific capabilities. 619 */ 620extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 621 HAL_CAPABILITY_TYPE type, uint32_t capability, 622 uint32_t *result); 623extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 624 HAL_CAPABILITY_TYPE type, uint32_t capability, 625 uint32_t setting, HAL_STATUS *status); 626 627/* The diagnostic codes used to be internally defined here -adrian */ 628#include "ah_diagcodes.h" 629 630enum { 631 HAL_BB_HANG_DFS = 0x0001, 632 HAL_BB_HANG_RIFS = 0x0002, 633 HAL_BB_HANG_RX_CLEAR = 0x0004, 634 HAL_BB_HANG_UNKNOWN = 0x0080, 635 636 HAL_MAC_HANG_SIG1 = 0x0100, 637 HAL_MAC_HANG_SIG2 = 0x0200, 638 HAL_MAC_HANG_UNKNOWN = 0x8000, 639 640 HAL_BB_HANGS = HAL_BB_HANG_DFS 641 | HAL_BB_HANG_RIFS 642 | HAL_BB_HANG_RX_CLEAR 643 | HAL_BB_HANG_UNKNOWN, 644 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 645 | HAL_MAC_HANG_SIG2 646 | HAL_MAC_HANG_UNKNOWN, 647}; 648 649/* 650 * Device revision information. 651 */ 652typedef struct { 653 uint16_t ah_devid; /* PCI device ID */ 654 uint16_t ah_subvendorid; /* PCI subvendor ID */ 655 uint32_t ah_macVersion; /* MAC version id */ 656 uint16_t ah_macRev; /* MAC revision */ 657 uint16_t ah_phyRev; /* PHY revision */ 658 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 659 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 660} HAL_REVS; 661 662/* 663 * Argument payload for HAL_DIAG_SETKEY. 664 */ 665typedef struct { 666 HAL_KEYVAL dk_keyval; 667 uint16_t dk_keyix; /* key index */ 668 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 669 int dk_xor; /* XOR key data */ 670} HAL_DIAG_KEYVAL; 671 672/* 673 * Argument payload for HAL_DIAG_EEWRITE. 674 */ 675typedef struct { 676 uint16_t ee_off; /* eeprom offset */ 677 uint16_t ee_data; /* write data */ 678} HAL_DIAG_EEVAL; 679 680 681typedef struct { 682 u_int offset; /* reg offset */ 683 uint32_t val; /* reg value */ 684} HAL_DIAG_REGVAL; 685 686/* 687 * 11n compatibility tweaks. 688 */ 689#define HAL_DIAG_11N_SERVICES 0x00000003 690#define HAL_DIAG_11N_SERVICES_S 0 691#define HAL_DIAG_11N_TXSTOMP 0x0000000c 692#define HAL_DIAG_11N_TXSTOMP_S 2 693 694typedef struct { 695 int maxNoiseImmunityLevel; /* [0..4] */ 696 int totalSizeDesired[5]; 697 int coarseHigh[5]; 698 int coarseLow[5]; 699 int firpwr[5]; 700 701 int maxSpurImmunityLevel; /* [0..7] */ 702 int cycPwrThr1[8]; 703 704 int maxFirstepLevel; /* [0..2] */ 705 int firstep[3]; 706 707 uint32_t ofdmTrigHigh; 708 uint32_t ofdmTrigLow; 709 int32_t cckTrigHigh; 710 int32_t cckTrigLow; 711 int32_t rssiThrLow; 712 int32_t rssiThrHigh; 713 714 int period; /* update listen period */ 715} HAL_ANI_PARAMS; 716 717extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 718 const void *args, uint32_t argsize, 719 void **result, uint32_t *resultsize); 720 721/* 722 * Setup a h/w rate table for use. 723 */ 724extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 725 726/* 727 * Common routine for implementing getChanNoise api. 728 */ 729int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 730 731/* 732 * Initialization support. 733 */ 734typedef struct { 735 const uint32_t *data; 736 int rows, cols; 737} HAL_INI_ARRAY; 738 739#define HAL_INI_INIT(_ia, _data, _cols) do { \ 740 (_ia)->data = (const uint32_t *)(_data); \ 741 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 742 (_ia)->cols = (_cols); \ 743} while (0) 744#define HAL_INI_VAL(_ia, _r, _c) \ 745 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 746 747/* 748 * OS_DELAY() does a PIO READ on the PCI bus which allows 749 * other cards' DMA reads to complete in the middle of our reset. 750 */ 751#define DMA_YIELD(x) do { \ 752 if ((++(x) % 64) == 0) \ 753 OS_DELAY(1); \ 754} while (0) 755 756#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 757 int r; \ 758 for (r = 0; r < N(regArray); r++) { \ 759 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 760 DMA_YIELD(regWr); \ 761 } \ 762} while (0) 763 764#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 765 int r; \ 766 for (r = 0; r < N(regArray); r++) { \ 767 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 768 DMA_YIELD(regWr); \ 769 } \ 770} while (0) 771 772extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 773 int col, int regWr); 774extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 775 int col); 776extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 777 const uint32_t data[], int regWr); 778 779#define CCK_SIFS_TIME 10 780#define CCK_PREAMBLE_BITS 144 781#define CCK_PLCP_BITS 48 782 783#define OFDM_SIFS_TIME 16 784#define OFDM_PREAMBLE_TIME 20 785#define OFDM_PLCP_BITS 22 786#define OFDM_SYMBOL_TIME 4 787 788#define OFDM_HALF_SIFS_TIME 32 789#define OFDM_HALF_PREAMBLE_TIME 40 790#define OFDM_HALF_PLCP_BITS 22 791#define OFDM_HALF_SYMBOL_TIME 8 792 793#define OFDM_QUARTER_SIFS_TIME 64 794#define OFDM_QUARTER_PREAMBLE_TIME 80 795#define OFDM_QUARTER_PLCP_BITS 22 796#define OFDM_QUARTER_SYMBOL_TIME 16 797 798#define TURBO_SIFS_TIME 8 799#define TURBO_PREAMBLE_TIME 14 800#define TURBO_PLCP_BITS 22 801#define TURBO_SYMBOL_TIME 4 802 803#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 804 805/* Generic EEPROM board value functions */ 806extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 807 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 808extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 809 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 810 uint8_t *pRetVpdList); 811extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 812 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 813 814/* Whether 5ghz fast clock is needed */ 815/* 816 * The chipset (Merlin, AR9300/later) should set the capability flag below; 817 * this flag simply says that the hardware can do it, not that the EEPROM 818 * says it can. 819 * 820 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 821 * if the relevant eeprom flag is set. 822 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 823 * by default. 824 */ 825#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 826 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 827 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 828 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 829 830 831#endif /* _ATH_AH_INTERAL_H_ */ 832