ah_internal.h revision 222277
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 222277 2011-05-25 07:34:49Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halForcePpmSupport : 1, 204 halEnhancedPmSupport : 1, 205 halMbssidAggrSupport : 1, 206 halBssidMatchSupport : 1, 207 hal4kbSplitTransSupport : 1, 208 halHasRxSelfLinkedTail : 1, 209 halSupportsFastClock5GHz : 1; /* Hardware supports 5ghz fast clock; check eeprom/channel before using */ 210 uint32_t halWirelessModes; 211 uint16_t halTotalQueues; 212 uint16_t halKeyCacheSize; 213 uint16_t halLow5GhzChan, halHigh5GhzChan; 214 uint16_t halLow2GhzChan, halHigh2GhzChan; 215 int halTstampPrecision; 216 int halRtsAggrLimit; 217 uint8_t halTxChainMask; 218 uint8_t halRxChainMask; 219 uint8_t halNumGpioPins; 220 uint8_t halNumAntCfg2GHz; 221 uint8_t halNumAntCfg5GHz; 222 uint32_t halIntrMask; 223 uint8_t halTxStreams; 224 uint8_t halRxStreams; 225} HAL_CAPABILITIES; 226 227struct regDomain; 228 229/* 230 * The ``private area'' follows immediately after the ``public area'' 231 * in the data structure returned by ath_hal_attach. Private data are 232 * used by device-independent code such as the regulatory domain support. 233 * In general, code within the HAL should never depend on data in the 234 * public area. Instead any public data needed internally should be 235 * shadowed here. 236 * 237 * When declaring a device-specific ath_hal data structure this structure 238 * is assumed to at the front; e.g. 239 * 240 * struct ath_hal_5212 { 241 * struct ath_hal_private ah_priv; 242 * ... 243 * }; 244 * 245 * It might be better to manage the method pointers in this structure 246 * using an indirect pointer to a read-only data structure but this would 247 * disallow class-style method overriding. 248 */ 249struct ath_hal_private { 250 struct ath_hal h; /* public area */ 251 252 /* NB: all methods go first to simplify initialization */ 253 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 254 uint16_t channelFlags, 255 uint16_t *lowChannel, uint16_t *highChannel); 256 u_int (*ah_getWirelessModes)(struct ath_hal*); 257 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 258 uint16_t *data); 259 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 260 uint16_t data); 261 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 262 struct ieee80211_channel *); 263 int16_t (*ah_getNfAdjust)(struct ath_hal *, 264 const HAL_CHANNEL_INTERNAL*); 265 void (*ah_getNoiseFloor)(struct ath_hal *, 266 int16_t nfarray[]); 267 268 void *ah_eeprom; /* opaque EEPROM state */ 269 uint16_t ah_eeversion; /* EEPROM version */ 270 void (*ah_eepromDetach)(struct ath_hal *); 271 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 272 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int); 273 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 274 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 275 const void *args, uint32_t argsize, 276 void **result, uint32_t *resultsize); 277 278 /* 279 * Device revision information. 280 */ 281 uint16_t ah_devid; /* PCI device ID */ 282 uint16_t ah_subvendorid; /* PCI subvendor ID */ 283 uint32_t ah_macVersion; /* MAC version id */ 284 uint16_t ah_macRev; /* MAC revision */ 285 uint16_t ah_phyRev; /* PHY revision */ 286 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 287 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 288 uint8_t ah_ispcie; /* PCIE, special treatment */ 289 290 HAL_OPMODE ah_opmode; /* operating mode from reset */ 291 const struct ieee80211_channel *ah_curchan;/* operating channel */ 292 HAL_CAPABILITIES ah_caps; /* device capabilities */ 293 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 294 int16_t ah_powerLimit; /* tx power cap */ 295 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 296 u_int ah_tpScale; /* tx power scale factor */ 297 uint32_t ah_11nCompat; /* 11n compat controls */ 298 299 /* 300 * State for regulatory domain handling. 301 */ 302 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 303 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 304 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 305 u_int ah_nchan; /* valid items in ah_channels */ 306 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 307 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 308 309 uint8_t ah_coverageClass; /* coverage class */ 310 /* 311 * RF Silent handling; setup according to the EEPROM. 312 */ 313 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 314 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 315 /* 316 * Diagnostic support for discriminating HIUERR reports. 317 */ 318 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 319 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 320}; 321 322#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 323 324#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 325 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 326#define ath_hal_getWirelessModes(_ah) \ 327 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 328#define ath_hal_eepromRead(_ah, _off, _data) \ 329 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 330#define ath_hal_eepromWrite(_ah, _off, _data) \ 331 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 332#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 333 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 334#define ath_hal_gpioCfgInput(_ah, _gpio) \ 335 (_ah)->ah_gpioCfgInput(_ah, _gpio) 336#define ath_hal_gpioGet(_ah, _gpio) \ 337 (_ah)->ah_gpioGet(_ah, _gpio) 338#define ath_hal_gpioSet(_ah, _gpio, _val) \ 339 (_ah)->ah_gpioSet(_ah, _gpio, _val) 340#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 341 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 342#define ath_hal_getpowerlimits(_ah, _chan) \ 343 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 344#define ath_hal_getNfAdjust(_ah, _c) \ 345 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 346#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 347 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 348#define ath_hal_configPCIE(_ah, _reset) \ 349 (_ah)->ah_configPCIE(_ah, _reset) 350#define ath_hal_disablePCIE(_ah) \ 351 (_ah)->ah_disablePCIE(_ah) 352#define ath_hal_setInterrupts(_ah, _mask) \ 353 (_ah)->ah_setInterrupts(_ah, _mask) 354 355#define ath_hal_eepromDetach(_ah) do { \ 356 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 357 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 358} while (0) 359#define ath_hal_eepromGet(_ah, _param, _val) \ 360 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 361#define ath_hal_eepromSet(_ah, _param, _val) \ 362 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 363#define ath_hal_eepromGetFlag(_ah, _param) \ 364 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 365#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 366 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 367#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 368 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 369 370#ifndef _NET_IF_IEEE80211_H_ 371/* 372 * Stuff that would naturally come from _ieee80211.h 373 */ 374#define IEEE80211_ADDR_LEN 6 375 376#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 377#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 378#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 379 380#define IEEE80211_CRC_LEN 4 381 382#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 383 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 384#endif /* _NET_IF_IEEE80211_H_ */ 385 386#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 387 388#define INIT_AIFS 2 389#define INIT_CWMIN 15 390#define INIT_CWMIN_11B 31 391#define INIT_CWMAX 1023 392#define INIT_SH_RETRY 10 393#define INIT_LG_RETRY 10 394#define INIT_SSH_RETRY 32 395#define INIT_SLG_RETRY 32 396 397typedef struct { 398 uint32_t tqi_ver; /* HAL TXQ verson */ 399 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 400 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 401 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 402 uint32_t tqi_priority; 403 uint32_t tqi_aifs; /* aifs */ 404 uint32_t tqi_cwmin; /* cwMin */ 405 uint32_t tqi_cwmax; /* cwMax */ 406 uint16_t tqi_shretry; /* frame short retry limit */ 407 uint16_t tqi_lgretry; /* frame long retry limit */ 408 uint32_t tqi_cbrPeriod; 409 uint32_t tqi_cbrOverflowLimit; 410 uint32_t tqi_burstTime; 411 uint32_t tqi_readyTime; 412 uint32_t tqi_physCompBuf; 413 uint32_t tqi_intFlags; /* flags for internal use */ 414} HAL_TX_QUEUE_INFO; 415 416extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 417 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 418extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 419 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 420 421#define HAL_SPUR_VAL_MASK 0x3FFF 422#define HAL_SPUR_CHAN_WIDTH 87 423#define HAL_BIN_WIDTH_BASE_100HZ 3125 424#define HAL_BIN_WIDTH_TURBO_100HZ 6250 425#define HAL_MAX_BINS_ALLOWED 28 426 427#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 428#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 429 430#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 431 432/* 433 * Deduce if the host cpu has big- or litt-endian byte order. 434 */ 435static __inline__ int 436isBigEndian(void) 437{ 438 union { 439 int32_t i; 440 char c[4]; 441 } u; 442 u.i = 1; 443 return (u.c[0] == 0); 444} 445 446/* unalligned little endian access */ 447#define LE_READ_2(p) \ 448 ((uint16_t) \ 449 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 450#define LE_READ_4(p) \ 451 ((uint32_t) \ 452 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 453 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 454 455/* 456 * Register manipulation macros that expect bit field defines 457 * to follow the convention that an _S suffix is appended for 458 * a shift count, while the field mask has no suffix. 459 */ 460#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 461#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 462#define OS_REG_RMW(_a, _r, _set, _clr) \ 463 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 464#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 465 OS_REG_WRITE(_a, _r, \ 466 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 467#define OS_REG_SET_BIT(_a, _r, _f) \ 468 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 469#define OS_REG_CLR_BIT(_a, _r, _f) \ 470 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 471 472/* Analog register writes may require a delay between each one (eg Merlin?) */ 473#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 474 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 475 476/* system-configurable parameters */ 477extern int ath_hal_dma_beacon_response_time; /* in TU's */ 478extern int ath_hal_sw_beacon_response_time; /* in TU's */ 479extern int ath_hal_additional_swba_backoff; /* in TU's */ 480extern int ath_hal_ar5416_biasadj; /* 1 or 0 */ 481 482/* wait for the register contents to have the specified value */ 483extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 484 uint32_t mask, uint32_t val); 485extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 486 uint32_t mask, uint32_t val, uint32_t timeout); 487 488/* return the first n bits in val reversed */ 489extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 490 491/* printf interfaces */ 492extern void ath_hal_printf(struct ath_hal *, const char*, ...) 493 __printflike(2,3); 494extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 495 __printflike(2, 0); 496extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 497 498/* allocate and free memory */ 499extern void *ath_hal_malloc(size_t); 500extern void ath_hal_free(void *); 501 502/* common debugging interfaces */ 503#ifdef AH_DEBUG 504#include "ah_debug.h" 505extern int ath_hal_debug; 506#define HALDEBUG(_ah, __m, ...) \ 507 do { \ 508 if ((__m) == HAL_DEBUG_UNMASKABLE || \ 509 (ath_hal_debug & (__m))) { \ 510 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 511 } \ 512 } while(0); 513 514extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 515 __printflike(3,4); 516#else 517#define HALDEBUG(_ah, __m, _fmt, ...) 518#endif /* AH_DEBUG */ 519 520/* 521 * Register logging definitions shared with ardecode. 522 */ 523#include "ah_decode.h" 524 525/* 526 * Common assertion interface. Note: it is a bad idea to generate 527 * an assertion failure for any recoverable event. Instead catch 528 * the violation and, if possible, fix it up or recover from it; either 529 * with an error return value or a diagnostic messages. System software 530 * does not panic unless the situation is hopeless. 531 */ 532#ifdef AH_ASSERT 533extern void ath_hal_assert_failed(const char* filename, 534 int lineno, const char* msg); 535 536#define HALASSERT(_x) do { \ 537 if (!(_x)) { \ 538 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 539 } \ 540} while (0) 541#else 542#define HALASSERT(_x) 543#endif /* AH_ASSERT */ 544 545/* 546 * Regulatory domain support. 547 */ 548 549/* 550 * Return the max allowed antenna gain and apply any regulatory 551 * domain specific changes. 552 */ 553u_int ath_hal_getantennareduction(struct ath_hal *ah, 554 const struct ieee80211_channel *chan, u_int twiceGain); 555 556/* 557 * Return the test group for the specific channel based on 558 * the current regulatory setup. 559 */ 560u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 561 562/* 563 * Map a public channel definition to the corresponding 564 * internal data structure. This implicitly specifies 565 * whether or not the specified channel is ok to use 566 * based on the current regulatory domain constraints. 567 */ 568#ifndef AH_DEBUG 569static OS_INLINE HAL_CHANNEL_INTERNAL * 570ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 571{ 572 HAL_CHANNEL_INTERNAL *cc; 573 574 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 575 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 576 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 577 return cc; 578} 579#else 580/* NB: non-inline version that checks state */ 581HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 582 const struct ieee80211_channel *); 583#endif /* AH_DEBUG */ 584 585/* 586 * Return the h/w frequency for a channel. This may be 587 * different from ic_freq if this is a GSM device that 588 * takes 2.4GHz frequencies and down-converts them. 589 */ 590static OS_INLINE uint16_t 591ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 592{ 593 return ath_hal_checkchannel(ah, c)->channel; 594} 595 596/* 597 * Convert between microseconds and core system clocks. 598 */ 599extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 600extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 601 602/* 603 * Generic get/set capability support. Each chip overrides 604 * this routine to support chip-specific capabilities. 605 */ 606extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 607 HAL_CAPABILITY_TYPE type, uint32_t capability, 608 uint32_t *result); 609extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 610 HAL_CAPABILITY_TYPE type, uint32_t capability, 611 uint32_t setting, HAL_STATUS *status); 612 613/* The diagnostic codes used to be internally defined here -adrian */ 614#include "ah_diagcodes.h" 615 616enum { 617 HAL_BB_HANG_DFS = 0x0001, 618 HAL_BB_HANG_RIFS = 0x0002, 619 HAL_BB_HANG_RX_CLEAR = 0x0004, 620 HAL_BB_HANG_UNKNOWN = 0x0080, 621 622 HAL_MAC_HANG_SIG1 = 0x0100, 623 HAL_MAC_HANG_SIG2 = 0x0200, 624 HAL_MAC_HANG_UNKNOWN = 0x8000, 625 626 HAL_BB_HANGS = HAL_BB_HANG_DFS 627 | HAL_BB_HANG_RIFS 628 | HAL_BB_HANG_RX_CLEAR 629 | HAL_BB_HANG_UNKNOWN, 630 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 631 | HAL_MAC_HANG_SIG2 632 | HAL_MAC_HANG_UNKNOWN, 633}; 634 635/* 636 * Device revision information. 637 */ 638typedef struct { 639 uint16_t ah_devid; /* PCI device ID */ 640 uint16_t ah_subvendorid; /* PCI subvendor ID */ 641 uint32_t ah_macVersion; /* MAC version id */ 642 uint16_t ah_macRev; /* MAC revision */ 643 uint16_t ah_phyRev; /* PHY revision */ 644 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 645 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 646} HAL_REVS; 647 648/* 649 * Argument payload for HAL_DIAG_SETKEY. 650 */ 651typedef struct { 652 HAL_KEYVAL dk_keyval; 653 uint16_t dk_keyix; /* key index */ 654 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 655 int dk_xor; /* XOR key data */ 656} HAL_DIAG_KEYVAL; 657 658/* 659 * Argument payload for HAL_DIAG_EEWRITE. 660 */ 661typedef struct { 662 uint16_t ee_off; /* eeprom offset */ 663 uint16_t ee_data; /* write data */ 664} HAL_DIAG_EEVAL; 665 666 667typedef struct { 668 u_int offset; /* reg offset */ 669 uint32_t val; /* reg value */ 670} HAL_DIAG_REGVAL; 671 672/* 673 * 11n compatibility tweaks. 674 */ 675#define HAL_DIAG_11N_SERVICES 0x00000003 676#define HAL_DIAG_11N_SERVICES_S 0 677#define HAL_DIAG_11N_TXSTOMP 0x0000000c 678#define HAL_DIAG_11N_TXSTOMP_S 2 679 680typedef struct { 681 int maxNoiseImmunityLevel; /* [0..4] */ 682 int totalSizeDesired[5]; 683 int coarseHigh[5]; 684 int coarseLow[5]; 685 int firpwr[5]; 686 687 int maxSpurImmunityLevel; /* [0..7] */ 688 int cycPwrThr1[8]; 689 690 int maxFirstepLevel; /* [0..2] */ 691 int firstep[3]; 692 693 uint32_t ofdmTrigHigh; 694 uint32_t ofdmTrigLow; 695 int32_t cckTrigHigh; 696 int32_t cckTrigLow; 697 int32_t rssiThrLow; 698 int32_t rssiThrHigh; 699 700 int period; /* update listen period */ 701} HAL_ANI_PARAMS; 702 703extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 704 const void *args, uint32_t argsize, 705 void **result, uint32_t *resultsize); 706 707/* 708 * Setup a h/w rate table for use. 709 */ 710extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 711 712/* 713 * Common routine for implementing getChanNoise api. 714 */ 715int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 716 717/* 718 * Initialization support. 719 */ 720typedef struct { 721 const uint32_t *data; 722 int rows, cols; 723} HAL_INI_ARRAY; 724 725#define HAL_INI_INIT(_ia, _data, _cols) do { \ 726 (_ia)->data = (const uint32_t *)(_data); \ 727 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 728 (_ia)->cols = (_cols); \ 729} while (0) 730#define HAL_INI_VAL(_ia, _r, _c) \ 731 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 732 733/* 734 * OS_DELAY() does a PIO READ on the PCI bus which allows 735 * other cards' DMA reads to complete in the middle of our reset. 736 */ 737#define DMA_YIELD(x) do { \ 738 if ((++(x) % 64) == 0) \ 739 OS_DELAY(1); \ 740} while (0) 741 742#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 743 int r; \ 744 for (r = 0; r < N(regArray); r++) { \ 745 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 746 DMA_YIELD(regWr); \ 747 } \ 748} while (0) 749 750#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 751 int r; \ 752 for (r = 0; r < N(regArray); r++) { \ 753 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 754 DMA_YIELD(regWr); \ 755 } \ 756} while (0) 757 758extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 759 int col, int regWr); 760extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 761 int col); 762extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 763 const uint32_t data[], int regWr); 764 765#define CCK_SIFS_TIME 10 766#define CCK_PREAMBLE_BITS 144 767#define CCK_PLCP_BITS 48 768 769#define OFDM_SIFS_TIME 16 770#define OFDM_PREAMBLE_TIME 20 771#define OFDM_PLCP_BITS 22 772#define OFDM_SYMBOL_TIME 4 773 774#define OFDM_HALF_SIFS_TIME 32 775#define OFDM_HALF_PREAMBLE_TIME 40 776#define OFDM_HALF_PLCP_BITS 22 777#define OFDM_HALF_SYMBOL_TIME 8 778 779#define OFDM_QUARTER_SIFS_TIME 64 780#define OFDM_QUARTER_PREAMBLE_TIME 80 781#define OFDM_QUARTER_PLCP_BITS 22 782#define OFDM_QUARTER_SYMBOL_TIME 16 783 784#define TURBO_SIFS_TIME 8 785#define TURBO_PREAMBLE_TIME 14 786#define TURBO_PLCP_BITS 22 787#define TURBO_SYMBOL_TIME 4 788 789#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 790 791/* Generic EEPROM board value functions */ 792extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 793 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 794extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 795 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 796 uint8_t *pRetVpdList); 797extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 798 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 799 800/* Whether 5ghz fast clock is needed */ 801/* 802 * The chipset (Merlin, AR9300/later) should set the capability flag below; 803 * this flag simply says that the hardware can do it, not that the EEPROM 804 * says it can. 805 * 806 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock 807 * if the relevant eeprom flag is set. 808 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock 809 * by default. 810 */ 811#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 812 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 813 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \ 814 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G)) 815 816 817#endif /* _ATH_AH_INTERAL_H_ */ 818