ah_internal.h revision 221603
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 221603 2011-05-07 15:30:23Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 int16_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 int16_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halHTSGI20Support : 1, 188 halRfSilentSupport : 1, 189 halHwPhyCounterSupport : 1, 190 halWowSupport : 1, 191 halWowMatchPatternExact : 1, 192 halAutoSleepSupport : 1, 193 halFastCCSupport : 1, 194 halBtCoexSupport : 1; 195 uint32_t halRxStbcSupport : 1, 196 halTxStbcSupport : 1, 197 halGTTSupport : 1, 198 halCSTSupport : 1, 199 halRifsRxSupport : 1, 200 halRifsTxSupport : 1, 201 hal4AddrAggrSupport : 1, 202 halExtChanDfsSupport : 1, 203 halForcePpmSupport : 1, 204 halEnhancedPmSupport : 1, 205 halMbssidAggrSupport : 1, 206 halBssidMatchSupport : 1, 207 hal4kbSplitTransSupport : 1, 208 halHasRxSelfLinkedTail : 1; 209 uint32_t halWirelessModes; 210 uint16_t halTotalQueues; 211 uint16_t halKeyCacheSize; 212 uint16_t halLow5GhzChan, halHigh5GhzChan; 213 uint16_t halLow2GhzChan, halHigh2GhzChan; 214 int halTstampPrecision; 215 int halRtsAggrLimit; 216 uint8_t halTxChainMask; 217 uint8_t halRxChainMask; 218 uint8_t halNumGpioPins; 219 uint8_t halNumAntCfg2GHz; 220 uint8_t halNumAntCfg5GHz; 221 uint32_t halIntrMask; 222 uint8_t halTxStreams; 223 uint8_t halRxStreams; 224} HAL_CAPABILITIES; 225 226struct regDomain; 227 228/* 229 * The ``private area'' follows immediately after the ``public area'' 230 * in the data structure returned by ath_hal_attach. Private data are 231 * used by device-independent code such as the regulatory domain support. 232 * In general, code within the HAL should never depend on data in the 233 * public area. Instead any public data needed internally should be 234 * shadowed here. 235 * 236 * When declaring a device-specific ath_hal data structure this structure 237 * is assumed to at the front; e.g. 238 * 239 * struct ath_hal_5212 { 240 * struct ath_hal_private ah_priv; 241 * ... 242 * }; 243 * 244 * It might be better to manage the method pointers in this structure 245 * using an indirect pointer to a read-only data structure but this would 246 * disallow class-style method overriding. 247 */ 248struct ath_hal_private { 249 struct ath_hal h; /* public area */ 250 251 /* NB: all methods go first to simplify initialization */ 252 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 253 uint16_t channelFlags, 254 uint16_t *lowChannel, uint16_t *highChannel); 255 u_int (*ah_getWirelessModes)(struct ath_hal*); 256 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 257 uint16_t *data); 258 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 259 uint16_t data); 260 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 261 struct ieee80211_channel *); 262 int16_t (*ah_getNfAdjust)(struct ath_hal *, 263 const HAL_CHANNEL_INTERNAL*); 264 void (*ah_getNoiseFloor)(struct ath_hal *, 265 int16_t nfarray[]); 266 267 void *ah_eeprom; /* opaque EEPROM state */ 268 uint16_t ah_eeversion; /* EEPROM version */ 269 void (*ah_eepromDetach)(struct ath_hal *); 270 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 271 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 272 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 273 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 274 const void *args, uint32_t argsize, 275 void **result, uint32_t *resultsize); 276 277 /* 278 * Device revision information. 279 */ 280 uint16_t ah_devid; /* PCI device ID */ 281 uint16_t ah_subvendorid; /* PCI subvendor ID */ 282 uint32_t ah_macVersion; /* MAC version id */ 283 uint16_t ah_macRev; /* MAC revision */ 284 uint16_t ah_phyRev; /* PHY revision */ 285 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 286 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 287 uint8_t ah_ispcie; /* PCIE, special treatment */ 288 289 HAL_OPMODE ah_opmode; /* operating mode from reset */ 290 const struct ieee80211_channel *ah_curchan;/* operating channel */ 291 HAL_CAPABILITIES ah_caps; /* device capabilities */ 292 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 293 int16_t ah_powerLimit; /* tx power cap */ 294 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 295 u_int ah_tpScale; /* tx power scale factor */ 296 uint32_t ah_11nCompat; /* 11n compat controls */ 297 298 /* 299 * State for regulatory domain handling. 300 */ 301 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 302 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */ 303 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 304 u_int ah_nchan; /* valid items in ah_channels */ 305 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 306 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 307 308 uint8_t ah_coverageClass; /* coverage class */ 309 /* 310 * RF Silent handling; setup according to the EEPROM. 311 */ 312 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 313 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 314 /* 315 * Diagnostic support for discriminating HIUERR reports. 316 */ 317 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 318 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 319}; 320 321#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 322 323#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 324 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 325#define ath_hal_getWirelessModes(_ah) \ 326 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 327#define ath_hal_eepromRead(_ah, _off, _data) \ 328 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 329#define ath_hal_eepromWrite(_ah, _off, _data) \ 330 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 331#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 332 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 333#define ath_hal_gpioCfgInput(_ah, _gpio) \ 334 (_ah)->ah_gpioCfgInput(_ah, _gpio) 335#define ath_hal_gpioGet(_ah, _gpio) \ 336 (_ah)->ah_gpioGet(_ah, _gpio) 337#define ath_hal_gpioSet(_ah, _gpio, _val) \ 338 (_ah)->ah_gpioSet(_ah, _gpio, _val) 339#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 340 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 341#define ath_hal_getpowerlimits(_ah, _chan) \ 342 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 343#define ath_hal_getNfAdjust(_ah, _c) \ 344 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 345#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 346 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 347#define ath_hal_configPCIE(_ah, _reset) \ 348 (_ah)->ah_configPCIE(_ah, _reset) 349#define ath_hal_disablePCIE(_ah) \ 350 (_ah)->ah_disablePCIE(_ah) 351#define ath_hal_setInterrupts(_ah, _mask) \ 352 (_ah)->ah_setInterrupts(_ah, _mask) 353 354#define ath_hal_eepromDetach(_ah) do { \ 355 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 356 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 357} while (0) 358#define ath_hal_eepromGet(_ah, _param, _val) \ 359 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 360#define ath_hal_eepromSet(_ah, _param, _val) \ 361 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 362#define ath_hal_eepromGetFlag(_ah, _param) \ 363 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 364#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 365 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 366#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 367 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 368 369#ifndef _NET_IF_IEEE80211_H_ 370/* 371 * Stuff that would naturally come from _ieee80211.h 372 */ 373#define IEEE80211_ADDR_LEN 6 374 375#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 376#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 377#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 378 379#define IEEE80211_CRC_LEN 4 380 381#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 382 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 383#endif /* _NET_IF_IEEE80211_H_ */ 384 385#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 386 387#define INIT_AIFS 2 388#define INIT_CWMIN 15 389#define INIT_CWMIN_11B 31 390#define INIT_CWMAX 1023 391#define INIT_SH_RETRY 10 392#define INIT_LG_RETRY 10 393#define INIT_SSH_RETRY 32 394#define INIT_SLG_RETRY 32 395 396typedef struct { 397 uint32_t tqi_ver; /* HAL TXQ verson */ 398 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 399 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 400 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 401 uint32_t tqi_priority; 402 uint32_t tqi_aifs; /* aifs */ 403 uint32_t tqi_cwmin; /* cwMin */ 404 uint32_t tqi_cwmax; /* cwMax */ 405 uint16_t tqi_shretry; /* frame short retry limit */ 406 uint16_t tqi_lgretry; /* frame long retry limit */ 407 uint32_t tqi_cbrPeriod; 408 uint32_t tqi_cbrOverflowLimit; 409 uint32_t tqi_burstTime; 410 uint32_t tqi_readyTime; 411 uint32_t tqi_physCompBuf; 412 uint32_t tqi_intFlags; /* flags for internal use */ 413} HAL_TX_QUEUE_INFO; 414 415extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 416 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 417extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 418 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 419 420typedef enum { 421 HAL_ANI_PRESENT = 0x1, /* is ANI support present */ 422 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */ 423 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */ 424 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */ 425 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */ 426 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */ 427 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */ 428 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */ 429 HAL_ANI_ALL = 0xff 430} HAL_ANI_CMD; 431 432#define HAL_SPUR_VAL_MASK 0x3FFF 433#define HAL_SPUR_CHAN_WIDTH 87 434#define HAL_BIN_WIDTH_BASE_100HZ 3125 435#define HAL_BIN_WIDTH_TURBO_100HZ 6250 436#define HAL_MAX_BINS_ALLOWED 28 437 438#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 439#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 440 441#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 442 443/* 444 * Deduce if the host cpu has big- or litt-endian byte order. 445 */ 446static __inline__ int 447isBigEndian(void) 448{ 449 union { 450 int32_t i; 451 char c[4]; 452 } u; 453 u.i = 1; 454 return (u.c[0] == 0); 455} 456 457/* unalligned little endian access */ 458#define LE_READ_2(p) \ 459 ((uint16_t) \ 460 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 461#define LE_READ_4(p) \ 462 ((uint32_t) \ 463 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 464 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 465 466/* 467 * Register manipulation macros that expect bit field defines 468 * to follow the convention that an _S suffix is appended for 469 * a shift count, while the field mask has no suffix. 470 */ 471#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 472#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 473#define OS_REG_RMW(_a, _r, _set, _clr) \ 474 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) 475#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 476 OS_REG_WRITE(_a, _r, \ 477 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 478#define OS_REG_SET_BIT(_a, _r, _f) \ 479 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 480#define OS_REG_CLR_BIT(_a, _r, _f) \ 481 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 482 483/* Analog register writes may require a delay between each one (eg Merlin?) */ 484#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 485 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 486 487/* system-configurable parameters */ 488extern int ath_hal_dma_beacon_response_time; /* in TU's */ 489extern int ath_hal_sw_beacon_response_time; /* in TU's */ 490extern int ath_hal_additional_swba_backoff; /* in TU's */ 491extern int ath_hal_ar5416_biasadj; /* 1 or 0 */ 492 493/* wait for the register contents to have the specified value */ 494extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 495 uint32_t mask, uint32_t val); 496extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 497 uint32_t mask, uint32_t val, uint32_t timeout); 498 499/* return the first n bits in val reversed */ 500extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 501 502/* printf interfaces */ 503extern void ath_hal_printf(struct ath_hal *, const char*, ...) 504 __printflike(2,3); 505extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 506 __printflike(2, 0); 507extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 508 509/* allocate and free memory */ 510extern void *ath_hal_malloc(size_t); 511extern void ath_hal_free(void *); 512 513/* common debugging interfaces */ 514#ifdef AH_DEBUG 515#include "ah_debug.h" 516extern int ath_hal_debug; 517#define HALDEBUG(_ah, __m, ...) \ 518 do { \ 519 if (ath_hal_debug & (__m)) { \ 520 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 521 } \ 522 } while(0); 523 524extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 525 __printflike(3,4); 526#else 527#define HALDEBUG(_ah, __m, _fmt, ...) 528#endif /* AH_DEBUG */ 529 530/* 531 * Register logging definitions shared with ardecode. 532 */ 533#include "ah_decode.h" 534 535/* 536 * Common assertion interface. Note: it is a bad idea to generate 537 * an assertion failure for any recoverable event. Instead catch 538 * the violation and, if possible, fix it up or recover from it; either 539 * with an error return value or a diagnostic messages. System software 540 * does not panic unless the situation is hopeless. 541 */ 542#ifdef AH_ASSERT 543extern void ath_hal_assert_failed(const char* filename, 544 int lineno, const char* msg); 545 546#define HALASSERT(_x) do { \ 547 if (!(_x)) { \ 548 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 549 } \ 550} while (0) 551#else 552#define HALASSERT(_x) 553#endif /* AH_ASSERT */ 554 555/* 556 * Regulatory domain support. 557 */ 558 559/* 560 * Return the max allowed antenna gain and apply any regulatory 561 * domain specific changes. 562 */ 563u_int ath_hal_getantennareduction(struct ath_hal *ah, 564 const struct ieee80211_channel *chan, u_int twiceGain); 565 566/* 567 * Return the test group for the specific channel based on 568 * the current regulatory setup. 569 */ 570u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 571 572/* 573 * Map a public channel definition to the corresponding 574 * internal data structure. This implicitly specifies 575 * whether or not the specified channel is ok to use 576 * based on the current regulatory domain constraints. 577 */ 578#ifndef AH_DEBUG 579static OS_INLINE HAL_CHANNEL_INTERNAL * 580ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 581{ 582 HAL_CHANNEL_INTERNAL *cc; 583 584 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 585 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 586 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 587 return cc; 588} 589#else 590/* NB: non-inline version that checks state */ 591HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 592 const struct ieee80211_channel *); 593#endif /* AH_DEBUG */ 594 595/* 596 * Return the h/w frequency for a channel. This may be 597 * different from ic_freq if this is a GSM device that 598 * takes 2.4GHz frequencies and down-converts them. 599 */ 600static OS_INLINE uint16_t 601ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 602{ 603 return ath_hal_checkchannel(ah, c)->channel; 604} 605 606/* 607 * Convert between microseconds and core system clocks. 608 */ 609extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 610extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 611 612/* 613 * Generic get/set capability support. Each chip overrides 614 * this routine to support chip-specific capabilities. 615 */ 616extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 617 HAL_CAPABILITY_TYPE type, uint32_t capability, 618 uint32_t *result); 619extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 620 HAL_CAPABILITY_TYPE type, uint32_t capability, 621 uint32_t setting, HAL_STATUS *status); 622 623/* The diagnostic codes used to be internally defined here -adrian */ 624#include "ah_diagcodes.h" 625 626enum { 627 HAL_BB_HANG_DFS = 0x0001, 628 HAL_BB_HANG_RIFS = 0x0002, 629 HAL_BB_HANG_RX_CLEAR = 0x0004, 630 HAL_BB_HANG_UNKNOWN = 0x0080, 631 632 HAL_MAC_HANG_SIG1 = 0x0100, 633 HAL_MAC_HANG_SIG2 = 0x0200, 634 HAL_MAC_HANG_UNKNOWN = 0x8000, 635 636 HAL_BB_HANGS = HAL_BB_HANG_DFS 637 | HAL_BB_HANG_RIFS 638 | HAL_BB_HANG_RX_CLEAR 639 | HAL_BB_HANG_UNKNOWN, 640 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 641 | HAL_MAC_HANG_SIG2 642 | HAL_MAC_HANG_UNKNOWN, 643}; 644 645/* 646 * Device revision information. 647 */ 648typedef struct { 649 uint16_t ah_devid; /* PCI device ID */ 650 uint16_t ah_subvendorid; /* PCI subvendor ID */ 651 uint32_t ah_macVersion; /* MAC version id */ 652 uint16_t ah_macRev; /* MAC revision */ 653 uint16_t ah_phyRev; /* PHY revision */ 654 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 655 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 656} HAL_REVS; 657 658/* 659 * Argument payload for HAL_DIAG_SETKEY. 660 */ 661typedef struct { 662 HAL_KEYVAL dk_keyval; 663 uint16_t dk_keyix; /* key index */ 664 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 665 int dk_xor; /* XOR key data */ 666} HAL_DIAG_KEYVAL; 667 668/* 669 * Argument payload for HAL_DIAG_EEWRITE. 670 */ 671typedef struct { 672 uint16_t ee_off; /* eeprom offset */ 673 uint16_t ee_data; /* write data */ 674} HAL_DIAG_EEVAL; 675 676 677typedef struct { 678 u_int offset; /* reg offset */ 679 uint32_t val; /* reg value */ 680} HAL_DIAG_REGVAL; 681 682/* 683 * 11n compatibility tweaks. 684 */ 685#define HAL_DIAG_11N_SERVICES 0x00000003 686#define HAL_DIAG_11N_SERVICES_S 0 687#define HAL_DIAG_11N_TXSTOMP 0x0000000c 688#define HAL_DIAG_11N_TXSTOMP_S 2 689 690typedef struct { 691 int maxNoiseImmunityLevel; /* [0..4] */ 692 int totalSizeDesired[5]; 693 int coarseHigh[5]; 694 int coarseLow[5]; 695 int firpwr[5]; 696 697 int maxSpurImmunityLevel; /* [0..7] */ 698 int cycPwrThr1[8]; 699 700 int maxFirstepLevel; /* [0..2] */ 701 int firstep[3]; 702 703 uint32_t ofdmTrigHigh; 704 uint32_t ofdmTrigLow; 705 int32_t cckTrigHigh; 706 int32_t cckTrigLow; 707 int32_t rssiThrLow; 708 int32_t rssiThrHigh; 709 710 int period; /* update listen period */ 711} HAL_ANI_PARAMS; 712 713extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 714 const void *args, uint32_t argsize, 715 void **result, uint32_t *resultsize); 716 717/* 718 * Setup a h/w rate table for use. 719 */ 720extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 721 722/* 723 * Common routine for implementing getChanNoise api. 724 */ 725int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 726 727/* 728 * Initialization support. 729 */ 730typedef struct { 731 const uint32_t *data; 732 int rows, cols; 733} HAL_INI_ARRAY; 734 735#define HAL_INI_INIT(_ia, _data, _cols) do { \ 736 (_ia)->data = (const uint32_t *)(_data); \ 737 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 738 (_ia)->cols = (_cols); \ 739} while (0) 740#define HAL_INI_VAL(_ia, _r, _c) \ 741 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 742 743/* 744 * OS_DELAY() does a PIO READ on the PCI bus which allows 745 * other cards' DMA reads to complete in the middle of our reset. 746 */ 747#define DMA_YIELD(x) do { \ 748 if ((++(x) % 64) == 0) \ 749 OS_DELAY(1); \ 750} while (0) 751 752#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 753 int r; \ 754 for (r = 0; r < N(regArray); r++) { \ 755 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 756 DMA_YIELD(regWr); \ 757 } \ 758} while (0) 759 760#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 761 int r; \ 762 for (r = 0; r < N(regArray); r++) { \ 763 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 764 DMA_YIELD(regWr); \ 765 } \ 766} while (0) 767 768extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 769 int col, int regWr); 770extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 771 int col); 772extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 773 const uint32_t data[], int regWr); 774 775#define CCK_SIFS_TIME 10 776#define CCK_PREAMBLE_BITS 144 777#define CCK_PLCP_BITS 48 778 779#define OFDM_SIFS_TIME 16 780#define OFDM_PREAMBLE_TIME 20 781#define OFDM_PLCP_BITS 22 782#define OFDM_SYMBOL_TIME 4 783 784#define OFDM_HALF_SIFS_TIME 32 785#define OFDM_HALF_PREAMBLE_TIME 40 786#define OFDM_HALF_PLCP_BITS 22 787#define OFDM_HALF_SYMBOL_TIME 8 788 789#define OFDM_QUARTER_SIFS_TIME 64 790#define OFDM_QUARTER_PREAMBLE_TIME 80 791#define OFDM_QUARTER_PLCP_BITS 22 792#define OFDM_QUARTER_SYMBOL_TIME 16 793 794#define TURBO_SIFS_TIME 8 795#define TURBO_PREAMBLE_TIME 14 796#define TURBO_PLCP_BITS 22 797#define TURBO_SYMBOL_TIME 4 798 799#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 800 801/* Generic EEPROM board value functions */ 802extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 803 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 804extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 805 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 806 uint8_t *pRetVpdList); 807extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 808 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 809 810/* Whether 5ghz fast clock is needed for Merlin and later */ 811#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 812 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 813 ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G)) 814 815 816#endif /* _ATH_AH_INTERAL_H_ */ 817