ah_internal.h revision 220442
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 220442 2011-04-08 06:58:01Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31#include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */ 32 33#ifndef NBBY 34#define NBBY 8 /* number of bits/byte */ 35#endif 36 37#ifndef roundup 38#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 39#endif 40#ifndef howmany 41#define howmany(x, y) (((x)+((y)-1))/(y)) 42#endif 43 44#ifndef offsetof 45#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 46#endif 47 48typedef struct { 49 uint16_t start; /* first register */ 50 uint16_t end; /* ending register or zero */ 51} HAL_REGRANGE; 52 53typedef struct { 54 uint32_t addr; /* regiser address/offset */ 55 uint32_t value; /* value to write */ 56} HAL_REGWRITE; 57 58/* 59 * Transmit power scale factor. 60 * 61 * NB: This is not public because we want to discourage the use of 62 * scaling; folks should use the tx power limit interface. 63 */ 64typedef enum { 65 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 66 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 67 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 68 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 69 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 70} HAL_TP_SCALE; 71 72typedef enum { 73 HAL_CAP_RADAR = 0, /* Radar capability */ 74 HAL_CAP_AR = 1, /* AR capability */ 75} HAL_PHYDIAG_CAPS; 76 77/* 78 * Each chip or class of chips registers to offer support. 79 */ 80struct ath_hal_chip { 81 const char *name; 82 const char *(*probe)(uint16_t vendorid, uint16_t devid); 83 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 84 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 85 HAL_STATUS *error); 86}; 87#ifndef AH_CHIP 88#define AH_CHIP(_name, _probe, _attach) \ 89static struct ath_hal_chip _name##_chip = { \ 90 .name = #_name, \ 91 .probe = _probe, \ 92 .attach = _attach \ 93}; \ 94OS_DATA_SET(ah_chips, _name##_chip) 95#endif 96 97/* 98 * Each RF backend registers to offer support; this is mostly 99 * used by multi-chip 5212 solutions. Single-chip solutions 100 * have a fixed idea about which RF to use. 101 */ 102struct ath_hal_rf { 103 const char *name; 104 HAL_BOOL (*probe)(struct ath_hal *ah); 105 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 106}; 107#ifndef AH_RF 108#define AH_RF(_name, _probe, _attach) \ 109static struct ath_hal_rf _name##_rf = { \ 110 .name = __STRING(_name), \ 111 .probe = _probe, \ 112 .attach = _attach \ 113}; \ 114OS_DATA_SET(ah_rfs, _name##_rf) 115#endif 116 117struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 118 119/* 120 * Maximum number of internal channels. Entries are per unique 121 * frequency so this might be need to be increased to handle all 122 * usage cases; typically no more than 32 are really needed but 123 * dynamically allocating the data structures is a bit painful 124 * right now. 125 */ 126#ifndef AH_MAXCHAN 127#define AH_MAXCHAN 96 128#endif 129 130/* 131 * Internal per-channel state. These are found 132 * using ic_devdata in the ieee80211_channel. 133 */ 134typedef struct { 135 uint16_t channel; /* h/w frequency, NB: may be mapped */ 136 uint8_t privFlags; 137#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 138#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 139#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 140#define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */ 141 uint8_t calValid; /* bitmask of cal types */ 142 int8_t iCoff; 143 int8_t qCoff; 144 int16_t rawNoiseFloor; 145 int16_t noiseFloorAdjust; 146#ifdef AH_SUPPORT_AR5416 147 uint8_t noiseFloorCtl[AH_MIMO_MAX_CHAINS]; 148 uint8_t noiseFloorExt[AH_MIMO_MAX_CHAINS]; 149#endif /* AH_SUPPORT_AR5416 */ 150 uint16_t mainSpur; /* cached spur value for this channel */ 151} HAL_CHANNEL_INTERNAL; 152 153/* channel requires noise floor check */ 154#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 155 156/* all full-width channels */ 157#define IEEE80211_CHAN_ALLFULL \ 158 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 159#define IEEE80211_CHAN_ALLTURBOFULL \ 160 (IEEE80211_CHAN_ALLTURBO - \ 161 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 162 163typedef struct { 164 uint32_t halChanSpreadSupport : 1, 165 halSleepAfterBeaconBroken : 1, 166 halCompressSupport : 1, 167 halBurstSupport : 1, 168 halFastFramesSupport : 1, 169 halChapTuningSupport : 1, 170 halTurboGSupport : 1, 171 halTurboPrimeSupport : 1, 172 halMicAesCcmSupport : 1, 173 halMicCkipSupport : 1, 174 halMicTkipSupport : 1, 175 halTkipMicTxRxKeySupport : 1, 176 halCipherAesCcmSupport : 1, 177 halCipherCkipSupport : 1, 178 halCipherTkipSupport : 1, 179 halPSPollBroken : 1, 180 halVEOLSupport : 1, 181 halBssIdMaskSupport : 1, 182 halMcastKeySrchSupport : 1, 183 halTsfAddSupport : 1, 184 halChanHalfRate : 1, 185 halChanQuarterRate : 1, 186 halHTSupport : 1, 187 halRfSilentSupport : 1, 188 halHwPhyCounterSupport : 1, 189 halWowSupport : 1, 190 halWowMatchPatternExact : 1, 191 halAutoSleepSupport : 1, 192 halFastCCSupport : 1, 193 halBtCoexSupport : 1; 194 uint32_t halRxStbcSupport : 1, 195 halTxStbcSupport : 1, 196 halGTTSupport : 1, 197 halCSTSupport : 1, 198 halRifsRxSupport : 1, 199 halRifsTxSupport : 1, 200 halExtChanDfsSupport : 1, 201 halForcePpmSupport : 1, 202 halEnhancedPmSupport : 1, 203 halMbssidAggrSupport : 1, 204 halBssidMatchSupport : 1, 205 hal4kbSplitTransSupport : 1, 206 halHasPsPollSupport : 1, 207 halHasRxSelfLinkedTail : 1; 208 uint32_t halWirelessModes; 209 uint16_t halTotalQueues; 210 uint16_t halKeyCacheSize; 211 uint16_t halLow5GhzChan, halHigh5GhzChan; 212 uint16_t halLow2GhzChan, halHigh2GhzChan; 213 int halTstampPrecision; 214 int halRtsAggrLimit; 215 uint8_t halTxChainMask; 216 uint8_t halRxChainMask; 217 uint8_t halNumGpioPins; 218 uint8_t halNumAntCfg2GHz; 219 uint8_t halNumAntCfg5GHz; 220 uint32_t halIntrMask; 221 uint8_t halTxStreams; 222 uint8_t halRxStreams; 223} HAL_CAPABILITIES; 224 225struct regDomain; 226 227/* 228 * The ``private area'' follows immediately after the ``public area'' 229 * in the data structure returned by ath_hal_attach. Private data are 230 * used by device-independent code such as the regulatory domain support. 231 * In general, code within the HAL should never depend on data in the 232 * public area. Instead any public data needed internally should be 233 * shadowed here. 234 * 235 * When declaring a device-specific ath_hal data structure this structure 236 * is assumed to at the front; e.g. 237 * 238 * struct ath_hal_5212 { 239 * struct ath_hal_private ah_priv; 240 * ... 241 * }; 242 * 243 * It might be better to manage the method pointers in this structure 244 * using an indirect pointer to a read-only data structure but this would 245 * disallow class-style method overriding. 246 */ 247struct ath_hal_private { 248 struct ath_hal h; /* public area */ 249 250 /* NB: all methods go first to simplify initialization */ 251 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 252 uint16_t channelFlags, 253 uint16_t *lowChannel, uint16_t *highChannel); 254 u_int (*ah_getWirelessModes)(struct ath_hal*); 255 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 256 uint16_t *data); 257 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 258 uint16_t data); 259 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 260 struct ieee80211_channel *); 261 int16_t (*ah_getNfAdjust)(struct ath_hal *, 262 const HAL_CHANNEL_INTERNAL*); 263 void (*ah_getNoiseFloor)(struct ath_hal *, 264 int16_t nfarray[]); 265 266 void *ah_eeprom; /* opaque EEPROM state */ 267 uint16_t ah_eeversion; /* EEPROM version */ 268 void (*ah_eepromDetach)(struct ath_hal *); 269 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 270 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 271 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 272 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 273 const void *args, uint32_t argsize, 274 void **result, uint32_t *resultsize); 275 276 /* 277 * Device revision information. 278 */ 279 uint16_t ah_devid; /* PCI device ID */ 280 uint16_t ah_subvendorid; /* PCI subvendor ID */ 281 uint32_t ah_macVersion; /* MAC version id */ 282 uint16_t ah_macRev; /* MAC revision */ 283 uint16_t ah_phyRev; /* PHY revision */ 284 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 285 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 286 uint8_t ah_ispcie; /* PCIE, special treatment */ 287 288 HAL_OPMODE ah_opmode; /* operating mode from reset */ 289 const struct ieee80211_channel *ah_curchan;/* operating channel */ 290 HAL_CAPABILITIES ah_caps; /* device capabilities */ 291 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 292 int16_t ah_powerLimit; /* tx power cap */ 293 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 294 u_int ah_tpScale; /* tx power scale factor */ 295 uint32_t ah_11nCompat; /* 11n compat controls */ 296 297 /* 298 * State for regulatory domain handling. 299 */ 300 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 301 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 302 u_int ah_nchan; /* valid items in ah_channels */ 303 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 304 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 305 306 uint8_t ah_coverageClass; /* coverage class */ 307 /* 308 * RF Silent handling; setup according to the EEPROM. 309 */ 310 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 311 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 312 /* 313 * Diagnostic support for discriminating HIUERR reports. 314 */ 315 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 316 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 317}; 318 319#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 320 321#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 322 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 323#define ath_hal_getWirelessModes(_ah) \ 324 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 325#define ath_hal_eepromRead(_ah, _off, _data) \ 326 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 327#define ath_hal_eepromWrite(_ah, _off, _data) \ 328 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 329#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 330 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 331#define ath_hal_gpioCfgInput(_ah, _gpio) \ 332 (_ah)->ah_gpioCfgInput(_ah, _gpio) 333#define ath_hal_gpioGet(_ah, _gpio) \ 334 (_ah)->ah_gpioGet(_ah, _gpio) 335#define ath_hal_gpioSet(_ah, _gpio, _val) \ 336 (_ah)->ah_gpioSet(_ah, _gpio, _val) 337#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 338 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 339#define ath_hal_getpowerlimits(_ah, _chan) \ 340 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 341#define ath_hal_getNfAdjust(_ah, _c) \ 342 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 343#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 344 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 345#define ath_hal_configPCIE(_ah, _reset) \ 346 (_ah)->ah_configPCIE(_ah, _reset) 347#define ath_hal_disablePCIE(_ah) \ 348 (_ah)->ah_disablePCIE(_ah) 349#define ath_hal_setInterrupts(_ah, _mask) \ 350 (_ah)->ah_setInterrupts(_ah, _mask) 351 352#define ath_hal_eepromDetach(_ah) do { \ 353 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 354 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 355} while (0) 356#define ath_hal_eepromGet(_ah, _param, _val) \ 357 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 358#define ath_hal_eepromSet(_ah, _param, _val) \ 359 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 360#define ath_hal_eepromGetFlag(_ah, _param) \ 361 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 362#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 363 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 364#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 365 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 366 367#ifndef _NET_IF_IEEE80211_H_ 368/* 369 * Stuff that would naturally come from _ieee80211.h 370 */ 371#define IEEE80211_ADDR_LEN 6 372 373#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 374#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 375#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 376 377#define IEEE80211_CRC_LEN 4 378 379#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 380 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 381#endif /* _NET_IF_IEEE80211_H_ */ 382 383#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 384 385#define INIT_AIFS 2 386#define INIT_CWMIN 15 387#define INIT_CWMIN_11B 31 388#define INIT_CWMAX 1023 389#define INIT_SH_RETRY 10 390#define INIT_LG_RETRY 10 391#define INIT_SSH_RETRY 32 392#define INIT_SLG_RETRY 32 393 394typedef struct { 395 uint32_t tqi_ver; /* HAL TXQ verson */ 396 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 397 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 398 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 399 uint32_t tqi_priority; 400 uint32_t tqi_aifs; /* aifs */ 401 uint32_t tqi_cwmin; /* cwMin */ 402 uint32_t tqi_cwmax; /* cwMax */ 403 uint16_t tqi_shretry; /* frame short retry limit */ 404 uint16_t tqi_lgretry; /* frame long retry limit */ 405 uint32_t tqi_cbrPeriod; 406 uint32_t tqi_cbrOverflowLimit; 407 uint32_t tqi_burstTime; 408 uint32_t tqi_readyTime; 409 uint32_t tqi_physCompBuf; 410 uint32_t tqi_intFlags; /* flags for internal use */ 411} HAL_TX_QUEUE_INFO; 412 413extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 414 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 415extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 416 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 417 418typedef enum { 419 HAL_ANI_PRESENT = 0x1, /* is ANI support present */ 420 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */ 421 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */ 422 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */ 423 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */ 424 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */ 425 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */ 426 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */ 427 HAL_ANI_ALL = 0xff 428} HAL_ANI_CMD; 429 430#define HAL_SPUR_VAL_MASK 0x3FFF 431#define HAL_SPUR_CHAN_WIDTH 87 432#define HAL_BIN_WIDTH_BASE_100HZ 3125 433#define HAL_BIN_WIDTH_TURBO_100HZ 6250 434#define HAL_MAX_BINS_ALLOWED 28 435 436#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 437#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 438 439#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 440 441/* 442 * Deduce if the host cpu has big- or litt-endian byte order. 443 */ 444static __inline__ int 445isBigEndian(void) 446{ 447 union { 448 int32_t i; 449 char c[4]; 450 } u; 451 u.i = 1; 452 return (u.c[0] == 0); 453} 454 455/* unalligned little endian access */ 456#define LE_READ_2(p) \ 457 ((uint16_t) \ 458 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 459#define LE_READ_4(p) \ 460 ((uint32_t) \ 461 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 462 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 463 464/* 465 * Register manipulation macros that expect bit field defines 466 * to follow the convention that an _S suffix is appended for 467 * a shift count, while the field mask has no suffix. 468 */ 469#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 470#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 471#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 472 OS_REG_WRITE(_a, _r, \ 473 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 474#define OS_REG_SET_BIT(_a, _r, _f) \ 475 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 476#define OS_REG_CLR_BIT(_a, _r, _f) \ 477 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 478 479/* Analog register writes may require a delay between each one (eg Merlin?) */ 480#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 481 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 482 483/* system-configurable parameters */ 484extern int ath_hal_dma_beacon_response_time; /* in TU's */ 485extern int ath_hal_sw_beacon_response_time; /* in TU's */ 486extern int ath_hal_additional_swba_backoff; /* in TU's */ 487extern int ath_hal_ar5416_biasadj; /* 1 or 0 */ 488 489/* wait for the register contents to have the specified value */ 490extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 491 uint32_t mask, uint32_t val); 492extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 493 uint32_t mask, uint32_t val, uint32_t timeout); 494 495/* return the first n bits in val reversed */ 496extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 497 498/* printf interfaces */ 499extern void ath_hal_printf(struct ath_hal *, const char*, ...) 500 __printflike(2,3); 501extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 502 __printflike(2, 0); 503extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 504 505/* allocate and free memory */ 506extern void *ath_hal_malloc(size_t); 507extern void ath_hal_free(void *); 508 509/* common debugging interfaces */ 510#ifdef AH_DEBUG 511#include "ah_debug.h" 512extern int ath_hal_debug; 513#define HALDEBUG(_ah, __m, ...) \ 514 do { \ 515 if (ath_hal_debug & (__m)) { \ 516 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 517 } \ 518 } while(0); 519 520extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 521 __printflike(3,4); 522#else 523#define HALDEBUG(_ah, __m, _fmt, ...) 524#endif /* AH_DEBUG */ 525 526/* 527 * Register logging definitions shared with ardecode. 528 */ 529#include "ah_decode.h" 530 531/* 532 * Common assertion interface. Note: it is a bad idea to generate 533 * an assertion failure for any recoverable event. Instead catch 534 * the violation and, if possible, fix it up or recover from it; either 535 * with an error return value or a diagnostic messages. System software 536 * does not panic unless the situation is hopeless. 537 */ 538#ifdef AH_ASSERT 539extern void ath_hal_assert_failed(const char* filename, 540 int lineno, const char* msg); 541 542#define HALASSERT(_x) do { \ 543 if (!(_x)) { \ 544 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 545 } \ 546} while (0) 547#else 548#define HALASSERT(_x) 549#endif /* AH_ASSERT */ 550 551/* 552 * Regulatory domain support. 553 */ 554 555/* 556 * Return the max allowed antenna gain and apply any regulatory 557 * domain specific changes. 558 */ 559u_int ath_hal_getantennareduction(struct ath_hal *ah, 560 const struct ieee80211_channel *chan, u_int twiceGain); 561 562/* 563 * Return the test group for the specific channel based on 564 * the current regulatory setup. 565 */ 566u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 567 568/* 569 * Map a public channel definition to the corresponding 570 * internal data structure. This implicitly specifies 571 * whether or not the specified channel is ok to use 572 * based on the current regulatory domain constraints. 573 */ 574#ifndef AH_DEBUG 575static OS_INLINE HAL_CHANNEL_INTERNAL * 576ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 577{ 578 HAL_CHANNEL_INTERNAL *cc; 579 580 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 581 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 582 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 583 return cc; 584} 585#else 586/* NB: non-inline version that checks state */ 587HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 588 const struct ieee80211_channel *); 589#endif /* AH_DEBUG */ 590 591/* 592 * Return the h/w frequency for a channel. This may be 593 * different from ic_freq if this is a GSM device that 594 * takes 2.4GHz frequencies and down-converts them. 595 */ 596static OS_INLINE uint16_t 597ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 598{ 599 return ath_hal_checkchannel(ah, c)->channel; 600} 601 602/* 603 * Convert between microseconds and core system clocks. 604 */ 605extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 606extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 607 608/* 609 * Generic get/set capability support. Each chip overrides 610 * this routine to support chip-specific capabilities. 611 */ 612extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 613 HAL_CAPABILITY_TYPE type, uint32_t capability, 614 uint32_t *result); 615extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 616 HAL_CAPABILITY_TYPE type, uint32_t capability, 617 uint32_t setting, HAL_STATUS *status); 618 619/* The diagnostic codes used to be internally defined here -adrian */ 620#include "ah_diagcodes.h" 621 622enum { 623 HAL_BB_HANG_DFS = 0x0001, 624 HAL_BB_HANG_RIFS = 0x0002, 625 HAL_BB_HANG_RX_CLEAR = 0x0004, 626 HAL_BB_HANG_UNKNOWN = 0x0080, 627 628 HAL_MAC_HANG_SIG1 = 0x0100, 629 HAL_MAC_HANG_SIG2 = 0x0200, 630 HAL_MAC_HANG_UNKNOWN = 0x8000, 631 632 HAL_BB_HANGS = HAL_BB_HANG_DFS 633 | HAL_BB_HANG_RIFS 634 | HAL_BB_HANG_RX_CLEAR 635 | HAL_BB_HANG_UNKNOWN, 636 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 637 | HAL_MAC_HANG_SIG2 638 | HAL_MAC_HANG_UNKNOWN, 639}; 640 641/* 642 * Device revision information. 643 */ 644typedef struct { 645 uint16_t ah_devid; /* PCI device ID */ 646 uint16_t ah_subvendorid; /* PCI subvendor ID */ 647 uint32_t ah_macVersion; /* MAC version id */ 648 uint16_t ah_macRev; /* MAC revision */ 649 uint16_t ah_phyRev; /* PHY revision */ 650 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 651 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 652} HAL_REVS; 653 654/* 655 * Argument payload for HAL_DIAG_SETKEY. 656 */ 657typedef struct { 658 HAL_KEYVAL dk_keyval; 659 uint16_t dk_keyix; /* key index */ 660 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 661 int dk_xor; /* XOR key data */ 662} HAL_DIAG_KEYVAL; 663 664/* 665 * Argument payload for HAL_DIAG_EEWRITE. 666 */ 667typedef struct { 668 uint16_t ee_off; /* eeprom offset */ 669 uint16_t ee_data; /* write data */ 670} HAL_DIAG_EEVAL; 671 672 673typedef struct { 674 u_int offset; /* reg offset */ 675 uint32_t val; /* reg value */ 676} HAL_DIAG_REGVAL; 677 678/* 679 * 11n compatibility tweaks. 680 */ 681#define HAL_DIAG_11N_SERVICES 0x00000003 682#define HAL_DIAG_11N_SERVICES_S 0 683#define HAL_DIAG_11N_TXSTOMP 0x0000000c 684#define HAL_DIAG_11N_TXSTOMP_S 2 685 686typedef struct { 687 int maxNoiseImmunityLevel; /* [0..4] */ 688 int totalSizeDesired[5]; 689 int coarseHigh[5]; 690 int coarseLow[5]; 691 int firpwr[5]; 692 693 int maxSpurImmunityLevel; /* [0..7] */ 694 int cycPwrThr1[8]; 695 696 int maxFirstepLevel; /* [0..2] */ 697 int firstep[3]; 698 699 uint32_t ofdmTrigHigh; 700 uint32_t ofdmTrigLow; 701 int32_t cckTrigHigh; 702 int32_t cckTrigLow; 703 int32_t rssiThrLow; 704 int32_t rssiThrHigh; 705 706 int period; /* update listen period */ 707} HAL_ANI_PARAMS; 708 709extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 710 const void *args, uint32_t argsize, 711 void **result, uint32_t *resultsize); 712 713/* 714 * Setup a h/w rate table for use. 715 */ 716extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 717 718/* 719 * Common routine for implementing getChanNoise api. 720 */ 721int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 722 723/* 724 * Initialization support. 725 */ 726typedef struct { 727 const uint32_t *data; 728 int rows, cols; 729} HAL_INI_ARRAY; 730 731#define HAL_INI_INIT(_ia, _data, _cols) do { \ 732 (_ia)->data = (const uint32_t *)(_data); \ 733 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 734 (_ia)->cols = (_cols); \ 735} while (0) 736#define HAL_INI_VAL(_ia, _r, _c) \ 737 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 738 739/* 740 * OS_DELAY() does a PIO READ on the PCI bus which allows 741 * other cards' DMA reads to complete in the middle of our reset. 742 */ 743#define DMA_YIELD(x) do { \ 744 if ((++(x) % 64) == 0) \ 745 OS_DELAY(1); \ 746} while (0) 747 748#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 749 int r; \ 750 for (r = 0; r < N(regArray); r++) { \ 751 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 752 DMA_YIELD(regWr); \ 753 } \ 754} while (0) 755 756#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 757 int r; \ 758 for (r = 0; r < N(regArray); r++) { \ 759 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 760 DMA_YIELD(regWr); \ 761 } \ 762} while (0) 763 764extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 765 int col, int regWr); 766extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 767 int col); 768extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 769 const uint32_t data[], int regWr); 770 771#define CCK_SIFS_TIME 10 772#define CCK_PREAMBLE_BITS 144 773#define CCK_PLCP_BITS 48 774 775#define OFDM_SIFS_TIME 16 776#define OFDM_PREAMBLE_TIME 20 777#define OFDM_PLCP_BITS 22 778#define OFDM_SYMBOL_TIME 4 779 780#define OFDM_HALF_SIFS_TIME 32 781#define OFDM_HALF_PREAMBLE_TIME 40 782#define OFDM_HALF_PLCP_BITS 22 783#define OFDM_HALF_SYMBOL_TIME 8 784 785#define OFDM_QUARTER_SIFS_TIME 64 786#define OFDM_QUARTER_PREAMBLE_TIME 80 787#define OFDM_QUARTER_PLCP_BITS 22 788#define OFDM_QUARTER_SYMBOL_TIME 16 789 790#define TURBO_SIFS_TIME 8 791#define TURBO_PREAMBLE_TIME 14 792#define TURBO_PLCP_BITS 22 793#define TURBO_SYMBOL_TIME 4 794 795#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 796 797/* Generic EEPROM board value functions */ 798extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 799 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 800extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 801 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 802 uint8_t *pRetVpdList); 803extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 804 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 805 806/* Whether 5ghz fast clock is needed for Merlin and later */ 807#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 808 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 809 ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G)) 810 811 812#endif /* _ATH_AH_INTERAL_H_ */ 813