ah_internal.h revision 220325
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 220325 2011-04-04 14:53:36Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 84 HAL_STATUS *error); 85}; 86#ifndef AH_CHIP 87#define AH_CHIP(_name, _probe, _attach) \ 88static struct ath_hal_chip _name##_chip = { \ 89 .name = #_name, \ 90 .probe = _probe, \ 91 .attach = _attach \ 92}; \ 93OS_DATA_SET(ah_chips, _name##_chip) 94#endif 95 96/* 97 * Each RF backend registers to offer support; this is mostly 98 * used by multi-chip 5212 solutions. Single-chip solutions 99 * have a fixed idea about which RF to use. 100 */ 101struct ath_hal_rf { 102 const char *name; 103 HAL_BOOL (*probe)(struct ath_hal *ah); 104 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 105}; 106#ifndef AH_RF 107#define AH_RF(_name, _probe, _attach) \ 108static struct ath_hal_rf _name##_rf = { \ 109 .name = __STRING(_name), \ 110 .probe = _probe, \ 111 .attach = _attach \ 112}; \ 113OS_DATA_SET(ah_rfs, _name##_rf) 114#endif 115 116struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 117 118/* 119 * Maximum number of internal channels. Entries are per unique 120 * frequency so this might be need to be increased to handle all 121 * usage cases; typically no more than 32 are really needed but 122 * dynamically allocating the data structures is a bit painful 123 * right now. 124 */ 125#ifndef AH_MAXCHAN 126#define AH_MAXCHAN 96 127#endif 128 129/* 130 * Internal per-channel state. These are found 131 * using ic_devdata in the ieee80211_channel. 132 */ 133typedef struct { 134 uint16_t channel; /* h/w frequency, NB: may be mapped */ 135 uint8_t privFlags; 136#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 137#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 138#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 139 uint8_t calValid; /* bitmask of cal types */ 140 int8_t iCoff; 141 int8_t qCoff; 142 int16_t rawNoiseFloor; 143 int16_t noiseFloorAdjust; 144 uint16_t mainSpur; /* cached spur value for this channel */ 145} HAL_CHANNEL_INTERNAL; 146 147/* channel requires noise floor check */ 148#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 149 150/* all full-width channels */ 151#define IEEE80211_CHAN_ALLFULL \ 152 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 153#define IEEE80211_CHAN_ALLTURBOFULL \ 154 (IEEE80211_CHAN_ALLTURBO - \ 155 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 156 157typedef struct { 158 uint32_t halChanSpreadSupport : 1, 159 halSleepAfterBeaconBroken : 1, 160 halCompressSupport : 1, 161 halBurstSupport : 1, 162 halFastFramesSupport : 1, 163 halChapTuningSupport : 1, 164 halTurboGSupport : 1, 165 halTurboPrimeSupport : 1, 166 halMicAesCcmSupport : 1, 167 halMicCkipSupport : 1, 168 halMicTkipSupport : 1, 169 halTkipMicTxRxKeySupport : 1, 170 halCipherAesCcmSupport : 1, 171 halCipherCkipSupport : 1, 172 halCipherTkipSupport : 1, 173 halPSPollBroken : 1, 174 halVEOLSupport : 1, 175 halBssIdMaskSupport : 1, 176 halMcastKeySrchSupport : 1, 177 halTsfAddSupport : 1, 178 halChanHalfRate : 1, 179 halChanQuarterRate : 1, 180 halHTSupport : 1, 181 halRfSilentSupport : 1, 182 halHwPhyCounterSupport : 1, 183 halWowSupport : 1, 184 halWowMatchPatternExact : 1, 185 halAutoSleepSupport : 1, 186 halFastCCSupport : 1, 187 halBtCoexSupport : 1; 188 uint32_t halRxStbcSupport : 1, 189 halTxStbcSupport : 1, 190 halGTTSupport : 1, 191 halCSTSupport : 1, 192 halRifsRxSupport : 1, 193 halRifsTxSupport : 1, 194 halExtChanDfsSupport : 1, 195 halForcePpmSupport : 1, 196 halEnhancedPmSupport : 1, 197 halMbssidAggrSupport : 1, 198 halBssidMatchSupport : 1, 199 hal4kbSplitTransSupport : 1, 200 halHasPsPollSupport : 1, 201 halHasRxSelfLinkedTail : 1; 202 uint32_t halWirelessModes; 203 uint16_t halTotalQueues; 204 uint16_t halKeyCacheSize; 205 uint16_t halLow5GhzChan, halHigh5GhzChan; 206 uint16_t halLow2GhzChan, halHigh2GhzChan; 207 int halTstampPrecision; 208 int halRtsAggrLimit; 209 uint8_t halTxChainMask; 210 uint8_t halRxChainMask; 211 uint8_t halNumGpioPins; 212 uint8_t halNumAntCfg2GHz; 213 uint8_t halNumAntCfg5GHz; 214 uint32_t halIntrMask; 215 uint8_t halTxStreams; 216 uint8_t halRxStreams; 217} HAL_CAPABILITIES; 218 219struct regDomain; 220 221/* 222 * The ``private area'' follows immediately after the ``public area'' 223 * in the data structure returned by ath_hal_attach. Private data are 224 * used by device-independent code such as the regulatory domain support. 225 * In general, code within the HAL should never depend on data in the 226 * public area. Instead any public data needed internally should be 227 * shadowed here. 228 * 229 * When declaring a device-specific ath_hal data structure this structure 230 * is assumed to at the front; e.g. 231 * 232 * struct ath_hal_5212 { 233 * struct ath_hal_private ah_priv; 234 * ... 235 * }; 236 * 237 * It might be better to manage the method pointers in this structure 238 * using an indirect pointer to a read-only data structure but this would 239 * disallow class-style method overriding. 240 */ 241struct ath_hal_private { 242 struct ath_hal h; /* public area */ 243 244 /* NB: all methods go first to simplify initialization */ 245 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 246 uint16_t channelFlags, 247 uint16_t *lowChannel, uint16_t *highChannel); 248 u_int (*ah_getWirelessModes)(struct ath_hal*); 249 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 250 uint16_t *data); 251 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 252 uint16_t data); 253 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 254 struct ieee80211_channel *); 255 int16_t (*ah_getNfAdjust)(struct ath_hal *, 256 const HAL_CHANNEL_INTERNAL*); 257 void (*ah_getNoiseFloor)(struct ath_hal *, 258 int16_t nfarray[]); 259 260 void *ah_eeprom; /* opaque EEPROM state */ 261 uint16_t ah_eeversion; /* EEPROM version */ 262 void (*ah_eepromDetach)(struct ath_hal *); 263 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 264 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 265 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 266 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 267 const void *args, uint32_t argsize, 268 void **result, uint32_t *resultsize); 269 270 /* 271 * Device revision information. 272 */ 273 uint16_t ah_devid; /* PCI device ID */ 274 uint16_t ah_subvendorid; /* PCI subvendor ID */ 275 uint32_t ah_macVersion; /* MAC version id */ 276 uint16_t ah_macRev; /* MAC revision */ 277 uint16_t ah_phyRev; /* PHY revision */ 278 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 279 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 280 uint8_t ah_ispcie; /* PCIE, special treatment */ 281 282 HAL_OPMODE ah_opmode; /* operating mode from reset */ 283 const struct ieee80211_channel *ah_curchan;/* operating channel */ 284 HAL_CAPABILITIES ah_caps; /* device capabilities */ 285 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 286 int16_t ah_powerLimit; /* tx power cap */ 287 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 288 u_int ah_tpScale; /* tx power scale factor */ 289 uint32_t ah_11nCompat; /* 11n compat controls */ 290 291 /* 292 * State for regulatory domain handling. 293 */ 294 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 295 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 296 u_int ah_nchan; /* valid items in ah_channels */ 297 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 298 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 299 300 uint8_t ah_coverageClass; /* coverage class */ 301 /* 302 * RF Silent handling; setup according to the EEPROM. 303 */ 304 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 305 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 306 /* 307 * Diagnostic support for discriminating HIUERR reports. 308 */ 309 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 310 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 311}; 312 313#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 314 315#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 316 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 317#define ath_hal_getWirelessModes(_ah) \ 318 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 319#define ath_hal_eepromRead(_ah, _off, _data) \ 320 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 321#define ath_hal_eepromWrite(_ah, _off, _data) \ 322 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 323#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 324 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 325#define ath_hal_gpioCfgInput(_ah, _gpio) \ 326 (_ah)->ah_gpioCfgInput(_ah, _gpio) 327#define ath_hal_gpioGet(_ah, _gpio) \ 328 (_ah)->ah_gpioGet(_ah, _gpio) 329#define ath_hal_gpioSet(_ah, _gpio, _val) \ 330 (_ah)->ah_gpioSet(_ah, _gpio, _val) 331#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 332 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 333#define ath_hal_getpowerlimits(_ah, _chan) \ 334 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 335#define ath_hal_getNfAdjust(_ah, _c) \ 336 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 337#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 338 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 339#define ath_hal_configPCIE(_ah, _reset) \ 340 (_ah)->ah_configPCIE(_ah, _reset) 341#define ath_hal_disablePCIE(_ah) \ 342 (_ah)->ah_disablePCIE(_ah) 343#define ath_hal_setInterrupts(_ah, _mask) \ 344 (_ah)->ah_setInterrupts(_ah, _mask) 345 346#define ath_hal_eepromDetach(_ah) do { \ 347 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 348 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 349} while (0) 350#define ath_hal_eepromGet(_ah, _param, _val) \ 351 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 352#define ath_hal_eepromSet(_ah, _param, _val) \ 353 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 354#define ath_hal_eepromGetFlag(_ah, _param) \ 355 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 356#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 357 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 358#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 359 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 360 361#ifndef _NET_IF_IEEE80211_H_ 362/* 363 * Stuff that would naturally come from _ieee80211.h 364 */ 365#define IEEE80211_ADDR_LEN 6 366 367#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 368#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 369#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 370 371#define IEEE80211_CRC_LEN 4 372 373#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 374 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 375#endif /* _NET_IF_IEEE80211_H_ */ 376 377#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 378 379#define INIT_AIFS 2 380#define INIT_CWMIN 15 381#define INIT_CWMIN_11B 31 382#define INIT_CWMAX 1023 383#define INIT_SH_RETRY 10 384#define INIT_LG_RETRY 10 385#define INIT_SSH_RETRY 32 386#define INIT_SLG_RETRY 32 387 388typedef struct { 389 uint32_t tqi_ver; /* HAL TXQ verson */ 390 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 391 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 392 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 393 uint32_t tqi_priority; 394 uint32_t tqi_aifs; /* aifs */ 395 uint32_t tqi_cwmin; /* cwMin */ 396 uint32_t tqi_cwmax; /* cwMax */ 397 uint16_t tqi_shretry; /* frame short retry limit */ 398 uint16_t tqi_lgretry; /* frame long retry limit */ 399 uint32_t tqi_cbrPeriod; 400 uint32_t tqi_cbrOverflowLimit; 401 uint32_t tqi_burstTime; 402 uint32_t tqi_readyTime; 403 uint32_t tqi_physCompBuf; 404 uint32_t tqi_intFlags; /* flags for internal use */ 405} HAL_TX_QUEUE_INFO; 406 407extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 408 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 409extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 410 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 411 412typedef enum { 413 HAL_ANI_PRESENT = 0x1, /* is ANI support present */ 414 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */ 415 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */ 416 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */ 417 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */ 418 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */ 419 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */ 420 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */ 421 HAL_ANI_ALL = 0xff 422} HAL_ANI_CMD; 423 424#define HAL_SPUR_VAL_MASK 0x3FFF 425#define HAL_SPUR_CHAN_WIDTH 87 426#define HAL_BIN_WIDTH_BASE_100HZ 3125 427#define HAL_BIN_WIDTH_TURBO_100HZ 6250 428#define HAL_MAX_BINS_ALLOWED 28 429 430#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 431#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 432 433#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 434 435/* 436 * Deduce if the host cpu has big- or litt-endian byte order. 437 */ 438static __inline__ int 439isBigEndian(void) 440{ 441 union { 442 int32_t i; 443 char c[4]; 444 } u; 445 u.i = 1; 446 return (u.c[0] == 0); 447} 448 449/* unalligned little endian access */ 450#define LE_READ_2(p) \ 451 ((uint16_t) \ 452 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 453#define LE_READ_4(p) \ 454 ((uint32_t) \ 455 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 456 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 457 458/* 459 * Register manipulation macros that expect bit field defines 460 * to follow the convention that an _S suffix is appended for 461 * a shift count, while the field mask has no suffix. 462 */ 463#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 464#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 465#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 466 OS_REG_WRITE(_a, _r, \ 467 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 468#define OS_REG_SET_BIT(_a, _r, _f) \ 469 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 470#define OS_REG_CLR_BIT(_a, _r, _f) \ 471 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 472 473/* Analog register writes may require a delay between each one (eg Merlin?) */ 474#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 475 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 476 477/* system-configurable parameters */ 478extern int ath_hal_dma_beacon_response_time; /* in TU's */ 479extern int ath_hal_sw_beacon_response_time; /* in TU's */ 480extern int ath_hal_additional_swba_backoff; /* in TU's */ 481extern int ath_hal_ar5416_biasadj; /* 1 or 0 */ 482 483/* wait for the register contents to have the specified value */ 484extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 485 uint32_t mask, uint32_t val); 486extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 487 uint32_t mask, uint32_t val, uint32_t timeout); 488 489/* return the first n bits in val reversed */ 490extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 491 492/* printf interfaces */ 493extern void ath_hal_printf(struct ath_hal *, const char*, ...) 494 __printflike(2,3); 495extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 496 __printflike(2, 0); 497extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 498 499/* allocate and free memory */ 500extern void *ath_hal_malloc(size_t); 501extern void ath_hal_free(void *); 502 503/* common debugging interfaces */ 504#ifdef AH_DEBUG 505#include "ah_debug.h" 506extern int ath_hal_debug; 507#define HALDEBUG(_ah, __m, ...) \ 508 do { \ 509 if (ath_hal_debug & (__m)) { \ 510 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 511 } \ 512 } while(0); 513 514extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 515 __printflike(3,4); 516#else 517#define HALDEBUG(_ah, __m, _fmt, ...) 518#endif /* AH_DEBUG */ 519 520/* 521 * Register logging definitions shared with ardecode. 522 */ 523#include "ah_decode.h" 524 525/* 526 * Common assertion interface. Note: it is a bad idea to generate 527 * an assertion failure for any recoverable event. Instead catch 528 * the violation and, if possible, fix it up or recover from it; either 529 * with an error return value or a diagnostic messages. System software 530 * does not panic unless the situation is hopeless. 531 */ 532#ifdef AH_ASSERT 533extern void ath_hal_assert_failed(const char* filename, 534 int lineno, const char* msg); 535 536#define HALASSERT(_x) do { \ 537 if (!(_x)) { \ 538 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 539 } \ 540} while (0) 541#else 542#define HALASSERT(_x) 543#endif /* AH_ASSERT */ 544 545/* 546 * Regulatory domain support. 547 */ 548 549/* 550 * Return the max allowed antenna gain and apply any regulatory 551 * domain specific changes. 552 */ 553u_int ath_hal_getantennareduction(struct ath_hal *ah, 554 const struct ieee80211_channel *chan, u_int twiceGain); 555 556/* 557 * Return the test group for the specific channel based on 558 * the current regulatory setup. 559 */ 560u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 561 562/* 563 * Map a public channel definition to the corresponding 564 * internal data structure. This implicitly specifies 565 * whether or not the specified channel is ok to use 566 * based on the current regulatory domain constraints. 567 */ 568#ifndef AH_DEBUG 569static OS_INLINE HAL_CHANNEL_INTERNAL * 570ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 571{ 572 HAL_CHANNEL_INTERNAL *cc; 573 574 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 575 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 576 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 577 return cc; 578} 579#else 580/* NB: non-inline version that checks state */ 581HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 582 const struct ieee80211_channel *); 583#endif /* AH_DEBUG */ 584 585/* 586 * Return the h/w frequency for a channel. This may be 587 * different from ic_freq if this is a GSM device that 588 * takes 2.4GHz frequencies and down-converts them. 589 */ 590static OS_INLINE uint16_t 591ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 592{ 593 return ath_hal_checkchannel(ah, c)->channel; 594} 595 596/* 597 * Convert between microseconds and core system clocks. 598 */ 599extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 600extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 601 602/* 603 * Generic get/set capability support. Each chip overrides 604 * this routine to support chip-specific capabilities. 605 */ 606extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 607 HAL_CAPABILITY_TYPE type, uint32_t capability, 608 uint32_t *result); 609extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 610 HAL_CAPABILITY_TYPE type, uint32_t capability, 611 uint32_t setting, HAL_STATUS *status); 612 613/* The diagnostic codes used to be internally defined here -adrian */ 614#include "ah_diagcodes.h" 615 616enum { 617 HAL_BB_HANG_DFS = 0x0001, 618 HAL_BB_HANG_RIFS = 0x0002, 619 HAL_BB_HANG_RX_CLEAR = 0x0004, 620 HAL_BB_HANG_UNKNOWN = 0x0080, 621 622 HAL_MAC_HANG_SIG1 = 0x0100, 623 HAL_MAC_HANG_SIG2 = 0x0200, 624 HAL_MAC_HANG_UNKNOWN = 0x8000, 625 626 HAL_BB_HANGS = HAL_BB_HANG_DFS 627 | HAL_BB_HANG_RIFS 628 | HAL_BB_HANG_RX_CLEAR 629 | HAL_BB_HANG_UNKNOWN, 630 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 631 | HAL_MAC_HANG_SIG2 632 | HAL_MAC_HANG_UNKNOWN, 633}; 634 635/* 636 * Device revision information. 637 */ 638typedef struct { 639 uint16_t ah_devid; /* PCI device ID */ 640 uint16_t ah_subvendorid; /* PCI subvendor ID */ 641 uint32_t ah_macVersion; /* MAC version id */ 642 uint16_t ah_macRev; /* MAC revision */ 643 uint16_t ah_phyRev; /* PHY revision */ 644 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 645 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 646} HAL_REVS; 647 648/* 649 * Argument payload for HAL_DIAG_SETKEY. 650 */ 651typedef struct { 652 HAL_KEYVAL dk_keyval; 653 uint16_t dk_keyix; /* key index */ 654 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 655 int dk_xor; /* XOR key data */ 656} HAL_DIAG_KEYVAL; 657 658/* 659 * Argument payload for HAL_DIAG_EEWRITE. 660 */ 661typedef struct { 662 uint16_t ee_off; /* eeprom offset */ 663 uint16_t ee_data; /* write data */ 664} HAL_DIAG_EEVAL; 665 666 667typedef struct { 668 u_int offset; /* reg offset */ 669 uint32_t val; /* reg value */ 670} HAL_DIAG_REGVAL; 671 672/* 673 * 11n compatibility tweaks. 674 */ 675#define HAL_DIAG_11N_SERVICES 0x00000003 676#define HAL_DIAG_11N_SERVICES_S 0 677#define HAL_DIAG_11N_TXSTOMP 0x0000000c 678#define HAL_DIAG_11N_TXSTOMP_S 2 679 680typedef struct { 681 int maxNoiseImmunityLevel; /* [0..4] */ 682 int totalSizeDesired[5]; 683 int coarseHigh[5]; 684 int coarseLow[5]; 685 int firpwr[5]; 686 687 int maxSpurImmunityLevel; /* [0..7] */ 688 int cycPwrThr1[8]; 689 690 int maxFirstepLevel; /* [0..2] */ 691 int firstep[3]; 692 693 uint32_t ofdmTrigHigh; 694 uint32_t ofdmTrigLow; 695 int32_t cckTrigHigh; 696 int32_t cckTrigLow; 697 int32_t rssiThrLow; 698 int32_t rssiThrHigh; 699 700 int period; /* update listen period */ 701} HAL_ANI_PARAMS; 702 703extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 704 const void *args, uint32_t argsize, 705 void **result, uint32_t *resultsize); 706 707/* 708 * Setup a h/w rate table for use. 709 */ 710extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 711 712/* 713 * Common routine for implementing getChanNoise api. 714 */ 715int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 716 717/* 718 * Initialization support. 719 */ 720typedef struct { 721 const uint32_t *data; 722 int rows, cols; 723} HAL_INI_ARRAY; 724 725#define HAL_INI_INIT(_ia, _data, _cols) do { \ 726 (_ia)->data = (const uint32_t *)(_data); \ 727 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 728 (_ia)->cols = (_cols); \ 729} while (0) 730#define HAL_INI_VAL(_ia, _r, _c) \ 731 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 732 733/* 734 * OS_DELAY() does a PIO READ on the PCI bus which allows 735 * other cards' DMA reads to complete in the middle of our reset. 736 */ 737#define DMA_YIELD(x) do { \ 738 if ((++(x) % 64) == 0) \ 739 OS_DELAY(1); \ 740} while (0) 741 742#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 743 int r; \ 744 for (r = 0; r < N(regArray); r++) { \ 745 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 746 DMA_YIELD(regWr); \ 747 } \ 748} while (0) 749 750#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 751 int r; \ 752 for (r = 0; r < N(regArray); r++) { \ 753 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 754 DMA_YIELD(regWr); \ 755 } \ 756} while (0) 757 758extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 759 int col, int regWr); 760extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 761 int col); 762extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 763 const uint32_t data[], int regWr); 764 765#define CCK_SIFS_TIME 10 766#define CCK_PREAMBLE_BITS 144 767#define CCK_PLCP_BITS 48 768 769#define OFDM_SIFS_TIME 16 770#define OFDM_PREAMBLE_TIME 20 771#define OFDM_PLCP_BITS 22 772#define OFDM_SYMBOL_TIME 4 773 774#define OFDM_HALF_SIFS_TIME 32 775#define OFDM_HALF_PREAMBLE_TIME 40 776#define OFDM_HALF_PLCP_BITS 22 777#define OFDM_HALF_SYMBOL_TIME 8 778 779#define OFDM_QUARTER_SIFS_TIME 64 780#define OFDM_QUARTER_PREAMBLE_TIME 80 781#define OFDM_QUARTER_PLCP_BITS 22 782#define OFDM_QUARTER_SYMBOL_TIME 16 783 784#define TURBO_SIFS_TIME 8 785#define TURBO_PREAMBLE_TIME 14 786#define TURBO_PLCP_BITS 22 787#define TURBO_SYMBOL_TIME 4 788 789#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 790 791/* Generic EEPROM board value functions */ 792extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 793 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 794extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 795 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 796 uint8_t *pRetVpdList); 797extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 798 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 799 800/* Whether 5ghz fast clock is needed for Merlin and later */ 801#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 802 (IEEE80211_IS_CHAN_5GHZ(_c) && \ 803 ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G)) 804 805 806#endif /* _ATH_AH_INTERAL_H_ */ 807