ah_internal.h revision 220034
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 220034 2011-03-26 11:59:18Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 84 HAL_STATUS *error); 85}; 86#ifndef AH_CHIP 87#define AH_CHIP(_name, _probe, _attach) \ 88static struct ath_hal_chip _name##_chip = { \ 89 .name = #_name, \ 90 .probe = _probe, \ 91 .attach = _attach \ 92}; \ 93OS_DATA_SET(ah_chips, _name##_chip) 94#endif 95 96/* 97 * Each RF backend registers to offer support; this is mostly 98 * used by multi-chip 5212 solutions. Single-chip solutions 99 * have a fixed idea about which RF to use. 100 */ 101struct ath_hal_rf { 102 const char *name; 103 HAL_BOOL (*probe)(struct ath_hal *ah); 104 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 105}; 106#ifndef AH_RF 107#define AH_RF(_name, _probe, _attach) \ 108static struct ath_hal_rf _name##_rf = { \ 109 .name = __STRING(_name), \ 110 .probe = _probe, \ 111 .attach = _attach \ 112}; \ 113OS_DATA_SET(ah_rfs, _name##_rf) 114#endif 115 116struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 117 118/* 119 * Maximum number of internal channels. Entries are per unique 120 * frequency so this might be need to be increased to handle all 121 * usage cases; typically no more than 32 are really needed but 122 * dynamically allocating the data structures is a bit painful 123 * right now. 124 */ 125#ifndef AH_MAXCHAN 126#define AH_MAXCHAN 96 127#endif 128 129/* 130 * Internal per-channel state. These are found 131 * using ic_devdata in the ieee80211_channel. 132 */ 133typedef struct { 134 uint16_t channel; /* h/w frequency, NB: may be mapped */ 135 uint8_t privFlags; 136#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 137#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 138#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 139 uint8_t calValid; /* bitmask of cal types */ 140 int8_t iCoff; 141 int8_t qCoff; 142 int16_t rawNoiseFloor; 143 int16_t noiseFloorAdjust; 144 uint16_t mainSpur; /* cached spur value for this channel */ 145} HAL_CHANNEL_INTERNAL; 146 147/* channel requires noise floor check */ 148#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 149 150/* all full-width channels */ 151#define IEEE80211_CHAN_ALLFULL \ 152 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 153#define IEEE80211_CHAN_ALLTURBOFULL \ 154 (IEEE80211_CHAN_ALLTURBO - \ 155 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 156 157typedef struct { 158 uint32_t halChanSpreadSupport : 1, 159 halSleepAfterBeaconBroken : 1, 160 halCompressSupport : 1, 161 halBurstSupport : 1, 162 halFastFramesSupport : 1, 163 halChapTuningSupport : 1, 164 halTurboGSupport : 1, 165 halTurboPrimeSupport : 1, 166 halMicAesCcmSupport : 1, 167 halMicCkipSupport : 1, 168 halMicTkipSupport : 1, 169 halTkipMicTxRxKeySupport : 1, 170 halCipherAesCcmSupport : 1, 171 halCipherCkipSupport : 1, 172 halCipherTkipSupport : 1, 173 halPSPollBroken : 1, 174 halVEOLSupport : 1, 175 halBssIdMaskSupport : 1, 176 halMcastKeySrchSupport : 1, 177 halTsfAddSupport : 1, 178 halChanHalfRate : 1, 179 halChanQuarterRate : 1, 180 halHTSupport : 1, 181 halRfSilentSupport : 1, 182 halHwPhyCounterSupport : 1, 183 halWowSupport : 1, 184 halWowMatchPatternExact : 1, 185 halAutoSleepSupport : 1, 186 halFastCCSupport : 1, 187 halBtCoexSupport : 1; 188 uint32_t halRxStbcSupport : 1, 189 halTxStbcSupport : 1, 190 halGTTSupport : 1, 191 halCSTSupport : 1, 192 halRifsRxSupport : 1, 193 halRifsTxSupport : 1, 194 halExtChanDfsSupport : 1, 195 halForcePpmSupport : 1, 196 halEnhancedPmSupport : 1, 197 halMbssidAggrSupport : 1, 198 halBssidMatchSupport : 1, 199 hal4kbSplitTransSupport : 1, 200 halHasPsPollSupport : 1; 201 uint32_t halWirelessModes; 202 uint16_t halTotalQueues; 203 uint16_t halKeyCacheSize; 204 uint16_t halLow5GhzChan, halHigh5GhzChan; 205 uint16_t halLow2GhzChan, halHigh2GhzChan; 206 int halTstampPrecision; 207 int halRtsAggrLimit; 208 uint8_t halTxChainMask; 209 uint8_t halRxChainMask; 210 uint8_t halNumGpioPins; 211 uint8_t halNumAntCfg2GHz; 212 uint8_t halNumAntCfg5GHz; 213 uint32_t halIntrMask; 214 uint8_t halTxStreams; 215 uint8_t halRxStreams; 216} HAL_CAPABILITIES; 217 218struct regDomain; 219 220/* 221 * The ``private area'' follows immediately after the ``public area'' 222 * in the data structure returned by ath_hal_attach. Private data are 223 * used by device-independent code such as the regulatory domain support. 224 * In general, code within the HAL should never depend on data in the 225 * public area. Instead any public data needed internally should be 226 * shadowed here. 227 * 228 * When declaring a device-specific ath_hal data structure this structure 229 * is assumed to at the front; e.g. 230 * 231 * struct ath_hal_5212 { 232 * struct ath_hal_private ah_priv; 233 * ... 234 * }; 235 * 236 * It might be better to manage the method pointers in this structure 237 * using an indirect pointer to a read-only data structure but this would 238 * disallow class-style method overriding. 239 */ 240struct ath_hal_private { 241 struct ath_hal h; /* public area */ 242 243 /* NB: all methods go first to simplify initialization */ 244 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 245 uint16_t channelFlags, 246 uint16_t *lowChannel, uint16_t *highChannel); 247 u_int (*ah_getWirelessModes)(struct ath_hal*); 248 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 249 uint16_t *data); 250 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 251 uint16_t data); 252 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 253 struct ieee80211_channel *); 254 int16_t (*ah_getNfAdjust)(struct ath_hal *, 255 const HAL_CHANNEL_INTERNAL*); 256 void (*ah_getNoiseFloor)(struct ath_hal *, 257 int16_t nfarray[]); 258 259 void *ah_eeprom; /* opaque EEPROM state */ 260 uint16_t ah_eeversion; /* EEPROM version */ 261 void (*ah_eepromDetach)(struct ath_hal *); 262 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 263 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 264 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 265 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 266 const void *args, uint32_t argsize, 267 void **result, uint32_t *resultsize); 268 269 /* 270 * Device revision information. 271 */ 272 uint16_t ah_devid; /* PCI device ID */ 273 uint16_t ah_subvendorid; /* PCI subvendor ID */ 274 uint32_t ah_macVersion; /* MAC version id */ 275 uint16_t ah_macRev; /* MAC revision */ 276 uint16_t ah_phyRev; /* PHY revision */ 277 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 278 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 279 uint8_t ah_ispcie; /* PCIE, special treatment */ 280 281 HAL_OPMODE ah_opmode; /* operating mode from reset */ 282 const struct ieee80211_channel *ah_curchan;/* operating channel */ 283 HAL_CAPABILITIES ah_caps; /* device capabilities */ 284 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 285 int16_t ah_powerLimit; /* tx power cap */ 286 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 287 u_int ah_tpScale; /* tx power scale factor */ 288 uint32_t ah_11nCompat; /* 11n compat controls */ 289 290 /* 291 * State for regulatory domain handling. 292 */ 293 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 294 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 295 u_int ah_nchan; /* valid items in ah_channels */ 296 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 297 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 298 299 uint8_t ah_coverageClass; /* coverage class */ 300 /* 301 * RF Silent handling; setup according to the EEPROM. 302 */ 303 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 304 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 305 /* 306 * Diagnostic support for discriminating HIUERR reports. 307 */ 308 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 309 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 310}; 311 312#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 313 314#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 315 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 316#define ath_hal_getWirelessModes(_ah) \ 317 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 318#define ath_hal_eepromRead(_ah, _off, _data) \ 319 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 320#define ath_hal_eepromWrite(_ah, _off, _data) \ 321 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 322#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 323 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 324#define ath_hal_gpioCfgInput(_ah, _gpio) \ 325 (_ah)->ah_gpioCfgInput(_ah, _gpio) 326#define ath_hal_gpioGet(_ah, _gpio) \ 327 (_ah)->ah_gpioGet(_ah, _gpio) 328#define ath_hal_gpioSet(_ah, _gpio, _val) \ 329 (_ah)->ah_gpioSet(_ah, _gpio, _val) 330#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 331 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 332#define ath_hal_getpowerlimits(_ah, _chan) \ 333 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 334#define ath_hal_getNfAdjust(_ah, _c) \ 335 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 336#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 337 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 338#define ath_hal_configPCIE(_ah, _reset) \ 339 (_ah)->ah_configPCIE(_ah, _reset) 340#define ath_hal_disablePCIE(_ah) \ 341 (_ah)->ah_disablePCIE(_ah) 342#define ath_hal_setInterrupts(_ah, _mask) \ 343 (_ah)->ah_setInterrupts(_ah, _mask) 344 345#define ath_hal_eepromDetach(_ah) do { \ 346 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 347 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 348} while (0) 349#define ath_hal_eepromGet(_ah, _param, _val) \ 350 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 351#define ath_hal_eepromSet(_ah, _param, _val) \ 352 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 353#define ath_hal_eepromGetFlag(_ah, _param) \ 354 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 355#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 356 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 357#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 358 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 359 360#ifndef _NET_IF_IEEE80211_H_ 361/* 362 * Stuff that would naturally come from _ieee80211.h 363 */ 364#define IEEE80211_ADDR_LEN 6 365 366#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 367#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 368#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 369 370#define IEEE80211_CRC_LEN 4 371 372#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 373 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 374#endif /* _NET_IF_IEEE80211_H_ */ 375 376#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 377 378#define INIT_AIFS 2 379#define INIT_CWMIN 15 380#define INIT_CWMIN_11B 31 381#define INIT_CWMAX 1023 382#define INIT_SH_RETRY 10 383#define INIT_LG_RETRY 10 384#define INIT_SSH_RETRY 32 385#define INIT_SLG_RETRY 32 386 387typedef struct { 388 uint32_t tqi_ver; /* HAL TXQ verson */ 389 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 390 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 391 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 392 uint32_t tqi_priority; 393 uint32_t tqi_aifs; /* aifs */ 394 uint32_t tqi_cwmin; /* cwMin */ 395 uint32_t tqi_cwmax; /* cwMax */ 396 uint16_t tqi_shretry; /* frame short retry limit */ 397 uint16_t tqi_lgretry; /* frame long retry limit */ 398 uint32_t tqi_cbrPeriod; 399 uint32_t tqi_cbrOverflowLimit; 400 uint32_t tqi_burstTime; 401 uint32_t tqi_readyTime; 402 uint32_t tqi_physCompBuf; 403 uint32_t tqi_intFlags; /* flags for internal use */ 404} HAL_TX_QUEUE_INFO; 405 406extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 407 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 408extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 409 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 410 411typedef enum { 412 HAL_ANI_PRESENT = 0x1, /* is ANI support present */ 413 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */ 414 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */ 415 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */ 416 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */ 417 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */ 418 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */ 419 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */ 420 HAL_ANI_ALL = 0xff 421} HAL_ANI_CMD; 422 423#define HAL_SPUR_VAL_MASK 0x3FFF 424#define HAL_SPUR_CHAN_WIDTH 87 425#define HAL_BIN_WIDTH_BASE_100HZ 3125 426#define HAL_BIN_WIDTH_TURBO_100HZ 6250 427#define HAL_MAX_BINS_ALLOWED 28 428 429#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 430#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 431 432#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 433 434/* 435 * Deduce if the host cpu has big- or litt-endian byte order. 436 */ 437static __inline__ int 438isBigEndian(void) 439{ 440 union { 441 int32_t i; 442 char c[4]; 443 } u; 444 u.i = 1; 445 return (u.c[0] == 0); 446} 447 448/* unalligned little endian access */ 449#define LE_READ_2(p) \ 450 ((uint16_t) \ 451 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 452#define LE_READ_4(p) \ 453 ((uint32_t) \ 454 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 455 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 456 457/* 458 * Register manipulation macros that expect bit field defines 459 * to follow the convention that an _S suffix is appended for 460 * a shift count, while the field mask has no suffix. 461 */ 462#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 463#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 464#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 465 OS_REG_WRITE(_a, _r, \ 466 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 467#define OS_REG_SET_BIT(_a, _r, _f) \ 468 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 469#define OS_REG_CLR_BIT(_a, _r, _f) \ 470 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 471 472/* Analog register writes may require a delay between each one (eg Merlin?) */ 473#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 474 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 475 476/* system-configurable parameters */ 477extern int ath_hal_dma_beacon_response_time; /* in TU's */ 478extern int ath_hal_sw_beacon_response_time; /* in TU's */ 479extern int ath_hal_additional_swba_backoff; /* in TU's */ 480extern int ath_hal_ar5416_biasadj; /* 1 or 0 */ 481 482/* wait for the register contents to have the specified value */ 483extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 484 uint32_t mask, uint32_t val); 485extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 486 uint32_t mask, uint32_t val, uint32_t timeout); 487 488/* return the first n bits in val reversed */ 489extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 490 491/* printf interfaces */ 492extern void ath_hal_printf(struct ath_hal *, const char*, ...) 493 __printflike(2,3); 494extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 495 __printflike(2, 0); 496extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 497 498/* allocate and free memory */ 499extern void *ath_hal_malloc(size_t); 500extern void ath_hal_free(void *); 501 502/* common debugging interfaces */ 503#ifdef AH_DEBUG 504#include "ah_debug.h" 505extern int ath_hal_debug; 506#define HALDEBUG(_ah, __m, ...) \ 507 do { \ 508 if (ath_hal_debug & (__m)) { \ 509 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 510 } \ 511 } while(0); 512 513extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 514 __printflike(3,4); 515#else 516#define HALDEBUG(_ah, __m, _fmt, ...) 517#endif /* AH_DEBUG */ 518 519/* 520 * Register logging definitions shared with ardecode. 521 */ 522#include "ah_decode.h" 523 524/* 525 * Common assertion interface. Note: it is a bad idea to generate 526 * an assertion failure for any recoverable event. Instead catch 527 * the violation and, if possible, fix it up or recover from it; either 528 * with an error return value or a diagnostic messages. System software 529 * does not panic unless the situation is hopeless. 530 */ 531#ifdef AH_ASSERT 532extern void ath_hal_assert_failed(const char* filename, 533 int lineno, const char* msg); 534 535#define HALASSERT(_x) do { \ 536 if (!(_x)) { \ 537 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 538 } \ 539} while (0) 540#else 541#define HALASSERT(_x) 542#endif /* AH_ASSERT */ 543 544/* 545 * Regulatory domain support. 546 */ 547 548/* 549 * Return the max allowed antenna gain and apply any regulatory 550 * domain specific changes. 551 */ 552u_int ath_hal_getantennareduction(struct ath_hal *ah, 553 const struct ieee80211_channel *chan, u_int twiceGain); 554 555/* 556 * Return the test group for the specific channel based on 557 * the current regulatory setup. 558 */ 559u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 560 561/* 562 * Map a public channel definition to the corresponding 563 * internal data structure. This implicitly specifies 564 * whether or not the specified channel is ok to use 565 * based on the current regulatory domain constraints. 566 */ 567#ifndef AH_DEBUG 568static OS_INLINE HAL_CHANNEL_INTERNAL * 569ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 570{ 571 HAL_CHANNEL_INTERNAL *cc; 572 573 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 574 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 575 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 576 return cc; 577} 578#else 579/* NB: non-inline version that checks state */ 580HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 581 const struct ieee80211_channel *); 582#endif /* AH_DEBUG */ 583 584/* 585 * Return the h/w frequency for a channel. This may be 586 * different from ic_freq if this is a GSM device that 587 * takes 2.4GHz frequencies and down-converts them. 588 */ 589static OS_INLINE uint16_t 590ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 591{ 592 return ath_hal_checkchannel(ah, c)->channel; 593} 594 595/* 596 * Convert between microseconds and core system clocks. 597 */ 598extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 599extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 600 601/* 602 * Generic get/set capability support. Each chip overrides 603 * this routine to support chip-specific capabilities. 604 */ 605extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 606 HAL_CAPABILITY_TYPE type, uint32_t capability, 607 uint32_t *result); 608extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 609 HAL_CAPABILITY_TYPE type, uint32_t capability, 610 uint32_t setting, HAL_STATUS *status); 611 612/* The diagnostic codes used to be internally defined here -adrian */ 613#include "ah_diagcodes.h" 614 615enum { 616 HAL_BB_HANG_DFS = 0x0001, 617 HAL_BB_HANG_RIFS = 0x0002, 618 HAL_BB_HANG_RX_CLEAR = 0x0004, 619 HAL_BB_HANG_UNKNOWN = 0x0080, 620 621 HAL_MAC_HANG_SIG1 = 0x0100, 622 HAL_MAC_HANG_SIG2 = 0x0200, 623 HAL_MAC_HANG_UNKNOWN = 0x8000, 624 625 HAL_BB_HANGS = HAL_BB_HANG_DFS 626 | HAL_BB_HANG_RIFS 627 | HAL_BB_HANG_RX_CLEAR 628 | HAL_BB_HANG_UNKNOWN, 629 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 630 | HAL_MAC_HANG_SIG2 631 | HAL_MAC_HANG_UNKNOWN, 632}; 633 634/* 635 * Device revision information. 636 */ 637typedef struct { 638 uint16_t ah_devid; /* PCI device ID */ 639 uint16_t ah_subvendorid; /* PCI subvendor ID */ 640 uint32_t ah_macVersion; /* MAC version id */ 641 uint16_t ah_macRev; /* MAC revision */ 642 uint16_t ah_phyRev; /* PHY revision */ 643 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 644 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 645} HAL_REVS; 646 647/* 648 * Argument payload for HAL_DIAG_SETKEY. 649 */ 650typedef struct { 651 HAL_KEYVAL dk_keyval; 652 uint16_t dk_keyix; /* key index */ 653 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 654 int dk_xor; /* XOR key data */ 655} HAL_DIAG_KEYVAL; 656 657/* 658 * Argument payload for HAL_DIAG_EEWRITE. 659 */ 660typedef struct { 661 uint16_t ee_off; /* eeprom offset */ 662 uint16_t ee_data; /* write data */ 663} HAL_DIAG_EEVAL; 664 665 666typedef struct { 667 u_int offset; /* reg offset */ 668 uint32_t val; /* reg value */ 669} HAL_DIAG_REGVAL; 670 671/* 672 * 11n compatibility tweaks. 673 */ 674#define HAL_DIAG_11N_SERVICES 0x00000003 675#define HAL_DIAG_11N_SERVICES_S 0 676#define HAL_DIAG_11N_TXSTOMP 0x0000000c 677#define HAL_DIAG_11N_TXSTOMP_S 2 678 679typedef struct { 680 int maxNoiseImmunityLevel; /* [0..4] */ 681 int totalSizeDesired[5]; 682 int coarseHigh[5]; 683 int coarseLow[5]; 684 int firpwr[5]; 685 686 int maxSpurImmunityLevel; /* [0..7] */ 687 int cycPwrThr1[8]; 688 689 int maxFirstepLevel; /* [0..2] */ 690 int firstep[3]; 691 692 uint32_t ofdmTrigHigh; 693 uint32_t ofdmTrigLow; 694 int32_t cckTrigHigh; 695 int32_t cckTrigLow; 696 int32_t rssiThrLow; 697 int32_t rssiThrHigh; 698 699 int period; /* update listen period */ 700} HAL_ANI_PARAMS; 701 702extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 703 const void *args, uint32_t argsize, 704 void **result, uint32_t *resultsize); 705 706/* 707 * Setup a h/w rate table for use. 708 */ 709extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 710 711/* 712 * Common routine for implementing getChanNoise api. 713 */ 714int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 715 716/* 717 * Initialization support. 718 */ 719typedef struct { 720 const uint32_t *data; 721 int rows, cols; 722} HAL_INI_ARRAY; 723 724#define HAL_INI_INIT(_ia, _data, _cols) do { \ 725 (_ia)->data = (const uint32_t *)(_data); \ 726 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 727 (_ia)->cols = (_cols); \ 728} while (0) 729#define HAL_INI_VAL(_ia, _r, _c) \ 730 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 731 732/* 733 * OS_DELAY() does a PIO READ on the PCI bus which allows 734 * other cards' DMA reads to complete in the middle of our reset. 735 */ 736#define DMA_YIELD(x) do { \ 737 if ((++(x) % 64) == 0) \ 738 OS_DELAY(1); \ 739} while (0) 740 741#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 742 int r; \ 743 for (r = 0; r < N(regArray); r++) { \ 744 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 745 DMA_YIELD(regWr); \ 746 } \ 747} while (0) 748 749#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 750 int r; \ 751 for (r = 0; r < N(regArray); r++) { \ 752 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 753 DMA_YIELD(regWr); \ 754 } \ 755} while (0) 756 757extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 758 int col, int regWr); 759extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 760 int col); 761extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 762 const uint32_t data[], int regWr); 763 764#define CCK_SIFS_TIME 10 765#define CCK_PREAMBLE_BITS 144 766#define CCK_PLCP_BITS 48 767 768#define OFDM_SIFS_TIME 16 769#define OFDM_PREAMBLE_TIME 20 770#define OFDM_PLCP_BITS 22 771#define OFDM_SYMBOL_TIME 4 772 773#define OFDM_HALF_SIFS_TIME 32 774#define OFDM_HALF_PREAMBLE_TIME 40 775#define OFDM_HALF_PLCP_BITS 22 776#define OFDM_HALF_SYMBOL_TIME 8 777 778#define OFDM_QUARTER_SIFS_TIME 64 779#define OFDM_QUARTER_PREAMBLE_TIME 80 780#define OFDM_QUARTER_PLCP_BITS 22 781#define OFDM_QUARTER_SYMBOL_TIME 16 782 783#define TURBO_SIFS_TIME 8 784#define TURBO_PREAMBLE_TIME 14 785#define TURBO_PLCP_BITS 22 786#define TURBO_SYMBOL_TIME 4 787 788#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 789 790/* Generic EEPROM board value functions */ 791extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 792 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 793extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 794 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 795 uint8_t *pRetVpdList); 796extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 797 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 798 799#endif /* _ATH_AH_INTERAL_H_ */ 800