ah_internal.h revision 219586
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 219586 2011-03-13 05:54:05Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 84 HAL_STATUS *error); 85}; 86#ifndef AH_CHIP 87#define AH_CHIP(_name, _probe, _attach) \ 88static struct ath_hal_chip _name##_chip = { \ 89 .name = #_name, \ 90 .probe = _probe, \ 91 .attach = _attach \ 92}; \ 93OS_DATA_SET(ah_chips, _name##_chip) 94#endif 95 96/* 97 * Each RF backend registers to offer support; this is mostly 98 * used by multi-chip 5212 solutions. Single-chip solutions 99 * have a fixed idea about which RF to use. 100 */ 101struct ath_hal_rf { 102 const char *name; 103 HAL_BOOL (*probe)(struct ath_hal *ah); 104 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 105}; 106#ifndef AH_RF 107#define AH_RF(_name, _probe, _attach) \ 108static struct ath_hal_rf _name##_rf = { \ 109 .name = __STRING(_name), \ 110 .probe = _probe, \ 111 .attach = _attach \ 112}; \ 113OS_DATA_SET(ah_rfs, _name##_rf) 114#endif 115 116struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 117 118/* 119 * Maximum number of internal channels. Entries are per unique 120 * frequency so this might be need to be increased to handle all 121 * usage cases; typically no more than 32 are really needed but 122 * dynamically allocating the data structures is a bit painful 123 * right now. 124 */ 125#ifndef AH_MAXCHAN 126#define AH_MAXCHAN 96 127#endif 128 129/* 130 * Internal per-channel state. These are found 131 * using ic_devdata in the ieee80211_channel. 132 */ 133typedef struct { 134 uint16_t channel; /* h/w frequency, NB: may be mapped */ 135 uint8_t privFlags; 136#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 137#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 138#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 139 uint8_t calValid; /* bitmask of cal types */ 140 int8_t iCoff; 141 int8_t qCoff; 142 int16_t rawNoiseFloor; 143 int16_t noiseFloorAdjust; 144 uint16_t mainSpur; /* cached spur value for this channel */ 145} HAL_CHANNEL_INTERNAL; 146 147/* channel requires noise floor check */ 148#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 149 150/* all full-width channels */ 151#define IEEE80211_CHAN_ALLFULL \ 152 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 153#define IEEE80211_CHAN_ALLTURBOFULL \ 154 (IEEE80211_CHAN_ALLTURBO - \ 155 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 156 157typedef struct { 158 uint32_t halChanSpreadSupport : 1, 159 halSleepAfterBeaconBroken : 1, 160 halCompressSupport : 1, 161 halBurstSupport : 1, 162 halFastFramesSupport : 1, 163 halChapTuningSupport : 1, 164 halTurboGSupport : 1, 165 halTurboPrimeSupport : 1, 166 halMicAesCcmSupport : 1, 167 halMicCkipSupport : 1, 168 halMicTkipSupport : 1, 169 halTkipMicTxRxKeySupport : 1, 170 halCipherAesCcmSupport : 1, 171 halCipherCkipSupport : 1, 172 halCipherTkipSupport : 1, 173 halPSPollBroken : 1, 174 halVEOLSupport : 1, 175 halBssIdMaskSupport : 1, 176 halMcastKeySrchSupport : 1, 177 halTsfAddSupport : 1, 178 halChanHalfRate : 1, 179 halChanQuarterRate : 1, 180 halHTSupport : 1, 181 halRfSilentSupport : 1, 182 halHwPhyCounterSupport : 1, 183 halWowSupport : 1, 184 halWowMatchPatternExact : 1, 185 halAutoSleepSupport : 1, 186 halFastCCSupport : 1, 187 halBtCoexSupport : 1; 188 uint32_t halRxStbcSupport : 1, 189 halTxStbcSupport : 1, 190 halGTTSupport : 1, 191 halCSTSupport : 1, 192 halRifsRxSupport : 1, 193 halRifsTxSupport : 1, 194 halExtChanDfsSupport : 1, 195 halForcePpmSupport : 1, 196 halEnhancedPmSupport : 1, 197 halMbssidAggrSupport : 1, 198 halBssidMatchSupport : 1, 199 hal4kbSplitTransSupport : 1; 200 uint32_t halWirelessModes; 201 uint16_t halTotalQueues; 202 uint16_t halKeyCacheSize; 203 uint16_t halLow5GhzChan, halHigh5GhzChan; 204 uint16_t halLow2GhzChan, halHigh2GhzChan; 205 int halTstampPrecision; 206 int halRtsAggrLimit; 207 uint8_t halTxChainMask; 208 uint8_t halRxChainMask; 209 uint8_t halNumGpioPins; 210 uint8_t halNumAntCfg2GHz; 211 uint8_t halNumAntCfg5GHz; 212 uint32_t halIntrMask; 213 uint8_t halTxStreams; 214 uint8_t halRxStreams; 215} HAL_CAPABILITIES; 216 217struct regDomain; 218 219/* 220 * The ``private area'' follows immediately after the ``public area'' 221 * in the data structure returned by ath_hal_attach. Private data are 222 * used by device-independent code such as the regulatory domain support. 223 * In general, code within the HAL should never depend on data in the 224 * public area. Instead any public data needed internally should be 225 * shadowed here. 226 * 227 * When declaring a device-specific ath_hal data structure this structure 228 * is assumed to at the front; e.g. 229 * 230 * struct ath_hal_5212 { 231 * struct ath_hal_private ah_priv; 232 * ... 233 * }; 234 * 235 * It might be better to manage the method pointers in this structure 236 * using an indirect pointer to a read-only data structure but this would 237 * disallow class-style method overriding. 238 */ 239struct ath_hal_private { 240 struct ath_hal h; /* public area */ 241 242 /* NB: all methods go first to simplify initialization */ 243 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 244 uint16_t channelFlags, 245 uint16_t *lowChannel, uint16_t *highChannel); 246 u_int (*ah_getWirelessModes)(struct ath_hal*); 247 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 248 uint16_t *data); 249 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 250 uint16_t data); 251 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 252 struct ieee80211_channel *); 253 int16_t (*ah_getNfAdjust)(struct ath_hal *, 254 const HAL_CHANNEL_INTERNAL*); 255 void (*ah_getNoiseFloor)(struct ath_hal *, 256 int16_t nfarray[]); 257 258 void *ah_eeprom; /* opaque EEPROM state */ 259 uint16_t ah_eeversion; /* EEPROM version */ 260 void (*ah_eepromDetach)(struct ath_hal *); 261 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 262 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 263 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 264 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 265 const void *args, uint32_t argsize, 266 void **result, uint32_t *resultsize); 267 268 /* 269 * Device revision information. 270 */ 271 uint16_t ah_devid; /* PCI device ID */ 272 uint16_t ah_subvendorid; /* PCI subvendor ID */ 273 uint32_t ah_macVersion; /* MAC version id */ 274 uint16_t ah_macRev; /* MAC revision */ 275 uint16_t ah_phyRev; /* PHY revision */ 276 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 277 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 278 uint8_t ah_ispcie; /* PCIE, special treatment */ 279 280 HAL_OPMODE ah_opmode; /* operating mode from reset */ 281 const struct ieee80211_channel *ah_curchan;/* operating channel */ 282 HAL_CAPABILITIES ah_caps; /* device capabilities */ 283 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 284 int16_t ah_powerLimit; /* tx power cap */ 285 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 286 u_int ah_tpScale; /* tx power scale factor */ 287 uint32_t ah_11nCompat; /* 11n compat controls */ 288 289 /* 290 * State for regulatory domain handling. 291 */ 292 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 293 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 294 u_int ah_nchan; /* valid items in ah_channels */ 295 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 296 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 297 298 uint8_t ah_coverageClass; /* coverage class */ 299 /* 300 * RF Silent handling; setup according to the EEPROM. 301 */ 302 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 303 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 304 /* 305 * Diagnostic support for discriminating HIUERR reports. 306 */ 307 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 308 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 309}; 310 311#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 312 313#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 314 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 315#define ath_hal_getWirelessModes(_ah) \ 316 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 317#define ath_hal_eepromRead(_ah, _off, _data) \ 318 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 319#define ath_hal_eepromWrite(_ah, _off, _data) \ 320 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 321#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 322 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 323#define ath_hal_gpioCfgInput(_ah, _gpio) \ 324 (_ah)->ah_gpioCfgInput(_ah, _gpio) 325#define ath_hal_gpioGet(_ah, _gpio) \ 326 (_ah)->ah_gpioGet(_ah, _gpio) 327#define ath_hal_gpioSet(_ah, _gpio, _val) \ 328 (_ah)->ah_gpioSet(_ah, _gpio, _val) 329#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 330 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 331#define ath_hal_getpowerlimits(_ah, _chan) \ 332 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 333#define ath_hal_getNfAdjust(_ah, _c) \ 334 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 335#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 336 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 337#define ath_hal_configPCIE(_ah, _reset) \ 338 (_ah)->ah_configPCIE(_ah, _reset) 339#define ath_hal_disablePCIE(_ah) \ 340 (_ah)->ah_disablePCIE(_ah) 341#define ath_hal_setInterrupts(_ah, _mask) \ 342 (_ah)->ah_setInterrupts(_ah, _mask) 343 344#define ath_hal_eepromDetach(_ah) do { \ 345 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 346 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 347} while (0) 348#define ath_hal_eepromGet(_ah, _param, _val) \ 349 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 350#define ath_hal_eepromSet(_ah, _param, _val) \ 351 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 352#define ath_hal_eepromGetFlag(_ah, _param) \ 353 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 354#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 355 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 356#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 357 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 358 359#ifndef _NET_IF_IEEE80211_H_ 360/* 361 * Stuff that would naturally come from _ieee80211.h 362 */ 363#define IEEE80211_ADDR_LEN 6 364 365#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 366#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 367#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 368 369#define IEEE80211_CRC_LEN 4 370 371#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 372 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 373#endif /* _NET_IF_IEEE80211_H_ */ 374 375#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 376 377#define INIT_AIFS 2 378#define INIT_CWMIN 15 379#define INIT_CWMIN_11B 31 380#define INIT_CWMAX 1023 381#define INIT_SH_RETRY 10 382#define INIT_LG_RETRY 10 383#define INIT_SSH_RETRY 32 384#define INIT_SLG_RETRY 32 385 386typedef struct { 387 uint32_t tqi_ver; /* HAL TXQ verson */ 388 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 389 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 390 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 391 uint32_t tqi_priority; 392 uint32_t tqi_aifs; /* aifs */ 393 uint32_t tqi_cwmin; /* cwMin */ 394 uint32_t tqi_cwmax; /* cwMax */ 395 uint16_t tqi_shretry; /* frame short retry limit */ 396 uint16_t tqi_lgretry; /* frame long retry limit */ 397 uint32_t tqi_cbrPeriod; 398 uint32_t tqi_cbrOverflowLimit; 399 uint32_t tqi_burstTime; 400 uint32_t tqi_readyTime; 401 uint32_t tqi_physCompBuf; 402 uint32_t tqi_intFlags; /* flags for internal use */ 403} HAL_TX_QUEUE_INFO; 404 405extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 406 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 407extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 408 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 409 410typedef enum { 411 HAL_ANI_PRESENT = 0x1, /* is ANI support present */ 412 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2, /* set level */ 413 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, /* enable/disable */ 414 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8, /* enable/disable */ 415 HAL_ANI_FIRSTEP_LEVEL = 0x10, /* set level */ 416 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20, /* set level */ 417 HAL_ANI_MODE = 0x40, /* 0 => manual, 1 => auto (XXX do not change) */ 418 HAL_ANI_PHYERR_RESET =0x80, /* reset phy error stats */ 419 HAL_ANI_ALL = 0xff 420} HAL_ANI_CMD; 421 422#define HAL_SPUR_VAL_MASK 0x3FFF 423#define HAL_SPUR_CHAN_WIDTH 87 424#define HAL_BIN_WIDTH_BASE_100HZ 3125 425#define HAL_BIN_WIDTH_TURBO_100HZ 6250 426#define HAL_MAX_BINS_ALLOWED 28 427 428#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 429#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 430 431#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 432 433/* 434 * Deduce if the host cpu has big- or litt-endian byte order. 435 */ 436static __inline__ int 437isBigEndian(void) 438{ 439 union { 440 int32_t i; 441 char c[4]; 442 } u; 443 u.i = 1; 444 return (u.c[0] == 0); 445} 446 447/* unalligned little endian access */ 448#define LE_READ_2(p) \ 449 ((uint16_t) \ 450 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 451#define LE_READ_4(p) \ 452 ((uint32_t) \ 453 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 454 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 455 456/* 457 * Register manipulation macros that expect bit field defines 458 * to follow the convention that an _S suffix is appended for 459 * a shift count, while the field mask has no suffix. 460 */ 461#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 462#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 463#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 464 OS_REG_WRITE(_a, _r, \ 465 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 466#define OS_REG_SET_BIT(_a, _r, _f) \ 467 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 468#define OS_REG_CLR_BIT(_a, _r, _f) \ 469 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 470 471/* Analog register writes may require a delay between each one (eg Merlin?) */ 472#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 473 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 474 475/* system-configurable parameters */ 476extern int ath_hal_dma_beacon_response_time; /* in TU's */ 477extern int ath_hal_sw_beacon_response_time; /* in TU's */ 478extern int ath_hal_additional_swba_backoff; /* in TU's */ 479 480/* wait for the register contents to have the specified value */ 481extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 482 uint32_t mask, uint32_t val); 483extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 484 uint32_t mask, uint32_t val, uint32_t timeout); 485 486/* return the first n bits in val reversed */ 487extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 488 489/* printf interfaces */ 490extern void ath_hal_printf(struct ath_hal *, const char*, ...) 491 __printflike(2,3); 492extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 493 __printflike(2, 0); 494extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 495 496/* allocate and free memory */ 497extern void *ath_hal_malloc(size_t); 498extern void ath_hal_free(void *); 499 500/* common debugging interfaces */ 501#ifdef AH_DEBUG 502#include "ah_debug.h" 503extern int ath_hal_debug; 504#define HALDEBUG(_ah, __m, ...) \ 505 do { \ 506 if (ath_hal_debug & (__m)) { \ 507 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \ 508 } \ 509 } while(0); 510 511extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 512 __printflike(3,4); 513#else 514#define HALDEBUG(_ah, __m, _fmt, ...) 515#endif /* AH_DEBUG */ 516 517/* 518 * Register logging definitions shared with ardecode. 519 */ 520#include "ah_decode.h" 521 522/* 523 * Common assertion interface. Note: it is a bad idea to generate 524 * an assertion failure for any recoverable event. Instead catch 525 * the violation and, if possible, fix it up or recover from it; either 526 * with an error return value or a diagnostic messages. System software 527 * does not panic unless the situation is hopeless. 528 */ 529#ifdef AH_ASSERT 530extern void ath_hal_assert_failed(const char* filename, 531 int lineno, const char* msg); 532 533#define HALASSERT(_x) do { \ 534 if (!(_x)) { \ 535 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 536 } \ 537} while (0) 538#else 539#define HALASSERT(_x) 540#endif /* AH_ASSERT */ 541 542/* 543 * Regulatory domain support. 544 */ 545 546/* 547 * Return the max allowed antenna gain and apply any regulatory 548 * domain specific changes. 549 */ 550u_int ath_hal_getantennareduction(struct ath_hal *ah, 551 const struct ieee80211_channel *chan, u_int twiceGain); 552 553/* 554 * Return the test group for the specific channel based on 555 * the current regulatory setup. 556 */ 557u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 558 559/* 560 * Map a public channel definition to the corresponding 561 * internal data structure. This implicitly specifies 562 * whether or not the specified channel is ok to use 563 * based on the current regulatory domain constraints. 564 */ 565#ifndef AH_DEBUG 566static OS_INLINE HAL_CHANNEL_INTERNAL * 567ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 568{ 569 HAL_CHANNEL_INTERNAL *cc; 570 571 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 572 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 573 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 574 return cc; 575} 576#else 577/* NB: non-inline version that checks state */ 578HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 579 const struct ieee80211_channel *); 580#endif /* AH_DEBUG */ 581 582/* 583 * Return the h/w frequency for a channel. This may be 584 * different from ic_freq if this is a GSM device that 585 * takes 2.4GHz frequencies and down-converts them. 586 */ 587static OS_INLINE uint16_t 588ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 589{ 590 return ath_hal_checkchannel(ah, c)->channel; 591} 592 593/* 594 * Convert between microseconds and core system clocks. 595 */ 596extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 597extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 598 599/* 600 * Generic get/set capability support. Each chip overrides 601 * this routine to support chip-specific capabilities. 602 */ 603extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 604 HAL_CAPABILITY_TYPE type, uint32_t capability, 605 uint32_t *result); 606extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 607 HAL_CAPABILITY_TYPE type, uint32_t capability, 608 uint32_t setting, HAL_STATUS *status); 609 610/* The diagnostic codes used to be internally defined here -adrian */ 611#include "ah_diagcodes.h" 612 613enum { 614 HAL_BB_HANG_DFS = 0x0001, 615 HAL_BB_HANG_RIFS = 0x0002, 616 HAL_BB_HANG_RX_CLEAR = 0x0004, 617 HAL_BB_HANG_UNKNOWN = 0x0080, 618 619 HAL_MAC_HANG_SIG1 = 0x0100, 620 HAL_MAC_HANG_SIG2 = 0x0200, 621 HAL_MAC_HANG_UNKNOWN = 0x8000, 622 623 HAL_BB_HANGS = HAL_BB_HANG_DFS 624 | HAL_BB_HANG_RIFS 625 | HAL_BB_HANG_RX_CLEAR 626 | HAL_BB_HANG_UNKNOWN, 627 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 628 | HAL_MAC_HANG_SIG2 629 | HAL_MAC_HANG_UNKNOWN, 630}; 631 632/* 633 * Device revision information. 634 */ 635typedef struct { 636 uint16_t ah_devid; /* PCI device ID */ 637 uint16_t ah_subvendorid; /* PCI subvendor ID */ 638 uint32_t ah_macVersion; /* MAC version id */ 639 uint16_t ah_macRev; /* MAC revision */ 640 uint16_t ah_phyRev; /* PHY revision */ 641 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 642 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 643} HAL_REVS; 644 645/* 646 * Argument payload for HAL_DIAG_SETKEY. 647 */ 648typedef struct { 649 HAL_KEYVAL dk_keyval; 650 uint16_t dk_keyix; /* key index */ 651 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 652 int dk_xor; /* XOR key data */ 653} HAL_DIAG_KEYVAL; 654 655/* 656 * Argument payload for HAL_DIAG_EEWRITE. 657 */ 658typedef struct { 659 uint16_t ee_off; /* eeprom offset */ 660 uint16_t ee_data; /* write data */ 661} HAL_DIAG_EEVAL; 662 663 664typedef struct { 665 u_int offset; /* reg offset */ 666 uint32_t val; /* reg value */ 667} HAL_DIAG_REGVAL; 668 669/* 670 * 11n compatibility tweaks. 671 */ 672#define HAL_DIAG_11N_SERVICES 0x00000003 673#define HAL_DIAG_11N_SERVICES_S 0 674#define HAL_DIAG_11N_TXSTOMP 0x0000000c 675#define HAL_DIAG_11N_TXSTOMP_S 2 676 677typedef struct { 678 int maxNoiseImmunityLevel; /* [0..4] */ 679 int totalSizeDesired[5]; 680 int coarseHigh[5]; 681 int coarseLow[5]; 682 int firpwr[5]; 683 684 int maxSpurImmunityLevel; /* [0..7] */ 685 int cycPwrThr1[8]; 686 687 int maxFirstepLevel; /* [0..2] */ 688 int firstep[3]; 689 690 uint32_t ofdmTrigHigh; 691 uint32_t ofdmTrigLow; 692 int32_t cckTrigHigh; 693 int32_t cckTrigLow; 694 int32_t rssiThrLow; 695 int32_t rssiThrHigh; 696 697 int period; /* update listen period */ 698} HAL_ANI_PARAMS; 699 700extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 701 const void *args, uint32_t argsize, 702 void **result, uint32_t *resultsize); 703 704/* 705 * Setup a h/w rate table for use. 706 */ 707extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 708 709/* 710 * Common routine for implementing getChanNoise api. 711 */ 712int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 713 714/* 715 * Initialization support. 716 */ 717typedef struct { 718 const uint32_t *data; 719 int rows, cols; 720} HAL_INI_ARRAY; 721 722#define HAL_INI_INIT(_ia, _data, _cols) do { \ 723 (_ia)->data = (const uint32_t *)(_data); \ 724 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 725 (_ia)->cols = (_cols); \ 726} while (0) 727#define HAL_INI_VAL(_ia, _r, _c) \ 728 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 729 730/* 731 * OS_DELAY() does a PIO READ on the PCI bus which allows 732 * other cards' DMA reads to complete in the middle of our reset. 733 */ 734#define DMA_YIELD(x) do { \ 735 if ((++(x) % 64) == 0) \ 736 OS_DELAY(1); \ 737} while (0) 738 739#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 740 int r; \ 741 for (r = 0; r < N(regArray); r++) { \ 742 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 743 DMA_YIELD(regWr); \ 744 } \ 745} while (0) 746 747#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 748 int r; \ 749 for (r = 0; r < N(regArray); r++) { \ 750 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 751 DMA_YIELD(regWr); \ 752 } \ 753} while (0) 754 755extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 756 int col, int regWr); 757extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 758 int col); 759extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 760 const uint32_t data[], int regWr); 761 762#define CCK_SIFS_TIME 10 763#define CCK_PREAMBLE_BITS 144 764#define CCK_PLCP_BITS 48 765 766#define OFDM_SIFS_TIME 16 767#define OFDM_PREAMBLE_TIME 20 768#define OFDM_PLCP_BITS 22 769#define OFDM_SYMBOL_TIME 4 770 771#define OFDM_HALF_SIFS_TIME 32 772#define OFDM_HALF_PREAMBLE_TIME 40 773#define OFDM_HALF_PLCP_BITS 22 774#define OFDM_HALF_SYMBOL_TIME 8 775 776#define OFDM_QUARTER_SIFS_TIME 64 777#define OFDM_QUARTER_PREAMBLE_TIME 80 778#define OFDM_QUARTER_PLCP_BITS 22 779#define OFDM_QUARTER_SYMBOL_TIME 16 780 781#define TURBO_SIFS_TIME 8 782#define TURBO_PREAMBLE_TIME 14 783#define TURBO_PLCP_BITS 22 784#define TURBO_SYMBOL_TIME 4 785 786#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 787 788/* Generic EEPROM board value functions */ 789extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList, 790 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 791extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 792 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts, 793 uint8_t *pRetVpdList); 794extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft, 795 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 796 797#endif /* _ATH_AH_INTERAL_H_ */ 798