ah_internal.h revision 218415
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 218415 2011-02-07 21:30:13Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, 84 HAL_STATUS *error); 85}; 86#ifndef AH_CHIP 87#define AH_CHIP(_name, _probe, _attach) \ 88static struct ath_hal_chip _name##_chip = { \ 89 .name = #_name, \ 90 .probe = _probe, \ 91 .attach = _attach \ 92}; \ 93OS_DATA_SET(ah_chips, _name##_chip) 94#endif 95 96/* 97 * Each RF backend registers to offer support; this is mostly 98 * used by multi-chip 5212 solutions. Single-chip solutions 99 * have a fixed idea about which RF to use. 100 */ 101struct ath_hal_rf { 102 const char *name; 103 HAL_BOOL (*probe)(struct ath_hal *ah); 104 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 105}; 106#ifndef AH_RF 107#define AH_RF(_name, _probe, _attach) \ 108static struct ath_hal_rf _name##_rf = { \ 109 .name = __STRING(_name), \ 110 .probe = _probe, \ 111 .attach = _attach \ 112}; \ 113OS_DATA_SET(ah_rfs, _name##_rf) 114#endif 115 116struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 117 118/* 119 * Maximum number of internal channels. Entries are per unique 120 * frequency so this might be need to be increased to handle all 121 * usage cases; typically no more than 32 are really needed but 122 * dynamically allocating the data structures is a bit painful 123 * right now. 124 */ 125#ifndef AH_MAXCHAN 126#define AH_MAXCHAN 96 127#endif 128 129/* 130 * Internal per-channel state. These are found 131 * using ic_devdata in the ieee80211_channel. 132 */ 133typedef struct { 134 uint16_t channel; /* h/w frequency, NB: may be mapped */ 135 uint8_t privFlags; 136#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 137#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 138#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 139 uint8_t calValid; /* bitmask of cal types */ 140 int8_t iCoff; 141 int8_t qCoff; 142 int16_t rawNoiseFloor; 143 int16_t noiseFloorAdjust; 144 uint16_t mainSpur; /* cached spur value for this channel */ 145} HAL_CHANNEL_INTERNAL; 146 147/* channel requires noise floor check */ 148#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 149 150/* all full-width channels */ 151#define IEEE80211_CHAN_ALLFULL \ 152 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 153#define IEEE80211_CHAN_ALLTURBOFULL \ 154 (IEEE80211_CHAN_ALLTURBO - \ 155 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 156 157typedef struct { 158 uint32_t halChanSpreadSupport : 1, 159 halSleepAfterBeaconBroken : 1, 160 halCompressSupport : 1, 161 halBurstSupport : 1, 162 halFastFramesSupport : 1, 163 halChapTuningSupport : 1, 164 halTurboGSupport : 1, 165 halTurboPrimeSupport : 1, 166 halMicAesCcmSupport : 1, 167 halMicCkipSupport : 1, 168 halMicTkipSupport : 1, 169 halTkipMicTxRxKeySupport : 1, 170 halCipherAesCcmSupport : 1, 171 halCipherCkipSupport : 1, 172 halCipherTkipSupport : 1, 173 halPSPollBroken : 1, 174 halVEOLSupport : 1, 175 halBssIdMaskSupport : 1, 176 halMcastKeySrchSupport : 1, 177 halTsfAddSupport : 1, 178 halChanHalfRate : 1, 179 halChanQuarterRate : 1, 180 halHTSupport : 1, 181 halRfSilentSupport : 1, 182 halHwPhyCounterSupport : 1, 183 halWowSupport : 1, 184 halWowMatchPatternExact : 1, 185 halAutoSleepSupport : 1, 186 halFastCCSupport : 1, 187 halBtCoexSupport : 1; 188 uint32_t halRxStbcSupport : 1, 189 halTxStbcSupport : 1, 190 halGTTSupport : 1, 191 halCSTSupport : 1, 192 halRifsRxSupport : 1, 193 halRifsTxSupport : 1, 194 halExtChanDfsSupport : 1, 195 halForcePpmSupport : 1, 196 halEnhancedPmSupport : 1, 197 halMbssidAggrSupport : 1, 198 halBssidMatchSupport : 1; 199 uint32_t halWirelessModes; 200 uint16_t halTotalQueues; 201 uint16_t halKeyCacheSize; 202 uint16_t halLow5GhzChan, halHigh5GhzChan; 203 uint16_t halLow2GhzChan, halHigh2GhzChan; 204 int halTstampPrecision; 205 int halRtsAggrLimit; 206 uint8_t halTxChainMask; 207 uint8_t halRxChainMask; 208 uint8_t halNumGpioPins; 209 uint8_t halNumAntCfg2GHz; 210 uint8_t halNumAntCfg5GHz; 211 uint32_t halIntrMask; 212 uint8_t halTxStreams; 213 uint8_t halRxStreams; 214} HAL_CAPABILITIES; 215 216struct regDomain; 217 218/* 219 * The ``private area'' follows immediately after the ``public area'' 220 * in the data structure returned by ath_hal_attach. Private data are 221 * used by device-independent code such as the regulatory domain support. 222 * In general, code within the HAL should never depend on data in the 223 * public area. Instead any public data needed internally should be 224 * shadowed here. 225 * 226 * When declaring a device-specific ath_hal data structure this structure 227 * is assumed to at the front; e.g. 228 * 229 * struct ath_hal_5212 { 230 * struct ath_hal_private ah_priv; 231 * ... 232 * }; 233 * 234 * It might be better to manage the method pointers in this structure 235 * using an indirect pointer to a read-only data structure but this would 236 * disallow class-style method overriding. 237 */ 238struct ath_hal_private { 239 struct ath_hal h; /* public area */ 240 241 /* NB: all methods go first to simplify initialization */ 242 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 243 uint16_t channelFlags, 244 uint16_t *lowChannel, uint16_t *highChannel); 245 u_int (*ah_getWirelessModes)(struct ath_hal*); 246 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 247 uint16_t *data); 248 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 249 uint16_t data); 250 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 251 struct ieee80211_channel *); 252 int16_t (*ah_getNfAdjust)(struct ath_hal *, 253 const HAL_CHANNEL_INTERNAL*); 254 void (*ah_getNoiseFloor)(struct ath_hal *, 255 int16_t nfarray[]); 256 257 void *ah_eeprom; /* opaque EEPROM state */ 258 uint16_t ah_eeversion; /* EEPROM version */ 259 void (*ah_eepromDetach)(struct ath_hal *); 260 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 261 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 262 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 263 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 264 const void *args, uint32_t argsize, 265 void **result, uint32_t *resultsize); 266 267 /* 268 * Device revision information. 269 */ 270 uint16_t ah_devid; /* PCI device ID */ 271 uint16_t ah_subvendorid; /* PCI subvendor ID */ 272 uint32_t ah_macVersion; /* MAC version id */ 273 uint16_t ah_macRev; /* MAC revision */ 274 uint16_t ah_phyRev; /* PHY revision */ 275 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 276 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 277 uint8_t ah_ispcie; /* PCIE, special treatment */ 278 279 HAL_OPMODE ah_opmode; /* operating mode from reset */ 280 const struct ieee80211_channel *ah_curchan;/* operating channel */ 281 HAL_CAPABILITIES ah_caps; /* device capabilities */ 282 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 283 int16_t ah_powerLimit; /* tx power cap */ 284 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 285 u_int ah_tpScale; /* tx power scale factor */ 286 uint32_t ah_11nCompat; /* 11n compat controls */ 287 288 /* 289 * State for regulatory domain handling. 290 */ 291 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 292 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 293 u_int ah_nchan; /* valid items in ah_channels */ 294 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 295 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 296 297 uint8_t ah_coverageClass; /* coverage class */ 298 /* 299 * RF Silent handling; setup according to the EEPROM. 300 */ 301 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 302 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 303 /* 304 * Diagnostic support for discriminating HIUERR reports. 305 */ 306 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 307 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 308}; 309 310#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 311 312#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 313 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 314#define ath_hal_getWirelessModes(_ah) \ 315 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 316#define ath_hal_eepromRead(_ah, _off, _data) \ 317 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 318#define ath_hal_eepromWrite(_ah, _off, _data) \ 319 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 320#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 321 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 322#define ath_hal_gpioCfgInput(_ah, _gpio) \ 323 (_ah)->ah_gpioCfgInput(_ah, _gpio) 324#define ath_hal_gpioGet(_ah, _gpio) \ 325 (_ah)->ah_gpioGet(_ah, _gpio) 326#define ath_hal_gpioSet(_ah, _gpio, _val) \ 327 (_ah)->ah_gpioSet(_ah, _gpio, _val) 328#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 329 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 330#define ath_hal_getpowerlimits(_ah, _chan) \ 331 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 332#define ath_hal_getNfAdjust(_ah, _c) \ 333 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 334#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 335 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 336#define ath_hal_configPCIE(_ah, _reset) \ 337 (_ah)->ah_configPCIE(_ah, _reset) 338#define ath_hal_disablePCIE(_ah) \ 339 (_ah)->ah_disablePCIE(_ah) 340#define ath_hal_setInterrupts(_ah, _mask) \ 341 (_ah)->ah_setInterrupts(_ah, _mask) 342 343#define ath_hal_eepromDetach(_ah) do { \ 344 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 345 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 346} while (0) 347#define ath_hal_eepromGet(_ah, _param, _val) \ 348 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 349#define ath_hal_eepromSet(_ah, _param, _val) \ 350 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 351#define ath_hal_eepromGetFlag(_ah, _param) \ 352 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 353#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 354 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 355#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 356 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 357 358#ifndef _NET_IF_IEEE80211_H_ 359/* 360 * Stuff that would naturally come from _ieee80211.h 361 */ 362#define IEEE80211_ADDR_LEN 6 363 364#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 365#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 366#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 367 368#define IEEE80211_CRC_LEN 4 369 370#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 371 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 372#endif /* _NET_IF_IEEE80211_H_ */ 373 374#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 375 376#define INIT_AIFS 2 377#define INIT_CWMIN 15 378#define INIT_CWMIN_11B 31 379#define INIT_CWMAX 1023 380#define INIT_SH_RETRY 10 381#define INIT_LG_RETRY 10 382#define INIT_SSH_RETRY 32 383#define INIT_SLG_RETRY 32 384 385typedef struct { 386 uint32_t tqi_ver; /* HAL TXQ verson */ 387 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 388 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 389 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 390 uint32_t tqi_priority; 391 uint32_t tqi_aifs; /* aifs */ 392 uint32_t tqi_cwmin; /* cwMin */ 393 uint32_t tqi_cwmax; /* cwMax */ 394 uint16_t tqi_shretry; /* frame short retry limit */ 395 uint16_t tqi_lgretry; /* frame long retry limit */ 396 uint32_t tqi_cbrPeriod; 397 uint32_t tqi_cbrOverflowLimit; 398 uint32_t tqi_burstTime; 399 uint32_t tqi_readyTime; 400 uint32_t tqi_physCompBuf; 401 uint32_t tqi_intFlags; /* flags for internal use */ 402} HAL_TX_QUEUE_INFO; 403 404extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 405 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 406extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 407 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 408 409typedef enum { 410 HAL_ANI_PRESENT, /* is ANI support present */ 411 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 412 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 413 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 414 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 415 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 416 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 417 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 418} HAL_ANI_CMD; 419 420#define HAL_SPUR_VAL_MASK 0x3FFF 421#define HAL_SPUR_CHAN_WIDTH 87 422#define HAL_BIN_WIDTH_BASE_100HZ 3125 423#define HAL_BIN_WIDTH_TURBO_100HZ 6250 424#define HAL_MAX_BINS_ALLOWED 28 425 426#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 427#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 428 429#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 430 431/* 432 * Deduce if the host cpu has big- or litt-endian byte order. 433 */ 434static __inline__ int 435isBigEndian(void) 436{ 437 union { 438 int32_t i; 439 char c[4]; 440 } u; 441 u.i = 1; 442 return (u.c[0] == 0); 443} 444 445/* unalligned little endian access */ 446#define LE_READ_2(p) \ 447 ((uint16_t) \ 448 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 449#define LE_READ_4(p) \ 450 ((uint32_t) \ 451 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 452 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 453 454/* 455 * Register manipulation macros that expect bit field defines 456 * to follow the convention that an _S suffix is appended for 457 * a shift count, while the field mask has no suffix. 458 */ 459#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 460#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 461#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 462 OS_REG_WRITE(_a, _r, \ 463 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 464#define OS_REG_SET_BIT(_a, _r, _f) \ 465 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 466#define OS_REG_CLR_BIT(_a, _r, _f) \ 467 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 468 469/* Analog register writes may require a delay between each one (eg Merlin?) */ 470#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \ 471 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0) 472 473/* system-configurable parameters */ 474extern int ath_hal_dma_beacon_response_time; /* in TU's */ 475extern int ath_hal_sw_beacon_response_time; /* in TU's */ 476extern int ath_hal_additional_swba_backoff; /* in TU's */ 477 478/* wait for the register contents to have the specified value */ 479extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 480 uint32_t mask, uint32_t val); 481extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg, 482 uint32_t mask, uint32_t val, uint32_t timeout); 483 484/* return the first n bits in val reversed */ 485extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 486 487/* printf interfaces */ 488extern void ath_hal_printf(struct ath_hal *, const char*, ...) 489 __printflike(2,3); 490extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 491 __printflike(2, 0); 492extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 493 494/* allocate and free memory */ 495extern void *ath_hal_malloc(size_t); 496extern void ath_hal_free(void *); 497 498/* common debugging interfaces */ 499#ifdef AH_DEBUG 500#include "ah_debug.h" 501extern int ath_hal_debug; 502extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 503 __printflike(3,4); 504#else 505#define HALDEBUG(_ah, __m, _fmt, ...) 506#endif /* AH_DEBUG */ 507 508/* 509 * Register logging definitions shared with ardecode. 510 */ 511#include "ah_decode.h" 512 513/* 514 * Common assertion interface. Note: it is a bad idea to generate 515 * an assertion failure for any recoverable event. Instead catch 516 * the violation and, if possible, fix it up or recover from it; either 517 * with an error return value or a diagnostic messages. System software 518 * does not panic unless the situation is hopeless. 519 */ 520#ifdef AH_ASSERT 521extern void ath_hal_assert_failed(const char* filename, 522 int lineno, const char* msg); 523 524#define HALASSERT(_x) do { \ 525 if (!(_x)) { \ 526 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 527 } \ 528} while (0) 529#else 530#define HALASSERT(_x) 531#endif /* AH_ASSERT */ 532 533/* 534 * Regulatory domain support. 535 */ 536 537/* 538 * Return the max allowed antenna gain and apply any regulatory 539 * domain specific changes. 540 */ 541u_int ath_hal_getantennareduction(struct ath_hal *ah, 542 const struct ieee80211_channel *chan, u_int twiceGain); 543 544/* 545 * Return the test group for the specific channel based on 546 * the current regulatory setup. 547 */ 548u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 549 550/* 551 * Map a public channel definition to the corresponding 552 * internal data structure. This implicitly specifies 553 * whether or not the specified channel is ok to use 554 * based on the current regulatory domain constraints. 555 */ 556#ifndef AH_DEBUG 557static OS_INLINE HAL_CHANNEL_INTERNAL * 558ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 559{ 560 HAL_CHANNEL_INTERNAL *cc; 561 562 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 563 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 564 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 565 return cc; 566} 567#else 568/* NB: non-inline version that checks state */ 569HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 570 const struct ieee80211_channel *); 571#endif /* AH_DEBUG */ 572 573/* 574 * Return the h/w frequency for a channel. This may be 575 * different from ic_freq if this is a GSM device that 576 * takes 2.4GHz frequencies and down-converts them. 577 */ 578static OS_INLINE uint16_t 579ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 580{ 581 return ath_hal_checkchannel(ah, c)->channel; 582} 583 584/* 585 * Convert between microseconds and core system clocks. 586 */ 587extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 588extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 589 590/* 591 * Generic get/set capability support. Each chip overrides 592 * this routine to support chip-specific capabilities. 593 */ 594extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 595 HAL_CAPABILITY_TYPE type, uint32_t capability, 596 uint32_t *result); 597extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 598 HAL_CAPABILITY_TYPE type, uint32_t capability, 599 uint32_t setting, HAL_STATUS *status); 600 601/* The diagnostic codes used to be internally defined here -adrian */ 602#include "ah_diagcodes.h" 603 604enum { 605 HAL_BB_HANG_DFS = 0x0001, 606 HAL_BB_HANG_RIFS = 0x0002, 607 HAL_BB_HANG_RX_CLEAR = 0x0004, 608 HAL_BB_HANG_UNKNOWN = 0x0080, 609 610 HAL_MAC_HANG_SIG1 = 0x0100, 611 HAL_MAC_HANG_SIG2 = 0x0200, 612 HAL_MAC_HANG_UNKNOWN = 0x8000, 613 614 HAL_BB_HANGS = HAL_BB_HANG_DFS 615 | HAL_BB_HANG_RIFS 616 | HAL_BB_HANG_RX_CLEAR 617 | HAL_BB_HANG_UNKNOWN, 618 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 619 | HAL_MAC_HANG_SIG2 620 | HAL_MAC_HANG_UNKNOWN, 621}; 622 623/* 624 * Device revision information. 625 */ 626typedef struct { 627 uint16_t ah_devid; /* PCI device ID */ 628 uint16_t ah_subvendorid; /* PCI subvendor ID */ 629 uint32_t ah_macVersion; /* MAC version id */ 630 uint16_t ah_macRev; /* MAC revision */ 631 uint16_t ah_phyRev; /* PHY revision */ 632 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 633 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 634} HAL_REVS; 635 636/* 637 * Argument payload for HAL_DIAG_SETKEY. 638 */ 639typedef struct { 640 HAL_KEYVAL dk_keyval; 641 uint16_t dk_keyix; /* key index */ 642 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 643 int dk_xor; /* XOR key data */ 644} HAL_DIAG_KEYVAL; 645 646/* 647 * Argument payload for HAL_DIAG_EEWRITE. 648 */ 649typedef struct { 650 uint16_t ee_off; /* eeprom offset */ 651 uint16_t ee_data; /* write data */ 652} HAL_DIAG_EEVAL; 653 654 655typedef struct { 656 u_int offset; /* reg offset */ 657 uint32_t val; /* reg value */ 658} HAL_DIAG_REGVAL; 659 660/* 661 * 11n compatibility tweaks. 662 */ 663#define HAL_DIAG_11N_SERVICES 0x00000003 664#define HAL_DIAG_11N_SERVICES_S 0 665#define HAL_DIAG_11N_TXSTOMP 0x0000000c 666#define HAL_DIAG_11N_TXSTOMP_S 2 667 668typedef struct { 669 int maxNoiseImmunityLevel; /* [0..4] */ 670 int totalSizeDesired[5]; 671 int coarseHigh[5]; 672 int coarseLow[5]; 673 int firpwr[5]; 674 675 int maxSpurImmunityLevel; /* [0..7] */ 676 int cycPwrThr1[8]; 677 678 int maxFirstepLevel; /* [0..2] */ 679 int firstep[3]; 680 681 uint32_t ofdmTrigHigh; 682 uint32_t ofdmTrigLow; 683 int32_t cckTrigHigh; 684 int32_t cckTrigLow; 685 int32_t rssiThrLow; 686 int32_t rssiThrHigh; 687 688 int period; /* update listen period */ 689} HAL_ANI_PARAMS; 690 691extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 692 const void *args, uint32_t argsize, 693 void **result, uint32_t *resultsize); 694 695/* 696 * Setup a h/w rate table for use. 697 */ 698extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 699 700/* 701 * Common routine for implementing getChanNoise api. 702 */ 703int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 704 705/* 706 * Initialization support. 707 */ 708typedef struct { 709 const uint32_t *data; 710 int rows, cols; 711} HAL_INI_ARRAY; 712 713#define HAL_INI_INIT(_ia, _data, _cols) do { \ 714 (_ia)->data = (const uint32_t *)(_data); \ 715 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 716 (_ia)->cols = (_cols); \ 717} while (0) 718#define HAL_INI_VAL(_ia, _r, _c) \ 719 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 720 721/* 722 * OS_DELAY() does a PIO READ on the PCI bus which allows 723 * other cards' DMA reads to complete in the middle of our reset. 724 */ 725#define DMA_YIELD(x) do { \ 726 if ((++(x) % 64) == 0) \ 727 OS_DELAY(1); \ 728} while (0) 729 730#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 731 int r; \ 732 for (r = 0; r < N(regArray); r++) { \ 733 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 734 DMA_YIELD(regWr); \ 735 } \ 736} while (0) 737 738#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 739 int r; \ 740 for (r = 0; r < N(regArray); r++) { \ 741 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 742 DMA_YIELD(regWr); \ 743 } \ 744} while (0) 745 746extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 747 int col, int regWr); 748extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 749 int col); 750extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 751 const uint32_t data[], int regWr); 752 753#define CCK_SIFS_TIME 10 754#define CCK_PREAMBLE_BITS 144 755#define CCK_PLCP_BITS 48 756 757#define OFDM_SIFS_TIME 16 758#define OFDM_PREAMBLE_TIME 20 759#define OFDM_PLCP_BITS 22 760#define OFDM_SYMBOL_TIME 4 761 762#define OFDM_HALF_SIFS_TIME 32 763#define OFDM_HALF_PREAMBLE_TIME 40 764#define OFDM_HALF_PLCP_BITS 22 765#define OFDM_HALF_SYMBOL_TIME 8 766 767#define OFDM_QUARTER_SIFS_TIME 64 768#define OFDM_QUARTER_PREAMBLE_TIME 80 769#define OFDM_QUARTER_PLCP_BITS 22 770#define OFDM_QUARTER_SYMBOL_TIME 16 771 772#define TURBO_SIFS_TIME 8 773#define TURBO_PREAMBLE_TIME 14 774#define TURBO_PLCP_BITS 22 775#define TURBO_SYMBOL_TIME 4 776 777#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 778#endif /* _ATH_AH_INTERAL_H_ */ 779