ah_internal.h revision 217618
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 217618 2011-01-20 04:57:26Z adrian $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84}; 85#ifndef AH_CHIP 86#define AH_CHIP(_name, _probe, _attach) \ 87static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91}; \ 92OS_DATA_SET(ah_chips, _name##_chip) 93#endif 94 95/* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104}; 105#ifndef AH_RF 106#define AH_RF(_name, _probe, _attach) \ 107static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111}; \ 112OS_DATA_SET(ah_rfs, _name##_rf) 113#endif 114 115struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117/* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124#ifndef AH_MAXCHAN 125#define AH_MAXCHAN 96 126#endif 127 128/* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144} HAL_CHANNEL_INTERNAL; 145 146/* channel requires noise floor check */ 147#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149/* all full-width channels */ 150#define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152#define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1, 197 halBssidMatchSupport : 1; 198 uint32_t halWirelessModes; 199 uint16_t halTotalQueues; 200 uint16_t halKeyCacheSize; 201 uint16_t halLow5GhzChan, halHigh5GhzChan; 202 uint16_t halLow2GhzChan, halHigh2GhzChan; 203 int halTstampPrecision; 204 int halRtsAggrLimit; 205 uint8_t halTxChainMask; 206 uint8_t halRxChainMask; 207 uint8_t halNumGpioPins; 208 uint8_t halNumAntCfg2GHz; 209 uint8_t halNumAntCfg5GHz; 210 uint32_t halIntrMask; 211} HAL_CAPABILITIES; 212 213struct regDomain; 214 215/* 216 * The ``private area'' follows immediately after the ``public area'' 217 * in the data structure returned by ath_hal_attach. Private data are 218 * used by device-independent code such as the regulatory domain support. 219 * In general, code within the HAL should never depend on data in the 220 * public area. Instead any public data needed internally should be 221 * shadowed here. 222 * 223 * When declaring a device-specific ath_hal data structure this structure 224 * is assumed to at the front; e.g. 225 * 226 * struct ath_hal_5212 { 227 * struct ath_hal_private ah_priv; 228 * ... 229 * }; 230 * 231 * It might be better to manage the method pointers in this structure 232 * using an indirect pointer to a read-only data structure but this would 233 * disallow class-style method overriding. 234 */ 235struct ath_hal_private { 236 struct ath_hal h; /* public area */ 237 238 /* NB: all methods go first to simplify initialization */ 239 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 240 uint16_t channelFlags, 241 uint16_t *lowChannel, uint16_t *highChannel); 242 u_int (*ah_getWirelessModes)(struct ath_hal*); 243 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 244 uint16_t *data); 245 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 246 uint16_t data); 247 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 248 struct ieee80211_channel *); 249 int16_t (*ah_getNfAdjust)(struct ath_hal *, 250 const HAL_CHANNEL_INTERNAL*); 251 void (*ah_getNoiseFloor)(struct ath_hal *, 252 int16_t nfarray[]); 253 254 void *ah_eeprom; /* opaque EEPROM state */ 255 uint16_t ah_eeversion; /* EEPROM version */ 256 void (*ah_eepromDetach)(struct ath_hal *); 257 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 258 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 259 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 260 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 261 const void *args, uint32_t argsize, 262 void **result, uint32_t *resultsize); 263 264 /* 265 * Device revision information. 266 */ 267 uint16_t ah_devid; /* PCI device ID */ 268 uint16_t ah_subvendorid; /* PCI subvendor ID */ 269 uint32_t ah_macVersion; /* MAC version id */ 270 uint16_t ah_macRev; /* MAC revision */ 271 uint16_t ah_phyRev; /* PHY revision */ 272 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 273 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 274 uint8_t ah_ispcie; /* PCIE, special treatment */ 275 276 HAL_OPMODE ah_opmode; /* operating mode from reset */ 277 const struct ieee80211_channel *ah_curchan;/* operating channel */ 278 HAL_CAPABILITIES ah_caps; /* device capabilities */ 279 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 280 int16_t ah_powerLimit; /* tx power cap */ 281 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 282 u_int ah_tpScale; /* tx power scale factor */ 283 uint32_t ah_11nCompat; /* 11n compat controls */ 284 285 /* 286 * State for regulatory domain handling. 287 */ 288 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 289 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 290 u_int ah_nchan; /* valid items in ah_channels */ 291 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 292 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 293 294 uint8_t ah_coverageClass; /* coverage class */ 295 /* 296 * RF Silent handling; setup according to the EEPROM. 297 */ 298 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 299 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 300 /* 301 * Diagnostic support for discriminating HIUERR reports. 302 */ 303 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 304 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 305}; 306 307#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 308 309#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 310 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 311#define ath_hal_getWirelessModes(_ah) \ 312 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 313#define ath_hal_eepromRead(_ah, _off, _data) \ 314 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 315#define ath_hal_eepromWrite(_ah, _off, _data) \ 316 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 317#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 318 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 319#define ath_hal_gpioCfgInput(_ah, _gpio) \ 320 (_ah)->ah_gpioCfgInput(_ah, _gpio) 321#define ath_hal_gpioGet(_ah, _gpio) \ 322 (_ah)->ah_gpioGet(_ah, _gpio) 323#define ath_hal_gpioSet(_ah, _gpio, _val) \ 324 (_ah)->ah_gpioSet(_ah, _gpio, _val) 325#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 326 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 327#define ath_hal_getpowerlimits(_ah, _chan) \ 328 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 329#define ath_hal_getNfAdjust(_ah, _c) \ 330 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 331#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 332 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 333#define ath_hal_configPCIE(_ah, _reset) \ 334 (_ah)->ah_configPCIE(_ah, _reset) 335#define ath_hal_disablePCIE(_ah) \ 336 (_ah)->ah_disablePCIE(_ah) 337#define ath_hal_setInterrupts(_ah, _mask) \ 338 (_ah)->ah_setInterrupts(_ah, _mask) 339 340#define ath_hal_eepromDetach(_ah) do { \ 341 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 342 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 343} while (0) 344#define ath_hal_eepromGet(_ah, _param, _val) \ 345 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 346#define ath_hal_eepromSet(_ah, _param, _val) \ 347 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 348#define ath_hal_eepromGetFlag(_ah, _param) \ 349 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 350#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 351 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 352#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 353 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 354 355#ifndef _NET_IF_IEEE80211_H_ 356/* 357 * Stuff that would naturally come from _ieee80211.h 358 */ 359#define IEEE80211_ADDR_LEN 6 360 361#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 362#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 363#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 364 365#define IEEE80211_CRC_LEN 4 366 367#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 368 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 369#endif /* _NET_IF_IEEE80211_H_ */ 370 371#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 372 373#define INIT_AIFS 2 374#define INIT_CWMIN 15 375#define INIT_CWMIN_11B 31 376#define INIT_CWMAX 1023 377#define INIT_SH_RETRY 10 378#define INIT_LG_RETRY 10 379#define INIT_SSH_RETRY 32 380#define INIT_SLG_RETRY 32 381 382typedef struct { 383 uint32_t tqi_ver; /* HAL TXQ verson */ 384 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 385 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 386 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 387 uint32_t tqi_priority; 388 uint32_t tqi_aifs; /* aifs */ 389 uint32_t tqi_cwmin; /* cwMin */ 390 uint32_t tqi_cwmax; /* cwMax */ 391 uint16_t tqi_shretry; /* frame short retry limit */ 392 uint16_t tqi_lgretry; /* frame long retry limit */ 393 uint32_t tqi_cbrPeriod; 394 uint32_t tqi_cbrOverflowLimit; 395 uint32_t tqi_burstTime; 396 uint32_t tqi_readyTime; 397 uint32_t tqi_physCompBuf; 398 uint32_t tqi_intFlags; /* flags for internal use */ 399} HAL_TX_QUEUE_INFO; 400 401extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 402 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 403extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 404 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 405 406typedef enum { 407 HAL_ANI_PRESENT, /* is ANI support present */ 408 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 409 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 410 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 411 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 412 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 413 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 414 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 415} HAL_ANI_CMD; 416 417#define HAL_SPUR_VAL_MASK 0x3FFF 418#define HAL_SPUR_CHAN_WIDTH 87 419#define HAL_BIN_WIDTH_BASE_100HZ 3125 420#define HAL_BIN_WIDTH_TURBO_100HZ 6250 421#define HAL_MAX_BINS_ALLOWED 28 422 423#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 424#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 425 426#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 427 428/* 429 * Deduce if the host cpu has big- or litt-endian byte order. 430 */ 431static __inline__ int 432isBigEndian(void) 433{ 434 union { 435 int32_t i; 436 char c[4]; 437 } u; 438 u.i = 1; 439 return (u.c[0] == 0); 440} 441 442/* unalligned little endian access */ 443#define LE_READ_2(p) \ 444 ((uint16_t) \ 445 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 446#define LE_READ_4(p) \ 447 ((uint32_t) \ 448 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 449 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 450 451/* 452 * Register manipulation macros that expect bit field defines 453 * to follow the convention that an _S suffix is appended for 454 * a shift count, while the field mask has no suffix. 455 */ 456#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 457#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 458#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 459 OS_REG_WRITE(_a, _r, \ 460 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 461#define OS_REG_SET_BIT(_a, _r, _f) \ 462 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 463#define OS_REG_CLR_BIT(_a, _r, _f) \ 464 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 465 466/* system-configurable parameters */ 467extern int ath_hal_dma_beacon_response_time; /* in TU's */ 468extern int ath_hal_sw_beacon_response_time; /* in TU's */ 469extern int ath_hal_additional_swba_backoff; /* in TU's */ 470 471/* wait for the register contents to have the specified value */ 472extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 473 uint32_t mask, uint32_t val); 474 475/* return the first n bits in val reversed */ 476extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 477 478/* printf interfaces */ 479extern void ath_hal_printf(struct ath_hal *, const char*, ...) 480 __printflike(2,3); 481extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 482 __printflike(2, 0); 483extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 484 485/* allocate and free memory */ 486extern void *ath_hal_malloc(size_t); 487extern void ath_hal_free(void *); 488 489/* common debugging interfaces */ 490#ifdef AH_DEBUG 491#include "ah_debug.h" 492extern int ath_hal_debug; 493extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 494 __printflike(3,4); 495#else 496#define HALDEBUG(_ah, __m, _fmt, ...) 497#endif /* AH_DEBUG */ 498 499/* 500 * Register logging definitions shared with ardecode. 501 */ 502#include "ah_decode.h" 503 504/* 505 * Common assertion interface. Note: it is a bad idea to generate 506 * an assertion failure for any recoverable event. Instead catch 507 * the violation and, if possible, fix it up or recover from it; either 508 * with an error return value or a diagnostic messages. System software 509 * does not panic unless the situation is hopeless. 510 */ 511#ifdef AH_ASSERT 512extern void ath_hal_assert_failed(const char* filename, 513 int lineno, const char* msg); 514 515#define HALASSERT(_x) do { \ 516 if (!(_x)) { \ 517 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 518 } \ 519} while (0) 520#else 521#define HALASSERT(_x) 522#endif /* AH_ASSERT */ 523 524/* 525 * Regulatory domain support. 526 */ 527 528/* 529 * Return the max allowed antenna gain and apply any regulatory 530 * domain specific changes. 531 */ 532u_int ath_hal_getantennareduction(struct ath_hal *ah, 533 const struct ieee80211_channel *chan, u_int twiceGain); 534 535/* 536 * Return the test group for the specific channel based on 537 * the current regulatory setup. 538 */ 539u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 540 541/* 542 * Map a public channel definition to the corresponding 543 * internal data structure. This implicitly specifies 544 * whether or not the specified channel is ok to use 545 * based on the current regulatory domain constraints. 546 */ 547#ifndef AH_DEBUG 548static OS_INLINE HAL_CHANNEL_INTERNAL * 549ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 550{ 551 HAL_CHANNEL_INTERNAL *cc; 552 553 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 554 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 555 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 556 return cc; 557} 558#else 559/* NB: non-inline version that checks state */ 560HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 561 const struct ieee80211_channel *); 562#endif /* AH_DEBUG */ 563 564/* 565 * Return the h/w frequency for a channel. This may be 566 * different from ic_freq if this is a GSM device that 567 * takes 2.4GHz frequencies and down-converts them. 568 */ 569static OS_INLINE uint16_t 570ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 571{ 572 return ath_hal_checkchannel(ah, c)->channel; 573} 574 575/* 576 * Convert between microseconds and core system clocks. 577 */ 578extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 579extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 580 581/* 582 * Generic get/set capability support. Each chip overrides 583 * this routine to support chip-specific capabilities. 584 */ 585extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 586 HAL_CAPABILITY_TYPE type, uint32_t capability, 587 uint32_t *result); 588extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 589 HAL_CAPABILITY_TYPE type, uint32_t capability, 590 uint32_t setting, HAL_STATUS *status); 591 592/* The diagnostic codes used to be internally defined here -adrian */ 593#include "ah_diagcodes.h" 594 595enum { 596 HAL_BB_HANG_DFS = 0x0001, 597 HAL_BB_HANG_RIFS = 0x0002, 598 HAL_BB_HANG_RX_CLEAR = 0x0004, 599 HAL_BB_HANG_UNKNOWN = 0x0080, 600 601 HAL_MAC_HANG_SIG1 = 0x0100, 602 HAL_MAC_HANG_SIG2 = 0x0200, 603 HAL_MAC_HANG_UNKNOWN = 0x8000, 604 605 HAL_BB_HANGS = HAL_BB_HANG_DFS 606 | HAL_BB_HANG_RIFS 607 | HAL_BB_HANG_RX_CLEAR 608 | HAL_BB_HANG_UNKNOWN, 609 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 610 | HAL_MAC_HANG_SIG2 611 | HAL_MAC_HANG_UNKNOWN, 612}; 613 614/* 615 * Device revision information. 616 */ 617typedef struct { 618 uint16_t ah_devid; /* PCI device ID */ 619 uint16_t ah_subvendorid; /* PCI subvendor ID */ 620 uint32_t ah_macVersion; /* MAC version id */ 621 uint16_t ah_macRev; /* MAC revision */ 622 uint16_t ah_phyRev; /* PHY revision */ 623 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 624 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 625} HAL_REVS; 626 627/* 628 * Argument payload for HAL_DIAG_SETKEY. 629 */ 630typedef struct { 631 HAL_KEYVAL dk_keyval; 632 uint16_t dk_keyix; /* key index */ 633 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 634 int dk_xor; /* XOR key data */ 635} HAL_DIAG_KEYVAL; 636 637/* 638 * Argument payload for HAL_DIAG_EEWRITE. 639 */ 640typedef struct { 641 uint16_t ee_off; /* eeprom offset */ 642 uint16_t ee_data; /* write data */ 643} HAL_DIAG_EEVAL; 644 645 646typedef struct { 647 u_int offset; /* reg offset */ 648 uint32_t val; /* reg value */ 649} HAL_DIAG_REGVAL; 650 651/* 652 * 11n compatibility tweaks. 653 */ 654#define HAL_DIAG_11N_SERVICES 0x00000003 655#define HAL_DIAG_11N_SERVICES_S 0 656#define HAL_DIAG_11N_TXSTOMP 0x0000000c 657#define HAL_DIAG_11N_TXSTOMP_S 2 658 659typedef struct { 660 int maxNoiseImmunityLevel; /* [0..4] */ 661 int totalSizeDesired[5]; 662 int coarseHigh[5]; 663 int coarseLow[5]; 664 int firpwr[5]; 665 666 int maxSpurImmunityLevel; /* [0..7] */ 667 int cycPwrThr1[8]; 668 669 int maxFirstepLevel; /* [0..2] */ 670 int firstep[3]; 671 672 uint32_t ofdmTrigHigh; 673 uint32_t ofdmTrigLow; 674 int32_t cckTrigHigh; 675 int32_t cckTrigLow; 676 int32_t rssiThrLow; 677 int32_t rssiThrHigh; 678 679 int period; /* update listen period */ 680} HAL_ANI_PARAMS; 681 682extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 683 const void *args, uint32_t argsize, 684 void **result, uint32_t *resultsize); 685 686/* 687 * Setup a h/w rate table for use. 688 */ 689extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 690 691/* 692 * Common routine for implementing getChanNoise api. 693 */ 694int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 695 696/* 697 * Initialization support. 698 */ 699typedef struct { 700 const uint32_t *data; 701 int rows, cols; 702} HAL_INI_ARRAY; 703 704#define HAL_INI_INIT(_ia, _data, _cols) do { \ 705 (_ia)->data = (const uint32_t *)(_data); \ 706 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 707 (_ia)->cols = (_cols); \ 708} while (0) 709#define HAL_INI_VAL(_ia, _r, _c) \ 710 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 711 712/* 713 * OS_DELAY() does a PIO READ on the PCI bus which allows 714 * other cards' DMA reads to complete in the middle of our reset. 715 */ 716#define DMA_YIELD(x) do { \ 717 if ((++(x) % 64) == 0) \ 718 OS_DELAY(1); \ 719} while (0) 720 721#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 722 int r; \ 723 for (r = 0; r < N(regArray); r++) { \ 724 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 725 DMA_YIELD(regWr); \ 726 } \ 727} while (0) 728 729#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 730 int r; \ 731 for (r = 0; r < N(regArray); r++) { \ 732 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 733 DMA_YIELD(regWr); \ 734 } \ 735} while (0) 736 737extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 738 int col, int regWr); 739extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 740 int col); 741extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 742 const uint32_t data[], int regWr); 743 744#define CCK_SIFS_TIME 10 745#define CCK_PREAMBLE_BITS 144 746#define CCK_PLCP_BITS 48 747 748#define OFDM_SIFS_TIME 16 749#define OFDM_PREAMBLE_TIME 20 750#define OFDM_PLCP_BITS 22 751#define OFDM_SYMBOL_TIME 4 752 753#define OFDM_HALF_SIFS_TIME 32 754#define OFDM_HALF_PREAMBLE_TIME 40 755#define OFDM_HALF_PLCP_BITS 22 756#define OFDM_HALF_SYMBOL_TIME 8 757 758#define OFDM_QUARTER_SIFS_TIME 64 759#define OFDM_QUARTER_PREAMBLE_TIME 80 760#define OFDM_QUARTER_PLCP_BITS 22 761#define OFDM_QUARTER_SYMBOL_TIME 16 762 763#define TURBO_SIFS_TIME 8 764#define TURBO_PREAMBLE_TIME 14 765#define TURBO_PLCP_BITS 22 766#define TURBO_SYMBOL_TIME 4 767 768#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 769#endif /* _ATH_AH_INTERAL_H_ */ 770