ah_internal.h revision 204579
1251875Speter/* 2251875Speter * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3251875Speter * Copyright (c) 2002-2008 Atheros Communications, Inc. 4251875Speter * 5251875Speter * Permission to use, copy, modify, and/or distribute this software for any 6251875Speter * purpose with or without fee is hereby granted, provided that the above 7251875Speter * copyright notice and this permission notice appear in all copies. 8251875Speter * 9251875Speter * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10251875Speter * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11251875Speter * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12251875Speter * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13251875Speter * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14251875Speter * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15251875Speter * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16251875Speter * 17251875Speter * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 204579 2010-03-02 12:59:42Z rpaulo $ 18251875Speter */ 19251875Speter#ifndef _ATH_AH_INTERAL_H_ 20251875Speter#define _ATH_AH_INTERAL_H_ 21251875Speter/* 22251875Speter * Atheros Device Hardware Access Layer (HAL). 23251875Speter * 24251875Speter * Internal definitions. 25251875Speter */ 26251875Speter#define AH_NULL 0 27251875Speter#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28251875Speter#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29251875Speter 30251875Speter#include <net80211/_ieee80211.h> 31251875Speter 32251875Speter#ifndef NBBY 33251875Speter#define NBBY 8 /* number of bits/byte */ 34251875Speter#endif 35251875Speter 36251875Speter#ifndef roundup 37251875Speter#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38251875Speter#endif 39251875Speter#ifndef howmany 40251875Speter#define howmany(x, y) (((x)+((y)-1))/(y)) 41251875Speter#endif 42251875Speter 43251875Speter#ifndef offsetof 44251875Speter#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45251875Speter#endif 46251875Speter 47251875Spetertypedef struct { 48251875Speter uint16_t start; /* first register */ 49251875Speter uint16_t end; /* ending register or zero */ 50251875Speter} HAL_REGRANGE; 51251875Speter 52251875Spetertypedef struct { 53251875Speter uint32_t addr; /* regiser address/offset */ 54251875Speter uint32_t value; /* value to write */ 55251875Speter} HAL_REGWRITE; 56251875Speter 57251875Speter/* 58251875Speter * Transmit power scale factor. 59251875Speter * 60251875Speter * NB: This is not public because we want to discourage the use of 61251875Speter * scaling; folks should use the tx power limit interface. 62251875Speter */ 63251875Spetertypedef enum { 64251875Speter HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65251875Speter HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66251875Speter HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67251875Speter HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68251875Speter HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69251875Speter} HAL_TP_SCALE; 70251875Speter 71251875Spetertypedef enum { 72251875Speter HAL_CAP_RADAR = 0, /* Radar capability */ 73251875Speter HAL_CAP_AR = 1, /* AR capability */ 74251875Speter} HAL_PHYDIAG_CAPS; 75251875Speter 76251875Speter/* 77251875Speter * Each chip or class of chips registers to offer support. 78251875Speter */ 79251875Speterstruct ath_hal_chip { 80251875Speter const char *name; 81251875Speter const char *(*probe)(uint16_t vendorid, uint16_t devid); 82251875Speter struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83251875Speter HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84251875Speter}; 85251875Speter#ifndef AH_CHIP 86251875Speter#define AH_CHIP(_name, _probe, _attach) \ 87251875Speterstatic struct ath_hal_chip _name##_chip = { \ 88251875Speter .name = #_name, \ 89251875Speter .probe = _probe, \ 90251875Speter .attach = _attach \ 91251875Speter}; \ 92251875SpeterOS_DATA_SET(ah_chips, _name##_chip) 93251875Speter#endif 94251875Speter 95251875Speter/* 96251875Speter * Each RF backend registers to offer support; this is mostly 97251875Speter * used by multi-chip 5212 solutions. Single-chip solutions 98251875Speter * have a fixed idea about which RF to use. 99251875Speter */ 100251875Speterstruct ath_hal_rf { 101251875Speter const char *name; 102251875Speter HAL_BOOL (*probe)(struct ath_hal *ah); 103251875Speter HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104251875Speter}; 105251875Speter#ifndef AH_RF 106251875Speter#define AH_RF(_name, _probe, _attach) \ 107251875Speterstatic struct ath_hal_rf _name##_rf = { \ 108251875Speter .name = __STRING(_name), \ 109251875Speter .probe = _probe, \ 110251875Speter .attach = _attach \ 111251875Speter}; \ 112251875SpeterOS_DATA_SET(ah_rfs, _name##_rf) 113251875Speter#endif 114251875Speter 115251875Speterstruct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116251875Speter 117251875Speter/* 118251875Speter * Maximum number of internal channels. Entries are per unique 119251875Speter * frequency so this might be need to be increased to handle all 120251875Speter * usage cases; typically no more than 32 are really needed but 121251875Speter * dynamically allocating the data structures is a bit painful 122251875Speter * right now. 123251875Speter */ 124251875Speter#ifndef AH_MAXCHAN 125251875Speter#define AH_MAXCHAN 96 126251875Speter#endif 127251875Speter 128251875Speter/* 129251875Speter * Internal per-channel state. These are found 130251875Speter * using ic_devdata in the ieee80211_channel. 131251875Speter */ 132251875Spetertypedef struct { 133251875Speter uint16_t channel; /* h/w frequency, NB: may be mapped */ 134251875Speter uint8_t privFlags; 135251875Speter#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136251875Speter#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137251875Speter#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138251875Speter uint8_t calValid; /* bitmask of cal types */ 139251875Speter int8_t iCoff; 140251875Speter int8_t qCoff; 141251875Speter int16_t rawNoiseFloor; 142251875Speter int16_t noiseFloorAdjust; 143251875Speter uint16_t mainSpur; /* cached spur value for this channel */ 144251875Speter} HAL_CHANNEL_INTERNAL; 145251875Speter 146251875Speter/* channel requires noise floor check */ 147251875Speter#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148251875Speter 149251875Speter/* all full-width channels */ 150251875Speter#define IEEE80211_CHAN_ALLFULL \ 151251875Speter (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152251875Speter#define IEEE80211_CHAN_ALLTURBOFULL \ 153251875Speter (IEEE80211_CHAN_ALLTURBO - \ 154251875Speter (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155251875Speter 156251875Spetertypedef struct { 157251875Speter uint32_t halChanSpreadSupport : 1, 158251875Speter halSleepAfterBeaconBroken : 1, 159251875Speter halCompressSupport : 1, 160251875Speter halBurstSupport : 1, 161251875Speter halFastFramesSupport : 1, 162251875Speter halChapTuningSupport : 1, 163251875Speter halTurboGSupport : 1, 164251875Speter halTurboPrimeSupport : 1, 165251875Speter halMicAesCcmSupport : 1, 166251875Speter halMicCkipSupport : 1, 167251875Speter halMicTkipSupport : 1, 168251875Speter halTkipMicTxRxKeySupport : 1, 169251875Speter halCipherAesCcmSupport : 1, 170251875Speter halCipherCkipSupport : 1, 171251875Speter halCipherTkipSupport : 1, 172251875Speter halPSPollBroken : 1, 173251875Speter halVEOLSupport : 1, 174251875Speter halBssIdMaskSupport : 1, 175251875Speter halMcastKeySrchSupport : 1, 176251875Speter halTsfAddSupport : 1, 177251875Speter halChanHalfRate : 1, 178251875Speter halChanQuarterRate : 1, 179251875Speter halHTSupport : 1, 180251875Speter halRfSilentSupport : 1, 181251875Speter halHwPhyCounterSupport : 1, 182362181Sdim halWowSupport : 1, 183251875Speter halWowMatchPatternExact : 1, 184251875Speter halAutoSleepSupport : 1, 185251875Speter halFastCCSupport : 1, 186251875Speter halBtCoexSupport : 1; 187251875Speter uint32_t halRxStbcSupport : 1, 188251875Speter halTxStbcSupport : 1, 189251875Speter halGTTSupport : 1, 190251875Speter halCSTSupport : 1, 191251875Speter halRifsRxSupport : 1, 192251875Speter halRifsTxSupport : 1, 193251875Speter halExtChanDfsSupport : 1, 194362181Sdim halForcePpmSupport : 1, 195251875Speter halEnhancedPmSupport : 1, 196251875Speter halMbssidAggrSupport : 1, 197251875Speter halBssidMatchSupport : 1; 198251875Speter uint32_t halWirelessModes; 199251875Speter uint16_t halTotalQueues; 200251875Speter uint16_t halKeyCacheSize; 201251875Speter uint16_t halLow5GhzChan, halHigh5GhzChan; 202251875Speter uint16_t halLow2GhzChan, halHigh2GhzChan; 203251875Speter int halTstampPrecision; 204251875Speter int halRtsAggrLimit; 205251875Speter uint8_t halTxChainMask; 206251875Speter uint8_t halRxChainMask; 207251875Speter uint8_t halNumGpioPins; 208251875Speter uint8_t halNumAntCfg2GHz; 209251875Speter uint8_t halNumAntCfg5GHz; 210251875Speter uint32_t halIntrMask; 211251875Speter} HAL_CAPABILITIES; 212251875Speter 213251875Speterstruct regDomain; 214251875Speter 215251875Speter/* 216251875Speter * The ``private area'' follows immediately after the ``public area'' 217251875Speter * in the data structure returned by ath_hal_attach. Private data are 218251875Speter * used by device-independent code such as the regulatory domain support. 219251875Speter * In general, code within the HAL should never depend on data in the 220251875Speter * public area. Instead any public data needed internally should be 221251875Speter * shadowed here. 222251875Speter * 223251875Speter * When declaring a device-specific ath_hal data structure this structure 224251875Speter * is assumed to at the front; e.g. 225251875Speter * 226251875Speter * struct ath_hal_5212 { 227251875Speter * struct ath_hal_private ah_priv; 228251875Speter * ... 229251875Speter * }; 230251875Speter * 231251875Speter * It might be better to manage the method pointers in this structure 232251875Speter * using an indirect pointer to a read-only data structure but this would 233251875Speter * disallow class-style method overriding. 234251875Speter */ 235251875Speterstruct ath_hal_private { 236251875Speter struct ath_hal h; /* public area */ 237251875Speter 238251875Speter /* NB: all methods go first to simplify initialization */ 239251875Speter HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 240251875Speter uint16_t channelFlags, 241251875Speter uint16_t *lowChannel, uint16_t *highChannel); 242251875Speter u_int (*ah_getWirelessModes)(struct ath_hal*); 243251875Speter HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 244251875Speter uint16_t *data); 245251875Speter HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 246251875Speter uint16_t data); 247251875Speter HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 248251875Speter struct ieee80211_channel *); 249251875Speter int16_t (*ah_getNfAdjust)(struct ath_hal *, 250251875Speter const HAL_CHANNEL_INTERNAL*); 251251875Speter void (*ah_getNoiseFloor)(struct ath_hal *, 252251875Speter int16_t nfarray[]); 253251875Speter 254251875Speter void *ah_eeprom; /* opaque EEPROM state */ 255251875Speter uint16_t ah_eeversion; /* EEPROM version */ 256251875Speter void (*ah_eepromDetach)(struct ath_hal *); 257251875Speter HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 258251875Speter HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 259251875Speter uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 260251875Speter HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 261251875Speter const void *args, uint32_t argsize, 262251875Speter void **result, uint32_t *resultsize); 263251875Speter 264251875Speter /* 265251875Speter * Device revision information. 266251875Speter */ 267251875Speter uint16_t ah_devid; /* PCI device ID */ 268251875Speter uint16_t ah_subvendorid; /* PCI subvendor ID */ 269251875Speter uint32_t ah_macVersion; /* MAC version id */ 270251875Speter uint16_t ah_macRev; /* MAC revision */ 271266735Speter uint16_t ah_phyRev; /* PHY revision */ 272266735Speter uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 273266735Speter uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 274266735Speter uint8_t ah_ispcie; /* PCIE, special treatment */ 275266735Speter 276266735Speter HAL_OPMODE ah_opmode; /* operating mode from reset */ 277266735Speter const struct ieee80211_channel *ah_curchan;/* operating channel */ 278266735Speter HAL_CAPABILITIES ah_caps; /* device capabilities */ 279266735Speter uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 280266735Speter int16_t ah_powerLimit; /* tx power cap */ 281266735Speter uint16_t ah_maxPowerLevel; /* calculated max tx power */ 282266735Speter u_int ah_tpScale; /* tx power scale factor */ 283251875Speter uint32_t ah_11nCompat; /* 11n compat controls */ 284251875Speter 285251875Speter /* 286251875Speter * State for regulatory domain handling. 287251875Speter */ 288251875Speter HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 289251875Speter HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 290251875Speter u_int ah_nchan; /* valid items in ah_channels */ 291251875Speter const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 292251875Speter const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 293251875Speter 294251875Speter uint8_t ah_coverageClass; /* coverage class */ 295251875Speter /* 296251875Speter * RF Silent handling; setup according to the EEPROM. 297251875Speter */ 298251875Speter uint16_t ah_rfsilent; /* GPIO pin + polarity */ 299251875Speter HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 300251875Speter /* 301251875Speter * Diagnostic support for discriminating HIUERR reports. 302251875Speter */ 303251875Speter uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 304251875Speter int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 305251875Speter}; 306251875Speter 307251875Speter#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 308251875Speter 309251875Speter#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 310251875Speter AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 311251875Speter#define ath_hal_getWirelessModes(_ah) \ 312251875Speter AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 313251875Speter#define ath_hal_eepromRead(_ah, _off, _data) \ 314251875Speter AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 315251875Speter#define ath_hal_eepromWrite(_ah, _off, _data) \ 316251875Speter AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 317251875Speter#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 318251875Speter (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 319251875Speter#define ath_hal_gpioCfgInput(_ah, _gpio) \ 320251875Speter (_ah)->ah_gpioCfgInput(_ah, _gpio) 321362181Sdim#define ath_hal_gpioGet(_ah, _gpio) \ 322251875Speter (_ah)->ah_gpioGet(_ah, _gpio) 323251875Speter#define ath_hal_gpioSet(_ah, _gpio, _val) \ 324251875Speter (_ah)->ah_gpioSet(_ah, _gpio, _val) 325251875Speter#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 326251875Speter (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 327251875Speter#define ath_hal_getpowerlimits(_ah, _chan) \ 328251875Speter AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 329251875Speter#define ath_hal_getNfAdjust(_ah, _c) \ 330251875Speter AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 331251875Speter#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 332251875Speter AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 333362181Sdim#define ath_hal_configPCIE(_ah, _reset) \ 334251875Speter (_ah)->ah_configPCIE(_ah, _reset) 335251875Speter#define ath_hal_disablePCIE(_ah) \ 336251875Speter (_ah)->ah_disablePCIE(_ah) 337251875Speter 338251875Speter#define ath_hal_eepromDetach(_ah) do { \ 339251875Speter if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 340251875Speter AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 341251875Speter} while (0) 342251875Speter#define ath_hal_eepromGet(_ah, _param, _val) \ 343251875Speter AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 344251875Speter#define ath_hal_eepromSet(_ah, _param, _val) \ 345251875Speter AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 346251875Speter#define ath_hal_eepromGetFlag(_ah, _param) \ 347251875Speter (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 348251875Speter#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 349251875Speter AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 350251875Speter#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 351251875Speter AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 352251875Speter 353251875Speter#ifndef _NET_IF_IEEE80211_H_ 354251875Speter/* 355251875Speter * Stuff that would naturally come from _ieee80211.h 356251875Speter */ 357251875Speter#define IEEE80211_ADDR_LEN 6 358251875Speter 359251875Speter#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 360251875Speter#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 361251875Speter#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 362251875Speter 363251875Speter#define IEEE80211_CRC_LEN 4 364251875Speter 365251875Speter#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 366251875Speter (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 367251875Speter#endif /* _NET_IF_IEEE80211_H_ */ 368251875Speter 369251875Speter#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 370251875Speter 371251875Speter#define INIT_AIFS 2 372251875Speter#define INIT_CWMIN 15 373251875Speter#define INIT_CWMIN_11B 31 374251875Speter#define INIT_CWMAX 1023 375251875Speter#define INIT_SH_RETRY 10 376251875Speter#define INIT_LG_RETRY 10 377251875Speter#define INIT_SSH_RETRY 32 378251875Speter#define INIT_SLG_RETRY 32 379251875Speter 380251875Spetertypedef struct { 381251875Speter uint32_t tqi_ver; /* HAL TXQ verson */ 382251875Speter HAL_TX_QUEUE tqi_type; /* hw queue type*/ 383362181Sdim HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 384251875Speter HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 385251875Speter uint32_t tqi_priority; 386251875Speter uint32_t tqi_aifs; /* aifs */ 387251875Speter uint32_t tqi_cwmin; /* cwMin */ 388251875Speter uint32_t tqi_cwmax; /* cwMax */ 389251875Speter uint16_t tqi_shretry; /* frame short retry limit */ 390251875Speter uint16_t tqi_lgretry; /* frame long retry limit */ 391251875Speter uint32_t tqi_cbrPeriod; 392251875Speter uint32_t tqi_cbrOverflowLimit; 393251875Speter uint32_t tqi_burstTime; 394251875Speter uint32_t tqi_readyTime; 395251875Speter uint32_t tqi_physCompBuf; 396362181Sdim uint32_t tqi_intFlags; /* flags for internal use */ 397251875Speter} HAL_TX_QUEUE_INFO; 398251875Speter 399251875Speterextern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 400251875Speter HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 401251875Speterextern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 402251875Speter HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 403251875Speter 404251875Spetertypedef enum { 405362181Sdim HAL_ANI_PRESENT, /* is ANI support present */ 406251875Speter HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 407251875Speter HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 408251875Speter HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 409251875Speter HAL_ANI_FIRSTEP_LEVEL, /* set level */ 410251875Speter HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 411251875Speter HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 412251875Speter HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 413251875Speter} HAL_ANI_CMD; 414251875Speter 415251875Speter#define HAL_SPUR_VAL_MASK 0x3FFF 416362181Sdim#define HAL_SPUR_CHAN_WIDTH 87 417251875Speter#define HAL_BIN_WIDTH_BASE_100HZ 3125 418251875Speter#define HAL_BIN_WIDTH_TURBO_100HZ 6250 419251875Speter#define HAL_MAX_BINS_ALLOWED 28 420251875Speter 421251875Speter#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 422362181Sdim#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 423251875Speter 424251875Speter#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 425251875Speter 426251875Speter/* 427251875Speter * Deduce if the host cpu has big- or litt-endian byte order. 428251875Speter */ 429251875Speterstatic __inline__ int 430251875SpeterisBigEndian(void) 431362181Sdim{ 432251875Speter union { 433251875Speter int32_t i; 434251875Speter char c[4]; 435251875Speter } u; 436251875Speter u.i = 1; 437251875Speter return (u.c[0] == 0); 438251875Speter} 439251875Speter 440362181Sdim/* unalligned little endian access */ 441362181Sdim#define LE_READ_2(p) \ 442251875Speter ((uint16_t) \ 443251875Speter ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 444251875Speter#define LE_READ_4(p) \ 445251875Speter ((uint32_t) \ 446251875Speter ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 447251875Speter (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 448251875Speter 449251875Speter/* 450362181Sdim * Register manipulation macros that expect bit field defines 451251875Speter * to follow the convention that an _S suffix is appended for 452251875Speter * a shift count, while the field mask has no suffix. 453251875Speter */ 454251875Speter#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 455251875Speter#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 456251875Speter#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 457251875Speter OS_REG_WRITE(_a, _r, \ 458251875Speter (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 459251875Speter#define OS_REG_SET_BIT(_a, _r, _f) \ 460251875Speter OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 461251875Speter#define OS_REG_CLR_BIT(_a, _r, _f) \ 462251875Speter OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 463251875Speter 464251875Speter/* system-configurable parameters */ 465251875Speterextern int ath_hal_dma_beacon_response_time; /* in TU's */ 466251875Speterextern int ath_hal_sw_beacon_response_time; /* in TU's */ 467251875Speterextern int ath_hal_additional_swba_backoff; /* in TU's */ 468362181Sdim 469362181Sdim/* wait for the register contents to have the specified value */ 470362181Sdimextern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 471251875Speter uint32_t mask, uint32_t val); 472251875Speter 473251875Speter/* return the first n bits in val reversed */ 474251875Speterextern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 475251875Speter 476251875Speter/* printf interfaces */ 477251875Speterextern void ath_hal_printf(struct ath_hal *, const char*, ...) 478251875Speter __printflike(2,3); 479251875Speterextern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 480251875Speter __printflike(2, 0); 481251875Speterextern const char* ath_hal_ether_sprintf(const uint8_t *mac); 482251875Speter 483251875Speter/* allocate and free memory */ 484251875Speterextern void *ath_hal_malloc(size_t); 485251875Speterextern void ath_hal_free(void *); 486251875Speter 487251875Speter/* common debugging interfaces */ 488251875Speter#ifdef AH_DEBUG 489251875Speter#include "ah_debug.h" 490251875Speterextern int ath_hal_debug; 491251875Speterextern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 492251875Speter __printflike(3,4); 493251875Speter#else 494362181Sdim#define HALDEBUG(_ah, __m, _fmt, ...) 495362181Sdim#endif /* AH_DEBUG */ 496251875Speter 497251875Speter/* 498251875Speter * Register logging definitions shared with ardecode. 499251875Speter */ 500251875Speter#include "ah_decode.h" 501251875Speter 502251875Speter/* 503251875Speter * Common assertion interface. Note: it is a bad idea to generate 504251875Speter * an assertion failure for any recoverable event. Instead catch 505251875Speter * the violation and, if possible, fix it up or recover from it; either 506251875Speter * with an error return value or a diagnostic messages. System software 507251875Speter * does not panic unless the situation is hopeless. 508 */ 509#ifdef AH_ASSERT 510extern void ath_hal_assert_failed(const char* filename, 511 int lineno, const char* msg); 512 513#define HALASSERT(_x) do { \ 514 if (!(_x)) { \ 515 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 516 } \ 517} while (0) 518#else 519#define HALASSERT(_x) 520#endif /* AH_ASSERT */ 521 522/* 523 * Regulatory domain support. 524 */ 525 526/* 527 * Return the max allowed antenna gain and apply any regulatory 528 * domain specific changes. 529 */ 530u_int ath_hal_getantennareduction(struct ath_hal *ah, 531 const struct ieee80211_channel *chan, u_int twiceGain); 532 533/* 534 * Return the test group for the specific channel based on 535 * the current regulatory setup. 536 */ 537u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 538 539/* 540 * Map a public channel definition to the corresponding 541 * internal data structure. This implicitly specifies 542 * whether or not the specified channel is ok to use 543 * based on the current regulatory domain constraints. 544 */ 545#ifndef AH_DEBUG 546static OS_INLINE HAL_CHANNEL_INTERNAL * 547ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 548{ 549 HAL_CHANNEL_INTERNAL *cc; 550 551 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 552 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 553 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 554 return cc; 555} 556#else 557/* NB: non-inline version that checks state */ 558HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 559 const struct ieee80211_channel *); 560#endif /* AH_DEBUG */ 561 562/* 563 * Return the h/w frequency for a channel. This may be 564 * different from ic_freq if this is a GSM device that 565 * takes 2.4GHz frequencies and down-converts them. 566 */ 567static OS_INLINE uint16_t 568ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 569{ 570 return ath_hal_checkchannel(ah, c)->channel; 571} 572 573/* 574 * Convert between microseconds and core system clocks. 575 */ 576extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 577extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 578 579/* 580 * Generic get/set capability support. Each chip overrides 581 * this routine to support chip-specific capabilities. 582 */ 583extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 584 HAL_CAPABILITY_TYPE type, uint32_t capability, 585 uint32_t *result); 586extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 587 HAL_CAPABILITY_TYPE type, uint32_t capability, 588 uint32_t setting, HAL_STATUS *status); 589 590/* 591 * Diagnostic interface. This is an open-ended interface that 592 * is opaque to applications. Diagnostic programs use this to 593 * retrieve internal data structures, etc. There is no guarantee 594 * that calling conventions for calls other than HAL_DIAG_REVS 595 * are stable between HAL releases; a diagnostic application must 596 * use the HAL revision information to deal with ABI/API differences. 597 * 598 * NB: do not renumber these, certain codes are publicly used. 599 */ 600enum { 601 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 602 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 603 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 604 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 605 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 606 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 607 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 608 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 609 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 610 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 611 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 612 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 613 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 614 HAL_DIAG_REGS = 13, /* Registers */ 615 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 616 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 617 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 618 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 619 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 620 /* 19-26 removed, do not reuse */ 621 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 622 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 623 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 624 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 625 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 626 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 627 HAL_DIAG_SETREGS = 33, /* write registers */ 628}; 629 630enum { 631 HAL_BB_HANG_DFS = 0x0001, 632 HAL_BB_HANG_RIFS = 0x0002, 633 HAL_BB_HANG_RX_CLEAR = 0x0004, 634 HAL_BB_HANG_UNKNOWN = 0x0080, 635 636 HAL_MAC_HANG_SIG1 = 0x0100, 637 HAL_MAC_HANG_SIG2 = 0x0200, 638 HAL_MAC_HANG_UNKNOWN = 0x8000, 639 640 HAL_BB_HANGS = HAL_BB_HANG_DFS 641 | HAL_BB_HANG_RIFS 642 | HAL_BB_HANG_RX_CLEAR 643 | HAL_BB_HANG_UNKNOWN, 644 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 645 | HAL_MAC_HANG_SIG2 646 | HAL_MAC_HANG_UNKNOWN, 647}; 648 649/* 650 * Device revision information. 651 */ 652typedef struct { 653 uint16_t ah_devid; /* PCI device ID */ 654 uint16_t ah_subvendorid; /* PCI subvendor ID */ 655 uint32_t ah_macVersion; /* MAC version id */ 656 uint16_t ah_macRev; /* MAC revision */ 657 uint16_t ah_phyRev; /* PHY revision */ 658 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 659 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 660} HAL_REVS; 661 662/* 663 * Argument payload for HAL_DIAG_SETKEY. 664 */ 665typedef struct { 666 HAL_KEYVAL dk_keyval; 667 uint16_t dk_keyix; /* key index */ 668 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 669 int dk_xor; /* XOR key data */ 670} HAL_DIAG_KEYVAL; 671 672/* 673 * Argument payload for HAL_DIAG_EEWRITE. 674 */ 675typedef struct { 676 uint16_t ee_off; /* eeprom offset */ 677 uint16_t ee_data; /* write data */ 678} HAL_DIAG_EEVAL; 679 680 681typedef struct { 682 u_int offset; /* reg offset */ 683 uint32_t val; /* reg value */ 684} HAL_DIAG_REGVAL; 685 686/* 687 * 11n compatibility tweaks. 688 */ 689#define HAL_DIAG_11N_SERVICES 0x00000003 690#define HAL_DIAG_11N_SERVICES_S 0 691#define HAL_DIAG_11N_TXSTOMP 0x0000000c 692#define HAL_DIAG_11N_TXSTOMP_S 2 693 694typedef struct { 695 int maxNoiseImmunityLevel; /* [0..4] */ 696 int totalSizeDesired[5]; 697 int coarseHigh[5]; 698 int coarseLow[5]; 699 int firpwr[5]; 700 701 int maxSpurImmunityLevel; /* [0..7] */ 702 int cycPwrThr1[8]; 703 704 int maxFirstepLevel; /* [0..2] */ 705 int firstep[3]; 706 707 uint32_t ofdmTrigHigh; 708 uint32_t ofdmTrigLow; 709 int32_t cckTrigHigh; 710 int32_t cckTrigLow; 711 int32_t rssiThrLow; 712 int32_t rssiThrHigh; 713 714 int period; /* update listen period */ 715} HAL_ANI_PARAMS; 716 717extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 718 const void *args, uint32_t argsize, 719 void **result, uint32_t *resultsize); 720 721/* 722 * Setup a h/w rate table for use. 723 */ 724extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 725 726/* 727 * Common routine for implementing getChanNoise api. 728 */ 729int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 730 731/* 732 * Initialization support. 733 */ 734typedef struct { 735 const uint32_t *data; 736 int rows, cols; 737} HAL_INI_ARRAY; 738 739#define HAL_INI_INIT(_ia, _data, _cols) do { \ 740 (_ia)->data = (const uint32_t *)(_data); \ 741 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 742 (_ia)->cols = (_cols); \ 743} while (0) 744#define HAL_INI_VAL(_ia, _r, _c) \ 745 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 746 747/* 748 * OS_DELAY() does a PIO READ on the PCI bus which allows 749 * other cards' DMA reads to complete in the middle of our reset. 750 */ 751#define DMA_YIELD(x) do { \ 752 if ((++(x) % 64) == 0) \ 753 OS_DELAY(1); \ 754} while (0) 755 756#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 757 int r; \ 758 for (r = 0; r < N(regArray); r++) { \ 759 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 760 DMA_YIELD(regWr); \ 761 } \ 762} while (0) 763 764#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 765 int r; \ 766 for (r = 0; r < N(regArray); r++) { \ 767 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 768 DMA_YIELD(regWr); \ 769 } \ 770} while (0) 771 772extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 773 int col, int regWr); 774extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 775 int col); 776extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 777 const uint32_t data[], int regWr); 778 779#define CCK_SIFS_TIME 10 780#define CCK_PREAMBLE_BITS 144 781#define CCK_PLCP_BITS 48 782 783#define OFDM_SIFS_TIME 16 784#define OFDM_PREAMBLE_TIME 20 785#define OFDM_PLCP_BITS 22 786#define OFDM_SYMBOL_TIME 4 787 788#define OFDM_HALF_SIFS_TIME 32 789#define OFDM_HALF_PREAMBLE_TIME 40 790#define OFDM_HALF_PLCP_BITS 22 791#define OFDM_HALF_SYMBOL_TIME 8 792 793#define OFDM_QUARTER_SIFS_TIME 64 794#define OFDM_QUARTER_PREAMBLE_TIME 80 795#define OFDM_QUARTER_PLCP_BITS 22 796#define OFDM_QUARTER_SYMBOL_TIME 16 797 798#define TURBO_SIFS_TIME 8 799#define TURBO_PREAMBLE_TIME 14 800#define TURBO_PLCP_BITS 22 801#define TURBO_SYMBOL_TIME 4 802 803#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 804#endif /* _ATH_AH_INTERAL_H_ */ 805