ah_internal.h revision 192396
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 192396 2009-05-19 17:30:13Z sam $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84}; 85#ifndef AH_CHIP 86#define AH_CHIP(_name, _probe, _attach) \ 87static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91}; \ 92OS_DATA_SET(ah_chips, _name##_chip) 93#endif 94 95/* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104}; 105#ifndef AH_RF 106#define AH_RF(_name, _probe, _attach) \ 107static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111}; \ 112OS_DATA_SET(ah_rfs, _name##_rf) 113#endif 114 115struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117/* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124#ifndef AH_MAXCHAN 125#define AH_MAXCHAN 96 126#endif 127 128/* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144} HAL_CHANNEL_INTERNAL; 145 146/* channel requires noise floor check */ 147#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149/* all full-width channels */ 150#define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152#define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1; 197 uint32_t halWirelessModes; 198 uint16_t halTotalQueues; 199 uint16_t halKeyCacheSize; 200 uint16_t halLow5GhzChan, halHigh5GhzChan; 201 uint16_t halLow2GhzChan, halHigh2GhzChan; 202 int halTstampPrecision; 203 int halRtsAggrLimit; 204 uint8_t halTxChainMask; 205 uint8_t halRxChainMask; 206 uint8_t halNumGpioPins; 207 uint8_t halNumAntCfg2GHz; 208 uint8_t halNumAntCfg5GHz; 209 uint32_t halIntrMask; 210} HAL_CAPABILITIES; 211 212struct regDomain; 213 214/* 215 * The ``private area'' follows immediately after the ``public area'' 216 * in the data structure returned by ath_hal_attach. Private data are 217 * used by device-independent code such as the regulatory domain support. 218 * In general, code within the HAL should never depend on data in the 219 * public area. Instead any public data needed internally should be 220 * shadowed here. 221 * 222 * When declaring a device-specific ath_hal data structure this structure 223 * is assumed to at the front; e.g. 224 * 225 * struct ath_hal_5212 { 226 * struct ath_hal_private ah_priv; 227 * ... 228 * }; 229 * 230 * It might be better to manage the method pointers in this structure 231 * using an indirect pointer to a read-only data structure but this would 232 * disallow class-style method overriding. 233 */ 234struct ath_hal_private { 235 struct ath_hal h; /* public area */ 236 237 /* NB: all methods go first to simplify initialization */ 238 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 239 uint16_t channelFlags, 240 uint16_t *lowChannel, uint16_t *highChannel); 241 u_int (*ah_getWirelessModes)(struct ath_hal*); 242 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 243 uint16_t *data); 244 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 245 uint16_t data); 246 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 247 struct ieee80211_channel *); 248 int16_t (*ah_getNfAdjust)(struct ath_hal *, 249 const HAL_CHANNEL_INTERNAL*); 250 void (*ah_getNoiseFloor)(struct ath_hal *, 251 int16_t nfarray[]); 252 253 void *ah_eeprom; /* opaque EEPROM state */ 254 uint16_t ah_eeversion; /* EEPROM version */ 255 void (*ah_eepromDetach)(struct ath_hal *); 256 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 257 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 258 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 259 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 260 const void *args, uint32_t argsize, 261 void **result, uint32_t *resultsize); 262 263 /* 264 * Device revision information. 265 */ 266 uint16_t ah_devid; /* PCI device ID */ 267 uint16_t ah_subvendorid; /* PCI subvendor ID */ 268 uint32_t ah_macVersion; /* MAC version id */ 269 uint16_t ah_macRev; /* MAC revision */ 270 uint16_t ah_phyRev; /* PHY revision */ 271 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 272 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 273 uint8_t ah_ispcie; /* PCIE, special treatment */ 274 275 HAL_OPMODE ah_opmode; /* operating mode from reset */ 276 const struct ieee80211_channel *ah_curchan;/* operating channel */ 277 HAL_CAPABILITIES ah_caps; /* device capabilities */ 278 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 279 int16_t ah_powerLimit; /* tx power cap */ 280 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 281 u_int ah_tpScale; /* tx power scale factor */ 282 uint32_t ah_11nCompat; /* 11n compat controls */ 283 284 /* 285 * State for regulatory domain handling. 286 */ 287 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 288 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 289 u_int ah_nchan; /* valid items in ah_channels */ 290 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 291 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 292 293 uint8_t ah_coverageClass; /* coverage class */ 294 /* 295 * RF Silent handling; setup according to the EEPROM. 296 */ 297 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 298 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 299 /* 300 * Diagnostic support for discriminating HIUERR reports. 301 */ 302 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 303 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 304}; 305 306#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 307 308#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 309 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 310#define ath_hal_getWirelessModes(_ah) \ 311 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 312#define ath_hal_eepromRead(_ah, _off, _data) \ 313 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 314#define ath_hal_eepromWrite(_ah, _off, _data) \ 315 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 316#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 317 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 318#define ath_hal_gpioCfgInput(_ah, _gpio) \ 319 (_ah)->ah_gpioCfgInput(_ah, _gpio) 320#define ath_hal_gpioGet(_ah, _gpio) \ 321 (_ah)->ah_gpioGet(_ah, _gpio) 322#define ath_hal_gpioSet(_ah, _gpio, _val) \ 323 (_ah)->ah_gpioSet(_ah, _gpio, _val) 324#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 325 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 326#define ath_hal_getpowerlimits(_ah, _chan) \ 327 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 328#define ath_hal_getNfAdjust(_ah, _c) \ 329 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 330#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 331 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 332#define ath_hal_configPCIE(_ah, _reset) \ 333 (_ah)->ah_configPCIE(_ah, _reset) 334#define ath_hal_disablePCIE(_ah) \ 335 (_ah)->ah_disablePCIE(_ah) 336 337#define ath_hal_eepromDetach(_ah) do { \ 338 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \ 339 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 340} while (0) 341#define ath_hal_eepromGet(_ah, _param, _val) \ 342 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 343#define ath_hal_eepromSet(_ah, _param, _val) \ 344 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 345#define ath_hal_eepromGetFlag(_ah, _param) \ 346 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 347#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 348 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 349#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 350 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 351 352#ifndef _NET_IF_IEEE80211_H_ 353/* 354 * Stuff that would naturally come from _ieee80211.h 355 */ 356#define IEEE80211_ADDR_LEN 6 357 358#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 359#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 360#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 361 362#define IEEE80211_CRC_LEN 4 363 364#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 365 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 366#endif /* _NET_IF_IEEE80211_H_ */ 367 368#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 369 370#define INIT_AIFS 2 371#define INIT_CWMIN 15 372#define INIT_CWMIN_11B 31 373#define INIT_CWMAX 1023 374#define INIT_SH_RETRY 10 375#define INIT_LG_RETRY 10 376#define INIT_SSH_RETRY 32 377#define INIT_SLG_RETRY 32 378 379typedef struct { 380 uint32_t tqi_ver; /* HAL TXQ verson */ 381 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 382 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 383 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 384 uint32_t tqi_priority; 385 uint32_t tqi_aifs; /* aifs */ 386 uint32_t tqi_cwmin; /* cwMin */ 387 uint32_t tqi_cwmax; /* cwMax */ 388 uint16_t tqi_shretry; /* frame short retry limit */ 389 uint16_t tqi_lgretry; /* frame long retry limit */ 390 uint32_t tqi_cbrPeriod; 391 uint32_t tqi_cbrOverflowLimit; 392 uint32_t tqi_burstTime; 393 uint32_t tqi_readyTime; 394 uint32_t tqi_physCompBuf; 395 uint32_t tqi_intFlags; /* flags for internal use */ 396} HAL_TX_QUEUE_INFO; 397 398extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 399 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 400extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 401 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 402 403typedef enum { 404 HAL_ANI_PRESENT, /* is ANI support present */ 405 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 406 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 407 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 408 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 409 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 410 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 411 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 412} HAL_ANI_CMD; 413 414#define HAL_SPUR_VAL_MASK 0x3FFF 415#define HAL_SPUR_CHAN_WIDTH 87 416#define HAL_BIN_WIDTH_BASE_100HZ 3125 417#define HAL_BIN_WIDTH_TURBO_100HZ 6250 418#define HAL_MAX_BINS_ALLOWED 28 419 420#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 421#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 422 423#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 424 425/* 426 * Deduce if the host cpu has big- or litt-endian byte order. 427 */ 428static __inline__ int 429isBigEndian(void) 430{ 431 union { 432 int32_t i; 433 char c[4]; 434 } u; 435 u.i = 1; 436 return (u.c[0] == 0); 437} 438 439/* unalligned little endian access */ 440#define LE_READ_2(p) \ 441 ((uint16_t) \ 442 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 443#define LE_READ_4(p) \ 444 ((uint32_t) \ 445 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 446 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 447 448/* 449 * Register manipulation macros that expect bit field defines 450 * to follow the convention that an _S suffix is appended for 451 * a shift count, while the field mask has no suffix. 452 */ 453#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 454#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 455#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 456 OS_REG_WRITE(_a, _r, \ 457 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 458#define OS_REG_SET_BIT(_a, _r, _f) \ 459 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 460#define OS_REG_CLR_BIT(_a, _r, _f) \ 461 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 462 463/* system-configurable parameters */ 464extern int ath_hal_dma_beacon_response_time; /* in TU's */ 465extern int ath_hal_sw_beacon_response_time; /* in TU's */ 466extern int ath_hal_additional_swba_backoff; /* in TU's */ 467 468/* wait for the register contents to have the specified value */ 469extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 470 uint32_t mask, uint32_t val); 471 472/* return the first n bits in val reversed */ 473extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 474 475/* printf interfaces */ 476extern void ath_hal_printf(struct ath_hal *, const char*, ...) 477 __printflike(2,3); 478extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 479 __printflike(2, 0); 480extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 481 482/* allocate and free memory */ 483extern void *ath_hal_malloc(size_t); 484extern void ath_hal_free(void *); 485 486/* common debugging interfaces */ 487#ifdef AH_DEBUG 488#include "ah_debug.h" 489extern int ath_hal_debug; 490extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 491 __printflike(3,4); 492#else 493#define HALDEBUG(_ah, __m, _fmt, ...) 494#endif /* AH_DEBUG */ 495 496/* 497 * Register logging definitions shared with ardecode. 498 */ 499#include "ah_decode.h" 500 501/* 502 * Common assertion interface. Note: it is a bad idea to generate 503 * an assertion failure for any recoverable event. Instead catch 504 * the violation and, if possible, fix it up or recover from it; either 505 * with an error return value or a diagnostic messages. System software 506 * does not panic unless the situation is hopeless. 507 */ 508#ifdef AH_ASSERT 509extern void ath_hal_assert_failed(const char* filename, 510 int lineno, const char* msg); 511 512#define HALASSERT(_x) do { \ 513 if (!(_x)) { \ 514 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 515 } \ 516} while (0) 517#else 518#define HALASSERT(_x) 519#endif /* AH_ASSERT */ 520 521/* 522 * Regulatory domain support. 523 */ 524 525/* 526 * Return the max allowed antenna gain and apply any regulatory 527 * domain specific changes. 528 */ 529u_int ath_hal_getantennareduction(struct ath_hal *ah, 530 const struct ieee80211_channel *chan, u_int twiceGain); 531 532/* 533 * Return the test group for the specific channel based on 534 * the current regulatory setup. 535 */ 536u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 537 538/* 539 * Map a public channel definition to the corresponding 540 * internal data structure. This implicitly specifies 541 * whether or not the specified channel is ok to use 542 * based on the current regulatory domain constraints. 543 */ 544#ifndef AH_DEBUG 545static OS_INLINE HAL_CHANNEL_INTERNAL * 546ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 547{ 548 HAL_CHANNEL_INTERNAL *cc; 549 550 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 551 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 552 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 553 return cc; 554} 555#else 556/* NB: non-inline version that checks state */ 557HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 558 const struct ieee80211_channel *); 559#endif /* AH_DEBUG */ 560 561/* 562 * Return the h/w frequency for a channel. This may be 563 * different from ic_freq if this is a GSM device that 564 * takes 2.4GHz frequencies and down-converts them. 565 */ 566static OS_INLINE uint16_t 567ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 568{ 569 return ath_hal_checkchannel(ah, c)->channel; 570} 571 572/* 573 * Convert between microseconds and core system clocks. 574 */ 575extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 576extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 577 578/* 579 * Generic get/set capability support. Each chip overrides 580 * this routine to support chip-specific capabilities. 581 */ 582extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 583 HAL_CAPABILITY_TYPE type, uint32_t capability, 584 uint32_t *result); 585extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 586 HAL_CAPABILITY_TYPE type, uint32_t capability, 587 uint32_t setting, HAL_STATUS *status); 588 589/* 590 * Diagnostic interface. This is an open-ended interface that 591 * is opaque to applications. Diagnostic programs use this to 592 * retrieve internal data structures, etc. There is no guarantee 593 * that calling conventions for calls other than HAL_DIAG_REVS 594 * are stable between HAL releases; a diagnostic application must 595 * use the HAL revision information to deal with ABI/API differences. 596 * 597 * NB: do not renumber these, certain codes are publicly used. 598 */ 599enum { 600 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 601 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 602 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 603 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 604 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 605 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 606 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 607 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 608 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 609 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 610 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 611 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 612 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 613 HAL_DIAG_REGS = 13, /* Registers */ 614 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 615 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 616 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 617 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 618 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 619 /* 19-26 removed, do not reuse */ 620 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 621 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 622 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 623 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 624 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 625 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 626 HAL_DIAG_SETREGS = 33, /* write registers */ 627}; 628 629enum { 630 HAL_BB_HANG_DFS = 0x0001, 631 HAL_BB_HANG_RIFS = 0x0002, 632 HAL_BB_HANG_RX_CLEAR = 0x0004, 633 HAL_BB_HANG_UNKNOWN = 0x0080, 634 635 HAL_MAC_HANG_SIG1 = 0x0100, 636 HAL_MAC_HANG_SIG2 = 0x0200, 637 HAL_MAC_HANG_UNKNOWN = 0x8000, 638 639 HAL_BB_HANGS = HAL_BB_HANG_DFS 640 | HAL_BB_HANG_RIFS 641 | HAL_BB_HANG_RX_CLEAR 642 | HAL_BB_HANG_UNKNOWN, 643 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 644 | HAL_MAC_HANG_SIG2 645 | HAL_MAC_HANG_UNKNOWN, 646}; 647 648/* 649 * Device revision information. 650 */ 651typedef struct { 652 uint16_t ah_devid; /* PCI device ID */ 653 uint16_t ah_subvendorid; /* PCI subvendor ID */ 654 uint32_t ah_macVersion; /* MAC version id */ 655 uint16_t ah_macRev; /* MAC revision */ 656 uint16_t ah_phyRev; /* PHY revision */ 657 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 658 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 659} HAL_REVS; 660 661/* 662 * Argument payload for HAL_DIAG_SETKEY. 663 */ 664typedef struct { 665 HAL_KEYVAL dk_keyval; 666 uint16_t dk_keyix; /* key index */ 667 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 668 int dk_xor; /* XOR key data */ 669} HAL_DIAG_KEYVAL; 670 671/* 672 * Argument payload for HAL_DIAG_EEWRITE. 673 */ 674typedef struct { 675 uint16_t ee_off; /* eeprom offset */ 676 uint16_t ee_data; /* write data */ 677} HAL_DIAG_EEVAL; 678 679 680typedef struct { 681 u_int offset; /* reg offset */ 682 uint32_t val; /* reg value */ 683} HAL_DIAG_REGVAL; 684 685/* 686 * 11n compatibility tweaks. 687 */ 688#define HAL_DIAG_11N_SERVICES 0x00000003 689#define HAL_DIAG_11N_SERVICES_S 0 690#define HAL_DIAG_11N_TXSTOMP 0x0000000c 691#define HAL_DIAG_11N_TXSTOMP_S 2 692 693typedef struct { 694 int maxNoiseImmunityLevel; /* [0..4] */ 695 int totalSizeDesired[5]; 696 int coarseHigh[5]; 697 int coarseLow[5]; 698 int firpwr[5]; 699 700 int maxSpurImmunityLevel; /* [0..7] */ 701 int cycPwrThr1[8]; 702 703 int maxFirstepLevel; /* [0..2] */ 704 int firstep[3]; 705 706 uint32_t ofdmTrigHigh; 707 uint32_t ofdmTrigLow; 708 int32_t cckTrigHigh; 709 int32_t cckTrigLow; 710 int32_t rssiThrLow; 711 int32_t rssiThrHigh; 712 713 int period; /* update listen period */ 714} HAL_ANI_PARAMS; 715 716extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 717 const void *args, uint32_t argsize, 718 void **result, uint32_t *resultsize); 719 720/* 721 * Setup a h/w rate table for use. 722 */ 723extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 724 725/* 726 * Common routine for implementing getChanNoise api. 727 */ 728int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 729 730/* 731 * Initialization support. 732 */ 733typedef struct { 734 const uint32_t *data; 735 int rows, cols; 736} HAL_INI_ARRAY; 737 738#define HAL_INI_INIT(_ia, _data, _cols) do { \ 739 (_ia)->data = (const uint32_t *)(_data); \ 740 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 741 (_ia)->cols = (_cols); \ 742} while (0) 743#define HAL_INI_VAL(_ia, _r, _c) \ 744 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 745 746/* 747 * OS_DELAY() does a PIO READ on the PCI bus which allows 748 * other cards' DMA reads to complete in the middle of our reset. 749 */ 750#define DMA_YIELD(x) do { \ 751 if ((++(x) % 64) == 0) \ 752 OS_DELAY(1); \ 753} while (0) 754 755#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 756 int r; \ 757 for (r = 0; r < N(regArray); r++) { \ 758 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 759 DMA_YIELD(regWr); \ 760 } \ 761} while (0) 762 763#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 764 int r; \ 765 for (r = 0; r < N(regArray); r++) { \ 766 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 767 DMA_YIELD(regWr); \ 768 } \ 769} while (0) 770 771extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 772 int col, int regWr); 773extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 774 int col); 775extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 776 const uint32_t data[], int regWr); 777 778#define CCK_SIFS_TIME 10 779#define CCK_PREAMBLE_BITS 144 780#define CCK_PLCP_BITS 48 781 782#define OFDM_SIFS_TIME 16 783#define OFDM_PREAMBLE_TIME 20 784#define OFDM_PLCP_BITS 22 785#define OFDM_SYMBOL_TIME 4 786 787#define OFDM_HALF_SIFS_TIME 32 788#define OFDM_HALF_PREAMBLE_TIME 40 789#define OFDM_HALF_PLCP_BITS 22 790#define OFDM_HALF_SYMBOL_TIME 8 791 792#define OFDM_QUARTER_SIFS_TIME 64 793#define OFDM_QUARTER_PREAMBLE_TIME 80 794#define OFDM_QUARTER_PLCP_BITS 22 795#define OFDM_QUARTER_SYMBOL_TIME 16 796 797#define TURBO_SIFS_TIME 8 798#define TURBO_PREAMBLE_TIME 14 799#define TURBO_PLCP_BITS 22 800#define TURBO_SYMBOL_TIME 4 801 802#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 803#endif /* _ATH_AH_INTERAL_H_ */ 804