ah_internal.h revision 188979
11553Srgrimes/* 21553Srgrimes * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 31553Srgrimes * Copyright (c) 2002-2008 Atheros Communications, Inc. 41553Srgrimes * 51553Srgrimes * Permission to use, copy, modify, and/or distribute this software for any 61553Srgrimes * purpose with or without fee is hereby granted, provided that the above 71553Srgrimes * copyright notice and this permission notice appear in all copies. 81553Srgrimes * 91553Srgrimes * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 101553Srgrimes * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 111553Srgrimes * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 121553Srgrimes * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 131553Srgrimes * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 141553Srgrimes * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 151553Srgrimes * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 161553Srgrimes * 171553Srgrimes * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 188979 2009-02-24 01:07:06Z sam $ 181553Srgrimes */ 191553Srgrimes#ifndef _ATH_AH_INTERAL_H_ 201553Srgrimes#define _ATH_AH_INTERAL_H_ 211553Srgrimes/* 221553Srgrimes * Atheros Device Hardware Access Layer (HAL). 231553Srgrimes * 241553Srgrimes * Internal definitions. 251553Srgrimes */ 261553Srgrimes#define AH_NULL 0 271553Srgrimes#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 281553Srgrimes#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 291553Srgrimes 301553Srgrimes#include <net80211/_ieee80211.h> 3130642Scharnier 321553Srgrimes#ifndef NBBY 331553Srgrimes#define NBBY 8 /* number of bits/byte */ 341553Srgrimes#endif 351553Srgrimes 36117278Scharnier#ifndef roundup 371553Srgrimes#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 381553Srgrimes#endif 39117278Scharnier#ifndef howmany 4030642Scharnier#define howmany(x, y) (((x)+((y)-1))/(y)) 411553Srgrimes#endif 42117278Scharnier 43117278Scharnier#ifndef offsetof 44117278Scharnier#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 451553Srgrimes#endif 461553Srgrimes 471553Srgrimestypedef struct { 481553Srgrimes uint16_t start; /* first register */ 491553Srgrimes uint16_t end; /* ending register or zero */ 501553Srgrimes} HAL_REGRANGE; 511553Srgrimes 521553Srgrimestypedef struct { 531553Srgrimes uint32_t addr; /* regiser address/offset */ 541553Srgrimes uint32_t value; /* value to write */ 551553Srgrimes} HAL_REGWRITE; 561553Srgrimes 571553Srgrimes/* 581553Srgrimes * Transmit power scale factor. 591553Srgrimes * 601553Srgrimes * NB: This is not public because we want to discourage the use of 611553Srgrimes * scaling; folks should use the tx power limit interface. 621553Srgrimes */ 631553Srgrimestypedef enum { 641553Srgrimes HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 651553Srgrimes HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 661553Srgrimes HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 671553Srgrimes HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 681553Srgrimes HAL_TP_SCALE_MIN = 4, /* min, but still on */ 691553Srgrimes} HAL_TP_SCALE; 701553Srgrimes 71299707Spfgtypedef enum { 721553Srgrimes HAL_CAP_RADAR = 0, /* Radar capability */ 731553Srgrimes HAL_CAP_AR = 1, /* AR capability */ 741553Srgrimes} HAL_PHYDIAG_CAPS; 751553Srgrimes 761553Srgrimes/* 771553Srgrimes * Each chip or class of chips registers to offer support. 781553Srgrimes */ 791553Srgrimesstruct ath_hal_chip { 801553Srgrimes const char *name; 81299707Spfg const char *(*probe)(uint16_t vendorid, uint16_t devid); 821553Srgrimes struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 831553Srgrimes HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 841553Srgrimes}; 851553Srgrimes#ifndef AH_CHIP 8630872Scharnier#define AH_CHIP(_name, _probe, _attach) \ 871553Srgrimesstatic struct ath_hal_chip _name##_chip = { \ 881553Srgrimes .name = #_name, \ 891553Srgrimes .probe = _probe, \ 901553Srgrimes .attach = _attach \ 911553Srgrimes}; \ 92117278ScharnierOS_DATA_SET(ah_chips, _name##_chip) 93117278Scharnier#endif 94117278Scharnier 95117278Scharnier/* 961553Srgrimes * Each RF backend registers to offer support; this is mostly 971553Srgrimes * used by multi-chip 5212 solutions. Single-chip solutions 981553Srgrimes * have a fixed idea about which RF to use. 991553Srgrimes */ 1001553Srgrimesstruct ath_hal_rf { 1011553Srgrimes const char *name; 1021553Srgrimes HAL_BOOL (*probe)(struct ath_hal *ah); 1031553Srgrimes HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 1041553Srgrimes}; 1051553Srgrimes#ifndef AH_RF 1061553Srgrimes#define AH_RF(_name, _probe, _attach) \ 1071553Srgrimesstatic struct ath_hal_rf _name##_rf = { \ 1081553Srgrimes .name = __STRING(_name), \ 1091553Srgrimes .probe = _probe, \ 1101553Srgrimes .attach = _attach \ 1111553Srgrimes}; \ 1121553SrgrimesOS_DATA_SET(ah_rfs, _name##_rf) 113246209Scharnier#endif 1141553Srgrimes 1151553Srgrimesstruct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 1161553Srgrimes 1171553Srgrimes/* 1181553Srgrimes * Maximum number of internal channels. Entries are per unique 1191553Srgrimes * frequency so this might be need to be increased to handle all 1201553Srgrimes * usage cases; typically no more than 32 are really needed but 1211553Srgrimes * dynamically allocating the data structures is a bit painful 1221553Srgrimes * right now. 1231553Srgrimes */ 1241553Srgrimes#ifndef AH_MAXCHAN 1251553Srgrimes#define AH_MAXCHAN 96 1261553Srgrimes#endif 1271553Srgrimes 1281553Srgrimes/* 1291553Srgrimes * Internal per-channel state. These are found 130179485Simp * using ic_devdata in the ieee80211_channel. 1311553Srgrimes */ 1321553Srgrimestypedef struct { 1331553Srgrimes uint16_t channel; /* h/w frequency, NB: may be mapped */ 1341553Srgrimes uint8_t privFlags; 1351553Srgrimes#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 1361553Srgrimes#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 1371553Srgrimes#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 1381553Srgrimes uint8_t calValid; /* bitmask of cal types */ 1391553Srgrimes int8_t iCoff; 1401553Srgrimes int8_t qCoff; 1411553Srgrimes int16_t rawNoiseFloor; 14224428Simp int16_t noiseFloorAdjust; 1431553Srgrimes uint16_t mainSpur; /* cached spur value for this channel */ 1441553Srgrimes} HAL_CHANNEL_INTERNAL; 1451553Srgrimes 1461553Srgrimes/* channel requires noise floor check */ 1471553Srgrimes#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 1481553Srgrimes 1491553Srgrimes/* all full-width channels */ 1501553Srgrimes#define IEEE80211_CHAN_ALLFULL \ 1511553Srgrimes (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 1521553Srgrimes#define IEEE80211_CHAN_ALLTURBOFULL \ 1531553Srgrimes (IEEE80211_CHAN_ALLTURBO - \ 15430642Scharnier (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 1551553Srgrimes 1561553Srgrimestypedef struct { 1571553Srgrimes uint32_t halChanSpreadSupport : 1, 1581553Srgrimes halSleepAfterBeaconBroken : 1, 1591553Srgrimes halCompressSupport : 1, 1601553Srgrimes halBurstSupport : 1, 1611553Srgrimes halFastFramesSupport : 1, 1621553Srgrimes halChapTuningSupport : 1, 16330642Scharnier halTurboGSupport : 1, 1641553Srgrimes halTurboPrimeSupport : 1, 1651553Srgrimes halMicAesCcmSupport : 1, 1661553Srgrimes halMicCkipSupport : 1, 1671553Srgrimes halMicTkipSupport : 1, 1681553Srgrimes halTkipMicTxRxKeySupport : 1, 1691553Srgrimes halCipherAesCcmSupport : 1, 1701553Srgrimes halCipherCkipSupport : 1, 1711553Srgrimes halCipherTkipSupport : 1, 1721553Srgrimes halPSPollBroken : 1, 1731553Srgrimes halVEOLSupport : 1, 1741553Srgrimes halBssIdMaskSupport : 1, 1751553Srgrimes halMcastKeySrchSupport : 1, 1761553Srgrimes halTsfAddSupport : 1, 1771553Srgrimes halChanHalfRate : 1, 1781553Srgrimes halChanQuarterRate : 1, 1791553Srgrimes halHTSupport : 1, 180299707Spfg halRfSilentSupport : 1, 18130642Scharnier halHwPhyCounterSupport : 1, 1821553Srgrimes halWowSupport : 1, 1831553Srgrimes halWowMatchPatternExact : 1, 1841553Srgrimes halAutoSleepSupport : 1, 1851553Srgrimes halFastCCSupport : 1, 18630642Scharnier halBtCoexSupport : 1; 1871553Srgrimes uint32_t halRxStbcSupport : 1, 1881553Srgrimes halTxStbcSupport : 1, 1891553Srgrimes halGTTSupport : 1, 19030642Scharnier halCSTSupport : 1, 19130642Scharnier halRifsRxSupport : 1, 1921553Srgrimes halRifsTxSupport : 1, 1931553Srgrimes halExtChanDfsSupport : 1, 1941553Srgrimes halForcePpmSupport : 1, 1951553Srgrimes halEnhancedPmSupport : 1, 196299707Spfg halMbssidAggrSupport : 1; 1971553Srgrimes uint32_t halWirelessModes; 1981553Srgrimes uint16_t halTotalQueues; 199299713Spfg uint16_t halKeyCacheSize; 20030642Scharnier uint16_t halLow5GhzChan, halHigh5GhzChan; 2011553Srgrimes uint16_t halLow2GhzChan, halHigh2GhzChan; 2021553Srgrimes int halTstampPrecision; 2031553Srgrimes int halRtsAggrLimit; 2041553Srgrimes uint8_t halTxChainMask; 2051553Srgrimes uint8_t halRxChainMask; 2061553Srgrimes uint8_t halNumGpioPins; 2071553Srgrimes uint8_t halNumAntCfg2GHz; 208299707Spfg uint8_t halNumAntCfg5GHz; 2091553Srgrimes} HAL_CAPABILITIES; 2101553Srgrimes 2111553Srgrimesstruct regDomain; 212299707Spfg 213117278Scharnier/* 2141553Srgrimes * The ``private area'' follows immediately after the ``public area'' 2158532Sdg * in the data structure returned by ath_hal_attach. Private data are 2161553Srgrimes * used by device-independent code such as the regulatory domain support. 2171553Srgrimes * In general, code within the HAL should never depend on data in the 2181553Srgrimes * public area. Instead any public data needed internally should be 21930642Scharnier * shadowed here. 22030642Scharnier * 2211553Srgrimes * When declaring a device-specific ath_hal data structure this structure 22230642Scharnier * is assumed to at the front; e.g. 22330642Scharnier * 2241553Srgrimes * struct ath_hal_5212 { 2251553Srgrimes * struct ath_hal_private ah_priv; 22630642Scharnier * ... 2271553Srgrimes * }; 22830642Scharnier * 2291553Srgrimes * It might be better to manage the method pointers in this structure 2301553Srgrimes * using an indirect pointer to a read-only data structure but this would 2311553Srgrimes * disallow class-style method overriding. 232299708Spfg */ 233299708Spfgstruct ath_hal_private { 234239991Sed struct ath_hal h; /* public area */ 2351553Srgrimes 2361553Srgrimes /* NB: all methods go first to simplify initialization */ 2371553Srgrimes HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 2381553Srgrimes uint16_t channelFlags, 2391553Srgrimes uint16_t *lowChannel, uint16_t *highChannel); 2401553Srgrimes u_int (*ah_getWirelessModes)(struct ath_hal*); 2411553Srgrimes HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 242299707Spfg uint16_t *data); 2431553Srgrimes HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 2441553Srgrimes uint16_t data); 2451553Srgrimes HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 2461553Srgrimes struct ieee80211_channel *); 247299707Spfg int16_t (*ah_getNfAdjust)(struct ath_hal *, 2481553Srgrimes const HAL_CHANNEL_INTERNAL*); 2491553Srgrimes void (*ah_getNoiseFloor)(struct ath_hal *, 25030642Scharnier int16_t nfarray[]); 2511553Srgrimes 25230642Scharnier void *ah_eeprom; /* opaque EEPROM state */ 2531553Srgrimes uint16_t ah_eeversion; /* EEPROM version */ 25430642Scharnier void (*ah_eepromDetach)(struct ath_hal *); 2551553Srgrimes HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 2561553Srgrimes HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 2571553Srgrimes uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 2581553Srgrimes HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 2591553Srgrimes const void *args, uint32_t argsize, 2601553Srgrimes void **result, uint32_t *resultsize); 2611553Srgrimes 2621553Srgrimes /* 2631553Srgrimes * Device revision information. 2641553Srgrimes */ 2651553Srgrimes uint16_t ah_devid; /* PCI device ID */ 2661553Srgrimes uint16_t ah_subvendorid; /* PCI subvendor ID */ 26730642Scharnier uint32_t ah_macVersion; /* MAC version id */ 26830642Scharnier uint16_t ah_macRev; /* MAC revision */ 2691553Srgrimes uint16_t ah_phyRev; /* PHY revision */ 2701553Srgrimes uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 2711553Srgrimes uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 2721553Srgrimes uint8_t ah_ispcie; /* PCIE, special treatment */ 2731553Srgrimes 2741553Srgrimes HAL_OPMODE ah_opmode; /* operating mode from reset */ 2751553Srgrimes const struct ieee80211_channel *ah_curchan;/* operating channel */ 2761553Srgrimes HAL_CAPABILITIES ah_caps; /* device capabilities */ 2771553Srgrimes uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 2781553Srgrimes int16_t ah_powerLimit; /* tx power cap */ 2791553Srgrimes uint16_t ah_maxPowerLevel; /* calculated max tx power */ 2801553Srgrimes u_int ah_tpScale; /* tx power scale factor */ 2811553Srgrimes uint32_t ah_11nCompat; /* 11n compat controls */ 2821553Srgrimes 2831553Srgrimes /* 2841553Srgrimes * State for regulatory domain handling. 2851553Srgrimes */ 28630642Scharnier HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 2871553Srgrimes HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 2881553Srgrimes u_int ah_nchan; /* valid items in ah_channels */ 2891553Srgrimes const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 2901553Srgrimes const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 2911553Srgrimes 2921553Srgrimes uint8_t ah_coverageClass; /* coverage class */ 2931553Srgrimes /* 2941553Srgrimes * RF Silent handling; setup according to the EEPROM. 2951553Srgrimes */ 2961553Srgrimes uint16_t ah_rfsilent; /* GPIO pin + polarity */ 2971553Srgrimes HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 29830642Scharnier /* 2991553Srgrimes * Diagnostic support for discriminating HIUERR reports. 3001553Srgrimes */ 3011553Srgrimes uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 3021553Srgrimes int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 3031553Srgrimes}; 3041553Srgrimes 3051553Srgrimes#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 30630642Scharnier 3071553Srgrimes#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 3081553Srgrimes AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 3091553Srgrimes#define ath_hal_getWirelessModes(_ah) \ 3101553Srgrimes AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 3111553Srgrimes#define ath_hal_eepromRead(_ah, _off, _data) \ 3121553Srgrimes AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 3131553Srgrimes#define ath_hal_eepromWrite(_ah, _off, _data) \ 3141553Srgrimes AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 3151553Srgrimes#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 3161553Srgrimes (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type) 31730642Scharnier#define ath_hal_gpioCfgInput(_ah, _gpio) \ 3181553Srgrimes (_ah)->ah_gpioCfgInput(_ah, _gpio) 3191553Srgrimes#define ath_hal_gpioGet(_ah, _gpio) \ 3201553Srgrimes (_ah)->ah_gpioGet(_ah, _gpio) 3211553Srgrimes#define ath_hal_gpioSet(_ah, _gpio, _val) \ 3221553Srgrimes (_ah)->ah_gpioSet(_ah, _gpio, _val) 3231553Srgrimes#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 3241553Srgrimes (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 3251553Srgrimes#define ath_hal_getpowerlimits(_ah, _chan) \ 3261553Srgrimes AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 32728547Sjlemon#define ath_hal_getNfAdjust(_ah, _c) \ 3281553Srgrimes AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 3291553Srgrimes#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 33030642Scharnier AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 3311553Srgrimes#define ath_hal_configPCIE(_ah, _reset) \ 3321553Srgrimes (_ah)->ah_configPCIE(_ah, _reset) 3331553Srgrimes#define ath_hal_disablePCIE(_ah) \ 3341553Srgrimes (_ah)->ah_disablePCIE(_ah) 3351553Srgrimes 3361553Srgrimes#define ath_hal_eepromDetach(_ah) \ 3371553Srgrimes AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 3381553Srgrimes#define ath_hal_eepromGet(_ah, _param, _val) \ 3391553Srgrimes AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 3401553Srgrimes#define ath_hal_eepromSet(_ah, _param, _val) \ 3411553Srgrimes AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 3421553Srgrimes#define ath_hal_eepromGetFlag(_ah, _param) \ 3431553Srgrimes (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 34430642Scharnier#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 34530642Scharnier AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 3461553Srgrimes#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 3471553Srgrimes AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 3481553Srgrimes 3491553Srgrimes#ifndef _NET_IF_IEEE80211_H_ 3501553Srgrimes/* 3511553Srgrimes * Stuff that would naturally come from _ieee80211.h 3521553Srgrimes */ 3531553Srgrimes#define IEEE80211_ADDR_LEN 6 3541553Srgrimes 3551553Srgrimes#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 3561553Srgrimes#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 3571553Srgrimes#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 3581553Srgrimes 3591553Srgrimes#define IEEE80211_CRC_LEN 4 3601553Srgrimes 3611553Srgrimes#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 3621553Srgrimes (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 3631553Srgrimes#endif /* _NET_IF_IEEE80211_H_ */ 3641553Srgrimes 3651553Srgrimes#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 3661553Srgrimes 3671553Srgrimes#define INIT_AIFS 2 3681553Srgrimes#define INIT_CWMIN 15 3691553Srgrimes#define INIT_CWMIN_11B 31 3701553Srgrimes#define INIT_CWMAX 1023 3711553Srgrimes#define INIT_SH_RETRY 10 3721553Srgrimes#define INIT_LG_RETRY 10 3731553Srgrimes#define INIT_SSH_RETRY 32 3741553Srgrimes#define INIT_SLG_RETRY 32 3751553Srgrimes 376299707Spfgtypedef struct { 3771553Srgrimes uint32_t tqi_ver; /* HAL TXQ verson */ 3781553Srgrimes HAL_TX_QUEUE tqi_type; /* hw queue type*/ 3791553Srgrimes HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 3801553Srgrimes HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 3811553Srgrimes uint32_t tqi_priority; 3821553Srgrimes uint32_t tqi_aifs; /* aifs */ 3831553Srgrimes uint32_t tqi_cwmin; /* cwMin */ 3841553Srgrimes uint32_t tqi_cwmax; /* cwMax */ 3851553Srgrimes uint16_t tqi_shretry; /* frame short retry limit */ 3861553Srgrimes uint16_t tqi_lgretry; /* frame long retry limit */ 3871553Srgrimes uint32_t tqi_cbrPeriod; 3881553Srgrimes uint32_t tqi_cbrOverflowLimit; 3891553Srgrimes uint32_t tqi_burstTime; 3901553Srgrimes uint32_t tqi_readyTime; 3911553Srgrimes uint32_t tqi_physCompBuf; 3921553Srgrimes uint32_t tqi_intFlags; /* flags for internal use */ 3931553Srgrimes} HAL_TX_QUEUE_INFO; 3941553Srgrimes 3951553Srgrimesextern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 3961553Srgrimes HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 3971553Srgrimesextern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 3981553Srgrimes HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 3991553Srgrimes 4001553Srgrimestypedef enum { 4011553Srgrimes HAL_ANI_PRESENT, /* is ANI support present */ 4021553Srgrimes HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 4031553Srgrimes HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 4041553Srgrimes HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 4051553Srgrimes HAL_ANI_FIRSTEP_LEVEL, /* set level */ 4061553Srgrimes HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 4071553Srgrimes HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 4081553Srgrimes HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 4091553Srgrimes} HAL_ANI_CMD; 4101553Srgrimes 4111553Srgrimes#define HAL_SPUR_VAL_MASK 0x3FFF 4121553Srgrimes#define HAL_SPUR_CHAN_WIDTH 87 4131553Srgrimes#define HAL_BIN_WIDTH_BASE_100HZ 3125 4141553Srgrimes#define HAL_BIN_WIDTH_TURBO_100HZ 6250 4151553Srgrimes#define HAL_MAX_BINS_ALLOWED 28 416240388Skevlo 4171553Srgrimes#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 4181553Srgrimes#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 419240388Skevlo 4201553Srgrimes#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 4211553Srgrimes 4221553Srgrimes/* 4231553Srgrimes * Deduce if the host cpu has big- or litt-endian byte order. 4241553Srgrimes */ 4251553Srgrimesstatic __inline__ int 4261553SrgrimesisBigEndian(void) 4271553Srgrimes{ 4281553Srgrimes union { 4291553Srgrimes int32_t i; 4301553Srgrimes char c[4]; 43130642Scharnier } u; 432246209Scharnier u.i = 1; 43330642Scharnier return (u.c[0] == 0); 43430642Scharnier} 43530642Scharnier 43630642Scharnier/* unalligned little endian access */ 43730642Scharnier#define LE_READ_2(p) \ 43830642Scharnier ((uint16_t) \ 43930642Scharnier ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 44030642Scharnier#define LE_READ_4(p) \ 44130642Scharnier ((uint32_t) \ 44230642Scharnier ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 44330642Scharnier (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 4441553Srgrimes 4451553Srgrimes/* 4461553Srgrimes * Register manipulation macros that expect bit field defines 4471553Srgrimes * to follow the convention that an _S suffix is appended for 448246209Scharnier * a shift count, while the field mask has no suffix. 4491553Srgrimes */ 4501553Srgrimes#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 4511553Srgrimes#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 4521553Srgrimes#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 4531553Srgrimes OS_REG_WRITE(_a, _r, \ 4541553Srgrimes (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 4551553Srgrimes#define OS_REG_SET_BIT(_a, _r, _f) \ 4561553Srgrimes OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 4571553Srgrimes#define OS_REG_CLR_BIT(_a, _r, _f) \ 458299709Spfg OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 4591553Srgrimes 4601553Srgrimes/* system-configurable parameters */ 4611553Srgrimesextern int ath_hal_dma_beacon_response_time; /* in TU's */ 4621553Srgrimesextern int ath_hal_sw_beacon_response_time; /* in TU's */ 4631553Srgrimesextern int ath_hal_additional_swba_backoff; /* in TU's */ 4641553Srgrimes 4651553Srgrimes/* wait for the register contents to have the specified value */ 4661553Srgrimesextern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 4671553Srgrimes uint32_t mask, uint32_t val); 46830830Scharnier 4691553Srgrimes/* return the first n bits in val reversed */ 4701553Srgrimesextern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 4711553Srgrimes 4721553Srgrimes/* printf interfaces */ 473246209Scharnierextern void ath_hal_printf(struct ath_hal *, const char*, ...) 4741553Srgrimes __printflike(2,3); 4751553Srgrimesextern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 4761553Srgrimes __printflike(2, 0); 4771553Srgrimesextern const char* ath_hal_ether_sprintf(const uint8_t *mac); 4781553Srgrimes 4791553Srgrimes/* allocate and free memory */ 4801553Srgrimesextern void *ath_hal_malloc(size_t); 4811553Srgrimesextern void ath_hal_free(void *); 4821553Srgrimes 4831553Srgrimes/* common debugging interfaces */ 4841553Srgrimes#ifdef AH_DEBUG 48530830Scharnier#include "ah_debug.h" 4861553Srgrimesextern int ath_hal_debug; 4871553Srgrimesextern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 488299707Spfg __printflike(3,4); 4891553Srgrimes#else 4901553Srgrimes#define HALDEBUG(_ah, __m, _fmt, ...) 491299707Spfg#endif /* AH_DEBUG */ 4921553Srgrimes 493299707Spfg/* 4941553Srgrimes * Register logging definitions shared with ardecode. 4951553Srgrimes */ 4961553Srgrimes#include "ah_decode.h" 4971553Srgrimes 4981553Srgrimes/* 4991553Srgrimes * Common assertion interface. Note: it is a bad idea to generate 5001553Srgrimes * an assertion failure for any recoverable event. Instead catch 5011553Srgrimes * the violation and, if possible, fix it up or recover from it; either 5021553Srgrimes * with an error return value or a diagnostic messages. System software 5031553Srgrimes * does not panic unless the situation is hopeless. 504299707Spfg */ 5051553Srgrimes#ifdef AH_ASSERT 5061553Srgrimesextern void ath_hal_assert_failed(const char* filename, 5071553Srgrimes int lineno, const char* msg); 5081553Srgrimes 5091553Srgrimes#define HALASSERT(_x) do { \ 5101553Srgrimes if (!(_x)) { \ 5111553Srgrimes ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 5121553Srgrimes } \ 5131553Srgrimes} while (0) 514299707Spfg#else 5151553Srgrimes#define HALASSERT(_x) 5161553Srgrimes#endif /* AH_ASSERT */ 5171553Srgrimes 5181553Srgrimes/* 5191553Srgrimes * Regulatory domain support. 5201553Srgrimes */ 5211553Srgrimes 5221553Srgrimes/* 5231553Srgrimes * Return the max allowed antenna gain and apply any regulatory 524299707Spfg * domain specific changes. 5251553Srgrimes */ 5261553Srgrimesu_int ath_hal_getantennareduction(struct ath_hal *ah, 5271553Srgrimes const struct ieee80211_channel *chan, u_int twiceGain); 5281553Srgrimes 5291553Srgrimes/* 5301553Srgrimes * Return the test group for the specific channel based on 5311553Srgrimes * the current regulatory setup. 5321553Srgrimes */ 5331553Srgrimesu_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 5341553Srgrimes 5351553Srgrimes/* 5361553Srgrimes * Map a public channel definition to the corresponding 5371553Srgrimes * internal data structure. This implicitly specifies 5381553Srgrimes * whether or not the specified channel is ok to use 5391553Srgrimes * based on the current regulatory domain constraints. 54030830Scharnier */ 5411553Srgrimes#ifndef AH_DEBUG 5421553Srgrimesstatic OS_INLINE HAL_CHANNEL_INTERNAL * 5431553Srgrimesath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 5441553Srgrimes{ 5451553Srgrimes HAL_CHANNEL_INTERNAL *cc; 5461553Srgrimes 5471553Srgrimes HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 5481553Srgrimes cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 5491553Srgrimes HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 5501553Srgrimes return cc; 5511553Srgrimes} 5521553Srgrimes#else 5531553Srgrimes/* NB: non-inline version that checks state */ 5541553SrgrimesHAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 5551553Srgrimes const struct ieee80211_channel *); 5561553Srgrimes#endif /* AH_DEBUG */ 5571553Srgrimes 55830830Scharnier/* 5591553Srgrimes * Return the h/w frequency for a channel. This may be 5601553Srgrimes * different from ic_freq if this is a GSM device that 5611553Srgrimes * takes 2.4GHz frequencies and down-converts them. 5621553Srgrimes */ 5631553Srgrimesstatic OS_INLINE uint16_t 5641553Srgrimesath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 5651553Srgrimes{ 5661553Srgrimes return ath_hal_checkchannel(ah, c)->channel; 5671553Srgrimes} 5681553Srgrimes 5691553Srgrimes/* 5701553Srgrimes * Convert between microseconds and core system clocks. 5711553Srgrimes */ 572246209Scharnierextern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 5731553Srgrimesextern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 5741553Srgrimes 5751553Srgrimes/* 5761553Srgrimes * Generic get/set capability support. Each chip overrides 5771553Srgrimes * this routine to support chip-specific capabilities. 5781553Srgrimes */ 5791553Srgrimesextern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 5801553Srgrimes HAL_CAPABILITY_TYPE type, uint32_t capability, 5811553Srgrimes uint32_t *result); 5821553Srgrimesextern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 5831553Srgrimes HAL_CAPABILITY_TYPE type, uint32_t capability, 5841553Srgrimes uint32_t setting, HAL_STATUS *status); 5851553Srgrimes 5861553Srgrimes/* 5871553Srgrimes * Diagnostic interface. This is an open-ended interface that 5881553Srgrimes * is opaque to applications. Diagnostic programs use this to 5891553Srgrimes * retrieve internal data structures, etc. There is no guarantee 5901553Srgrimes * that calling conventions for calls other than HAL_DIAG_REVS 5911553Srgrimes * are stable between HAL releases; a diagnostic application must 5921553Srgrimes * use the HAL revision information to deal with ABI/API differences. 5931553Srgrimes * 5941553Srgrimes * NB: do not renumber these, certain codes are publicly used. 5951553Srgrimes */ 5961553Srgrimesenum { 5971553Srgrimes HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 5981553Srgrimes HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 5991553Srgrimes HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 6001553Srgrimes HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 6011553Srgrimes HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 6021553Srgrimes HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 6031553Srgrimes HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 6041553Srgrimes HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 6051553Srgrimes HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 6061553Srgrimes HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 6071553Srgrimes HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 6081553Srgrimes HAL_DIAG_PCDAC = 11, /* PCDAC table */ 6091553Srgrimes HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 6101553Srgrimes HAL_DIAG_REGS = 13, /* Registers */ 6111553Srgrimes HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 6121553Srgrimes HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 6131553Srgrimes HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 6141553Srgrimes HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 6151553Srgrimes HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 6161553Srgrimes /* 19-26 removed, do not reuse */ 6171553Srgrimes HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 6181553Srgrimes HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 6191553Srgrimes HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 62037268Sbde HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 62137268Sbde HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 6221553Srgrimes HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 6231553Srgrimes HAL_DIAG_SETREGS = 33, /* write registers */ 6241553Srgrimes}; 625246209Scharnier 6261553Srgrimesenum { 6271553Srgrimes HAL_BB_HANG_DFS = 0x0001, 6281553Srgrimes HAL_BB_HANG_RIFS = 0x0002, 6291553Srgrimes HAL_BB_HANG_RX_CLEAR = 0x0004, 6301553Srgrimes HAL_BB_HANG_UNKNOWN = 0x0080, 6311553Srgrimes 6321553Srgrimes HAL_MAC_HANG_SIG1 = 0x0100, 6331553Srgrimes HAL_MAC_HANG_SIG2 = 0x0200, 6341553Srgrimes HAL_MAC_HANG_UNKNOWN = 0x8000, 6351553Srgrimes 6361553Srgrimes HAL_BB_HANGS = HAL_BB_HANG_DFS 6371553Srgrimes | HAL_BB_HANG_RIFS 6381553Srgrimes | HAL_BB_HANG_RX_CLEAR 6391553Srgrimes | HAL_BB_HANG_UNKNOWN, 640246209Scharnier HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 6411553Srgrimes | HAL_MAC_HANG_SIG2 6421553Srgrimes | HAL_MAC_HANG_UNKNOWN, 6431553Srgrimes}; 6441553Srgrimes 6451553Srgrimes/* 6461553Srgrimes * Device revision information. 6471553Srgrimes */ 6481553Srgrimestypedef struct { 6491553Srgrimes uint16_t ah_devid; /* PCI device ID */ 6501553Srgrimes uint16_t ah_subvendorid; /* PCI subvendor ID */ 6511553Srgrimes uint32_t ah_macVersion; /* MAC version id */ 6521553Srgrimes uint16_t ah_macRev; /* MAC revision */ 6531553Srgrimes uint16_t ah_phyRev; /* PHY revision */ 6541553Srgrimes uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 6551553Srgrimes uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 6561553Srgrimes} HAL_REVS; 6571553Srgrimes 6581553Srgrimes/* 6591553Srgrimes * Argument payload for HAL_DIAG_SETKEY. 6601553Srgrimes */ 6611553Srgrimestypedef struct { 662246209Scharnier HAL_KEYVAL dk_keyval; 6631553Srgrimes uint16_t dk_keyix; /* key index */ 664299707Spfg uint8_t dk_mac[IEEE80211_ADDR_LEN]; 6651553Srgrimes int dk_xor; /* XOR key data */ 6661553Srgrimes} HAL_DIAG_KEYVAL; 6671553Srgrimes 6681553Srgrimes/* 669299707Spfg * Argument payload for HAL_DIAG_EEWRITE. 670299707Spfg */ 6711553Srgrimestypedef struct { 6721553Srgrimes uint16_t ee_off; /* eeprom offset */ 6731553Srgrimes uint16_t ee_data; /* write data */ 6741553Srgrimes} HAL_DIAG_EEVAL; 6751553Srgrimes 6761553Srgrimes 6771553Srgrimestypedef struct { 6781553Srgrimes u_int offset; /* reg offset */ 6791553Srgrimes uint32_t val; /* reg value */ 6801553Srgrimes} HAL_DIAG_REGVAL; 6811553Srgrimes 682246209Scharnier/* 6831553Srgrimes * 11n compatibility tweaks. 6841553Srgrimes */ 6851553Srgrimes#define HAL_DIAG_11N_SERVICES 0x00000003 6861553Srgrimes#define HAL_DIAG_11N_SERVICES_S 0 6871553Srgrimes#define HAL_DIAG_11N_TXSTOMP 0x0000000c 6881553Srgrimes#define HAL_DIAG_11N_TXSTOMP_S 2 6891553Srgrimes 6901553Srgrimestypedef struct { 691246209Scharnier int maxNoiseImmunityLevel; /* [0..4] */ 6921553Srgrimes int totalSizeDesired[5]; 69337268Sbde int coarseHigh[5]; 6941553Srgrimes int coarseLow[5]; 695239991Sed int firpwr[5]; 69637268Sbde 6971553Srgrimes int maxSpurImmunityLevel; /* [0..7] */ 6981553Srgrimes int cycPwrThr1[8]; 6991553Srgrimes 700246209Scharnier int maxFirstepLevel; /* [0..2] */ 7011553Srgrimes int firstep[3]; 7021553Srgrimes 7031553Srgrimes uint32_t ofdmTrigHigh; 7041553Srgrimes uint32_t ofdmTrigLow; 7051553Srgrimes int32_t cckTrigHigh; 7061553Srgrimes int32_t cckTrigLow; 707299707Spfg int32_t rssiThrLow; 70830642Scharnier int32_t rssiThrHigh; 7091553Srgrimes 7101553Srgrimes int period; /* update listen period */ 7111553Srgrimes} HAL_ANI_PARAMS; 7121553Srgrimes 713246209Scharnierextern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 714246209Scharnier const void *args, uint32_t argsize, 715246209Scharnier void **result, uint32_t *resultsize); 7161553Srgrimes 717246209Scharnier/* 7181553Srgrimes * Setup a h/w rate table for use. 7191553Srgrimes */ 7201553Srgrimesextern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 7211553Srgrimes 7221553Srgrimes/* 7231553Srgrimes * Common routine for implementing getChanNoise api. 7241553Srgrimes */ 7251553Srgrimesint16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 7261553Srgrimes 7271553Srgrimes/* 7281553Srgrimes * Initialization support. 7291553Srgrimes */ 7301553Srgrimestypedef struct { 7311553Srgrimes const uint32_t *data; 7321553Srgrimes int rows, cols; 7331553Srgrimes} HAL_INI_ARRAY; 7341553Srgrimes 735299707Spfg#define HAL_INI_INIT(_ia, _data, _cols) do { \ 73630642Scharnier (_ia)->data = (const uint32_t *)(_data); \ 7371553Srgrimes (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 7381553Srgrimes (_ia)->cols = (_cols); \ 7391553Srgrimes} while (0) 7401553Srgrimes#define HAL_INI_VAL(_ia, _r, _c) \ 7411553Srgrimes ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 7421553Srgrimes 743246209Scharnier/* 7441553Srgrimes * OS_DELAY() does a PIO READ on the PCI bus which allows 7451553Srgrimes * other cards' DMA reads to complete in the middle of our reset. 7461553Srgrimes */ 7471553Srgrimes#define DMA_YIELD(x) do { \ 74830642Scharnier if ((++(x) % 64) == 0) \ 74930642Scharnier OS_DELAY(1); \ 7501553Srgrimes} while (0) 7511553Srgrimes 75230642Scharnier#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 7531553Srgrimes int r; \ 7541553Srgrimes for (r = 0; r < N(regArray); r++) { \ 7551553Srgrimes OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 7561553Srgrimes DMA_YIELD(regWr); \ 757299707Spfg } \ 7581553Srgrimes} while (0) 7591553Srgrimes 7601553Srgrimes#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 7611553Srgrimes int r; \ 7621553Srgrimes for (r = 0; r < N(regArray); r++) { \ 7631553Srgrimes OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 7641553Srgrimes DMA_YIELD(regWr); \ 7651553Srgrimes } \ 7661553Srgrimes} while (0) 7671553Srgrimes 7681553Srgrimesextern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 7691553Srgrimes int col, int regWr); 770299707Spfgextern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 7711553Srgrimes int col); 7721553Srgrimesextern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 773299707Spfg const uint32_t data[], int regWr); 7741553Srgrimes 7751553Srgrimes#define CCK_SIFS_TIME 10 7761553Srgrimes#define CCK_PREAMBLE_BITS 144 7771553Srgrimes#define CCK_PLCP_BITS 48 7781553Srgrimes 7791553Srgrimes#define OFDM_SIFS_TIME 16 7801553Srgrimes#define OFDM_PREAMBLE_TIME 20 7811553Srgrimes#define OFDM_PLCP_BITS 22 7821553Srgrimes#define OFDM_SYMBOL_TIME 4 7831553Srgrimes 7841553Srgrimes#define OFDM_HALF_SIFS_TIME 32 7851553Srgrimes#define OFDM_HALF_PREAMBLE_TIME 40 7861553Srgrimes#define OFDM_HALF_PLCP_BITS 22 7871553Srgrimes#define OFDM_HALF_SYMBOL_TIME 8 7881553Srgrimes 7891553Srgrimes#define OFDM_QUARTER_SIFS_TIME 64 7901553Srgrimes#define OFDM_QUARTER_PREAMBLE_TIME 80 7911553Srgrimes#define OFDM_QUARTER_PLCP_BITS 22 7921553Srgrimes#define OFDM_QUARTER_SYMBOL_TIME 16 7931553Srgrimes 7941553Srgrimes#define TURBO_SIFS_TIME 8 795299707Spfg#define TURBO_PREAMBLE_TIME 14 7961553Srgrimes#define TURBO_PLCP_BITS 22 7971553Srgrimes#define TURBO_SYMBOL_TIME 4 7981553Srgrimes 7991553Srgrimes#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 8001553Srgrimes#endif /* _ATH_AH_INTERAL_H_ */ 8011553Srgrimes