ah_internal.h revision 188970
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 188970 2009-02-23 23:48:17Z sam $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84}; 85#ifndef AH_CHIP 86#define AH_CHIP(_name, _probe, _attach) \ 87static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91}; \ 92OS_DATA_SET(ah_chips, _name##_chip) 93#endif 94 95/* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104}; 105#ifndef AH_RF 106#define AH_RF(_name, _probe, _attach) \ 107static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111}; \ 112OS_DATA_SET(ah_rfs, _name##_rf) 113#endif 114 115struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117/* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124#ifndef AH_MAXCHAN 125#define AH_MAXCHAN 96 126#endif 127 128/* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144} HAL_CHANNEL_INTERNAL; 145 146/* channel requires noise floor check */ 147#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149/* all full-width channels */ 150#define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152#define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1; 197 uint32_t halWirelessModes; 198 uint16_t halTotalQueues; 199 uint16_t halKeyCacheSize; 200 uint16_t halLow5GhzChan, halHigh5GhzChan; 201 uint16_t halLow2GhzChan, halHigh2GhzChan; 202 int halTstampPrecision; 203 int halRtsAggrLimit; 204 uint8_t halTxChainMask; 205 uint8_t halRxChainMask; 206 uint8_t halNumGpioPins; 207 uint8_t halNumAntCfg2GHz; 208 uint8_t halNumAntCfg5GHz; 209} HAL_CAPABILITIES; 210 211struct regDomain; 212 213/* 214 * The ``private area'' follows immediately after the ``public area'' 215 * in the data structure returned by ath_hal_attach. Private data are 216 * used by device-independent code such as the regulatory domain support. 217 * In general, code within the HAL should never depend on data in the 218 * public area. Instead any public data needed internally should be 219 * shadowed here. 220 * 221 * When declaring a device-specific ath_hal data structure this structure 222 * is assumed to at the front; e.g. 223 * 224 * struct ath_hal_5212 { 225 * struct ath_hal_private ah_priv; 226 * ... 227 * }; 228 * 229 * It might be better to manage the method pointers in this structure 230 * using an indirect pointer to a read-only data structure but this would 231 * disallow class-style method overriding. 232 */ 233struct ath_hal_private { 234 struct ath_hal h; /* public area */ 235 236 /* NB: all methods go first to simplify initialization */ 237 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 238 uint16_t channelFlags, 239 uint16_t *lowChannel, uint16_t *highChannel); 240 u_int (*ah_getWirelessModes)(struct ath_hal*); 241 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 242 uint16_t *data); 243 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 244 uint16_t data); 245 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 246 struct ieee80211_channel *); 247 int16_t (*ah_getNfAdjust)(struct ath_hal *, 248 const HAL_CHANNEL_INTERNAL*); 249 void (*ah_getNoiseFloor)(struct ath_hal *, 250 int16_t nfarray[]); 251 252 void *ah_eeprom; /* opaque EEPROM state */ 253 uint16_t ah_eeversion; /* EEPROM version */ 254 void (*ah_eepromDetach)(struct ath_hal *); 255 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 256 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 257 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 258 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 259 const void *args, uint32_t argsize, 260 void **result, uint32_t *resultsize); 261 262 /* 263 * Device revision information. 264 */ 265 uint16_t ah_devid; /* PCI device ID */ 266 uint16_t ah_subvendorid; /* PCI subvendor ID */ 267 uint32_t ah_macVersion; /* MAC version id */ 268 uint16_t ah_macRev; /* MAC revision */ 269 uint16_t ah_phyRev; /* PHY revision */ 270 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 271 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 272 273 HAL_OPMODE ah_opmode; /* operating mode from reset */ 274 const struct ieee80211_channel *ah_curchan;/* operating channel */ 275 HAL_CAPABILITIES ah_caps; /* device capabilities */ 276 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 277 int16_t ah_powerLimit; /* tx power cap */ 278 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 279 u_int ah_tpScale; /* tx power scale factor */ 280 uint32_t ah_11nCompat; /* 11n compat controls */ 281 282 /* 283 * State for regulatory domain handling. 284 */ 285 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 286 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 287 u_int ah_nchan; /* valid items in ah_channels */ 288 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 289 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 290 291 uint8_t ah_coverageClass; /* coverage class */ 292 /* 293 * RF Silent handling; setup according to the EEPROM. 294 */ 295 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 296 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 297 /* 298 * Diagnostic support for discriminating HIUERR reports. 299 */ 300 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 301 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 302}; 303 304#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 305 306#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 307 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 308#define ath_hal_getWirelessModes(_ah) \ 309 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 310#define ath_hal_eepromRead(_ah, _off, _data) \ 311 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 312#define ath_hal_eepromWrite(_ah, _off, _data) \ 313 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 314#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 315 (_ah)->ah_gpioCfgOutput(_ah, _gpio) 316#define ath_hal_gpioCfgInput(_ah, _gpio) \ 317 (_ah)->ah_gpioCfgInput(_ah, _gpio) 318#define ath_hal_gpioGet(_ah, _gpio) \ 319 (_ah)->ah_gpioGet(_ah, _gpio) 320#define ath_hal_gpioSet(_ah, _gpio, _val) \ 321 (_ah)->ah_gpioSet(_ah, _gpio, _val) 322#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 323 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 324#define ath_hal_getpowerlimits(_ah, _chan) \ 325 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 326#define ath_hal_getNfAdjust(_ah, _c) \ 327 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 328#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 329 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 330 331#define ath_hal_eepromDetach(_ah) \ 332 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 333#define ath_hal_eepromGet(_ah, _param, _val) \ 334 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 335#define ath_hal_eepromSet(_ah, _param, _val) \ 336 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 337#define ath_hal_eepromGetFlag(_ah, _param) \ 338 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 339#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 340 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 341#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 342 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 343 344#ifndef _NET_IF_IEEE80211_H_ 345/* 346 * Stuff that would naturally come from _ieee80211.h 347 */ 348#define IEEE80211_ADDR_LEN 6 349 350#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 351#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 352#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 353 354#define IEEE80211_CRC_LEN 4 355 356#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 357 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 358#endif /* _NET_IF_IEEE80211_H_ */ 359 360#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 361 362#define INIT_AIFS 2 363#define INIT_CWMIN 15 364#define INIT_CWMIN_11B 31 365#define INIT_CWMAX 1023 366#define INIT_SH_RETRY 10 367#define INIT_LG_RETRY 10 368#define INIT_SSH_RETRY 32 369#define INIT_SLG_RETRY 32 370 371typedef struct { 372 uint32_t tqi_ver; /* HAL TXQ verson */ 373 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 374 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 375 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 376 uint32_t tqi_priority; 377 uint32_t tqi_aifs; /* aifs */ 378 uint32_t tqi_cwmin; /* cwMin */ 379 uint32_t tqi_cwmax; /* cwMax */ 380 uint16_t tqi_shretry; /* frame short retry limit */ 381 uint16_t tqi_lgretry; /* frame long retry limit */ 382 uint32_t tqi_cbrPeriod; 383 uint32_t tqi_cbrOverflowLimit; 384 uint32_t tqi_burstTime; 385 uint32_t tqi_readyTime; 386 uint32_t tqi_physCompBuf; 387 uint32_t tqi_intFlags; /* flags for internal use */ 388} HAL_TX_QUEUE_INFO; 389 390extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 391 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 392extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 393 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 394 395typedef enum { 396 HAL_ANI_PRESENT, /* is ANI support present */ 397 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 398 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 399 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 400 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 401 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 402 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 403 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 404} HAL_ANI_CMD; 405 406#define HAL_SPUR_VAL_MASK 0x3FFF 407#define HAL_SPUR_CHAN_WIDTH 87 408#define HAL_BIN_WIDTH_BASE_100HZ 3125 409#define HAL_BIN_WIDTH_TURBO_100HZ 6250 410#define HAL_MAX_BINS_ALLOWED 28 411 412#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 413#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 414 415#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 416 417/* 418 * Deduce if the host cpu has big- or litt-endian byte order. 419 */ 420static __inline__ int 421isBigEndian(void) 422{ 423 union { 424 int32_t i; 425 char c[4]; 426 } u; 427 u.i = 1; 428 return (u.c[0] == 0); 429} 430 431/* unalligned little endian access */ 432#define LE_READ_2(p) \ 433 ((uint16_t) \ 434 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 435#define LE_READ_4(p) \ 436 ((uint32_t) \ 437 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 438 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 439 440/* 441 * Register manipulation macros that expect bit field defines 442 * to follow the convention that an _S suffix is appended for 443 * a shift count, while the field mask has no suffix. 444 */ 445#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 446#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 447#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 448 OS_REG_WRITE(_a, _r, \ 449 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 450#define OS_REG_SET_BIT(_a, _r, _f) \ 451 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 452#define OS_REG_CLR_BIT(_a, _r, _f) \ 453 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 454 455/* system-configurable parameters */ 456extern int ath_hal_dma_beacon_response_time; /* in TU's */ 457extern int ath_hal_sw_beacon_response_time; /* in TU's */ 458extern int ath_hal_additional_swba_backoff; /* in TU's */ 459 460/* wait for the register contents to have the specified value */ 461extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 462 uint32_t mask, uint32_t val); 463 464/* return the first n bits in val reversed */ 465extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 466 467/* printf interfaces */ 468extern void ath_hal_printf(struct ath_hal *, const char*, ...) 469 __printflike(2,3); 470extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 471 __printflike(2, 0); 472extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 473 474/* allocate and free memory */ 475extern void *ath_hal_malloc(size_t); 476extern void ath_hal_free(void *); 477 478/* common debugging interfaces */ 479#ifdef AH_DEBUG 480#include "ah_debug.h" 481extern int ath_hal_debug; 482extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 483 __printflike(3,4); 484#else 485#define HALDEBUG(_ah, __m, _fmt, ...) 486#endif /* AH_DEBUG */ 487 488/* 489 * Register logging definitions shared with ardecode. 490 */ 491#include "ah_decode.h" 492 493/* 494 * Common assertion interface. Note: it is a bad idea to generate 495 * an assertion failure for any recoverable event. Instead catch 496 * the violation and, if possible, fix it up or recover from it; either 497 * with an error return value or a diagnostic messages. System software 498 * does not panic unless the situation is hopeless. 499 */ 500#ifdef AH_ASSERT 501extern void ath_hal_assert_failed(const char* filename, 502 int lineno, const char* msg); 503 504#define HALASSERT(_x) do { \ 505 if (!(_x)) { \ 506 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 507 } \ 508} while (0) 509#else 510#define HALASSERT(_x) 511#endif /* AH_ASSERT */ 512 513/* 514 * Regulatory domain support. 515 */ 516 517/* 518 * Return the max allowed antenna gain and apply any regulatory 519 * domain specific changes. 520 */ 521u_int ath_hal_getantennareduction(struct ath_hal *ah, 522 const struct ieee80211_channel *chan, u_int twiceGain); 523 524/* 525 * Return the test group for the specific channel based on 526 * the current regulatory setup. 527 */ 528u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 529 530/* 531 * Map a public channel definition to the corresponding 532 * internal data structure. This implicitly specifies 533 * whether or not the specified channel is ok to use 534 * based on the current regulatory domain constraints. 535 */ 536#ifndef AH_DEBUG 537static OS_INLINE HAL_CHANNEL_INTERNAL * 538ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 539{ 540 HAL_CHANNEL_INTERNAL *cc; 541 542 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 543 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 544 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 545 return cc; 546} 547#else 548/* NB: non-inline version that checks state */ 549HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 550 const struct ieee80211_channel *); 551#endif /* AH_DEBUG */ 552 553/* 554 * Return the h/w frequency for a channel. This may be 555 * different from ic_freq if this is a GSM device that 556 * takes 2.4GHz frequencies and down-converts them. 557 */ 558static OS_INLINE uint16_t 559ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 560{ 561 return ath_hal_checkchannel(ah, c)->channel; 562} 563 564/* 565 * Convert between microseconds and core system clocks. 566 */ 567extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 568extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 569 570/* 571 * Generic get/set capability support. Each chip overrides 572 * this routine to support chip-specific capabilities. 573 */ 574extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 575 HAL_CAPABILITY_TYPE type, uint32_t capability, 576 uint32_t *result); 577extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 578 HAL_CAPABILITY_TYPE type, uint32_t capability, 579 uint32_t setting, HAL_STATUS *status); 580 581/* 582 * Diagnostic interface. This is an open-ended interface that 583 * is opaque to applications. Diagnostic programs use this to 584 * retrieve internal data structures, etc. There is no guarantee 585 * that calling conventions for calls other than HAL_DIAG_REVS 586 * are stable between HAL releases; a diagnostic application must 587 * use the HAL revision information to deal with ABI/API differences. 588 * 589 * NB: do not renumber these, certain codes are publicly used. 590 */ 591enum { 592 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 593 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 594 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 595 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 596 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 597 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 598 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 599 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 600 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 601 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 602 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 603 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 604 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 605 HAL_DIAG_REGS = 13, /* Registers */ 606 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 607 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 608 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 609 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 610 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 611 /* 19-26 removed, do not reuse */ 612 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 613 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 614 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 615 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 616 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 617 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 618 HAL_DIAG_SETREGS = 33, /* write registers */ 619}; 620 621enum { 622 HAL_BB_HANG_DFS = 0x0001, 623 HAL_BB_HANG_RIFS = 0x0002, 624 HAL_BB_HANG_RX_CLEAR = 0x0004, 625 HAL_BB_HANG_UNKNOWN = 0x0080, 626 627 HAL_MAC_HANG_SIG1 = 0x0100, 628 HAL_MAC_HANG_SIG2 = 0x0200, 629 HAL_MAC_HANG_UNKNOWN = 0x8000, 630 631 HAL_BB_HANGS = HAL_BB_HANG_DFS 632 | HAL_BB_HANG_RIFS 633 | HAL_BB_HANG_RX_CLEAR 634 | HAL_BB_HANG_UNKNOWN, 635 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 636 | HAL_MAC_HANG_SIG2 637 | HAL_MAC_HANG_UNKNOWN, 638}; 639 640/* 641 * Device revision information. 642 */ 643typedef struct { 644 uint16_t ah_devid; /* PCI device ID */ 645 uint16_t ah_subvendorid; /* PCI subvendor ID */ 646 uint32_t ah_macVersion; /* MAC version id */ 647 uint16_t ah_macRev; /* MAC revision */ 648 uint16_t ah_phyRev; /* PHY revision */ 649 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 650 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 651} HAL_REVS; 652 653/* 654 * Argument payload for HAL_DIAG_SETKEY. 655 */ 656typedef struct { 657 HAL_KEYVAL dk_keyval; 658 uint16_t dk_keyix; /* key index */ 659 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 660 int dk_xor; /* XOR key data */ 661} HAL_DIAG_KEYVAL; 662 663/* 664 * Argument payload for HAL_DIAG_EEWRITE. 665 */ 666typedef struct { 667 uint16_t ee_off; /* eeprom offset */ 668 uint16_t ee_data; /* write data */ 669} HAL_DIAG_EEVAL; 670 671 672typedef struct { 673 u_int offset; /* reg offset */ 674 uint32_t val; /* reg value */ 675} HAL_DIAG_REGVAL; 676 677/* 678 * 11n compatibility tweaks. 679 */ 680#define HAL_DIAG_11N_SERVICES 0x00000003 681#define HAL_DIAG_11N_SERVICES_S 0 682#define HAL_DIAG_11N_TXSTOMP 0x0000000c 683#define HAL_DIAG_11N_TXSTOMP_S 2 684 685typedef struct { 686 int maxNoiseImmunityLevel; /* [0..4] */ 687 int totalSizeDesired[5]; 688 int coarseHigh[5]; 689 int coarseLow[5]; 690 int firpwr[5]; 691 692 int maxSpurImmunityLevel; /* [0..7] */ 693 int cycPwrThr1[8]; 694 695 int maxFirstepLevel; /* [0..2] */ 696 int firstep[3]; 697 698 uint32_t ofdmTrigHigh; 699 uint32_t ofdmTrigLow; 700 int32_t cckTrigHigh; 701 int32_t cckTrigLow; 702 int32_t rssiThrLow; 703 int32_t rssiThrHigh; 704 705 int period; /* update listen period */ 706} HAL_ANI_PARAMS; 707 708extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 709 const void *args, uint32_t argsize, 710 void **result, uint32_t *resultsize); 711 712/* 713 * Setup a h/w rate table for use. 714 */ 715extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 716 717/* 718 * Common routine for implementing getChanNoise api. 719 */ 720int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 721 722/* 723 * Initialization support. 724 */ 725typedef struct { 726 const uint32_t *data; 727 int rows, cols; 728} HAL_INI_ARRAY; 729 730#define HAL_INI_INIT(_ia, _data, _cols) do { \ 731 (_ia)->data = (const uint32_t *)(_data); \ 732 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 733 (_ia)->cols = (_cols); \ 734} while (0) 735#define HAL_INI_VAL(_ia, _r, _c) \ 736 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 737 738/* 739 * OS_DELAY() does a PIO READ on the PCI bus which allows 740 * other cards' DMA reads to complete in the middle of our reset. 741 */ 742#define DMA_YIELD(x) do { \ 743 if ((++(x) % 64) == 0) \ 744 OS_DELAY(1); \ 745} while (0) 746 747#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 748 int r; \ 749 for (r = 0; r < N(regArray); r++) { \ 750 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 751 DMA_YIELD(regWr); \ 752 } \ 753} while (0) 754 755#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 756 int r; \ 757 for (r = 0; r < N(regArray); r++) { \ 758 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 759 DMA_YIELD(regWr); \ 760 } \ 761} while (0) 762 763extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 764 int col, int regWr); 765extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 766 int col); 767extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 768 const uint32_t data[], int regWr); 769 770#define CCK_SIFS_TIME 10 771#define CCK_PREAMBLE_BITS 144 772#define CCK_PLCP_BITS 48 773 774#define OFDM_SIFS_TIME 16 775#define OFDM_PREAMBLE_TIME 20 776#define OFDM_PLCP_BITS 22 777#define OFDM_SYMBOL_TIME 4 778 779#define OFDM_HALF_SIFS_TIME 32 780#define OFDM_HALF_PREAMBLE_TIME 40 781#define OFDM_HALF_PLCP_BITS 22 782#define OFDM_HALF_SYMBOL_TIME 8 783 784#define OFDM_QUARTER_SIFS_TIME 64 785#define OFDM_QUARTER_PREAMBLE_TIME 80 786#define OFDM_QUARTER_PLCP_BITS 22 787#define OFDM_QUARTER_SYMBOL_TIME 16 788 789#define TURBO_SIFS_TIME 8 790#define TURBO_PREAMBLE_TIME 14 791#define TURBO_PLCP_BITS 22 792#define TURBO_SYMBOL_TIME 4 793 794#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 795#endif /* _ATH_AH_INTERAL_H_ */ 796