ah_internal.h revision 188771
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 188771 2009-02-19 04:15:14Z sam $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52typedef struct { 53 uint32_t addr; /* regiser address/offset */ 54 uint32_t value; /* value to write */ 55} HAL_REGWRITE; 56 57/* 58 * Transmit power scale factor. 59 * 60 * NB: This is not public because we want to discourage the use of 61 * scaling; folks should use the tx power limit interface. 62 */ 63typedef enum { 64 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 65 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 66 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 67 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 68 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 69} HAL_TP_SCALE; 70 71typedef enum { 72 HAL_CAP_RADAR = 0, /* Radar capability */ 73 HAL_CAP_AR = 1, /* AR capability */ 74} HAL_PHYDIAG_CAPS; 75 76/* 77 * Each chip or class of chips registers to offer support. 78 */ 79struct ath_hal_chip { 80 const char *name; 81 const char *(*probe)(uint16_t vendorid, uint16_t devid); 82 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 83 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 84}; 85#ifndef AH_CHIP 86#define AH_CHIP(_name, _probe, _attach) \ 87static struct ath_hal_chip _name##_chip = { \ 88 .name = #_name, \ 89 .probe = _probe, \ 90 .attach = _attach \ 91}; \ 92OS_DATA_SET(ah_chips, _name##_chip) 93#endif 94 95/* 96 * Each RF backend registers to offer support; this is mostly 97 * used by multi-chip 5212 solutions. Single-chip solutions 98 * have a fixed idea about which RF to use. 99 */ 100struct ath_hal_rf { 101 const char *name; 102 HAL_BOOL (*probe)(struct ath_hal *ah); 103 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 104}; 105#ifndef AH_RF 106#define AH_RF(_name, _probe, _attach) \ 107static struct ath_hal_rf _name##_rf = { \ 108 .name = __STRING(_name), \ 109 .probe = _probe, \ 110 .attach = _attach \ 111}; \ 112OS_DATA_SET(ah_rfs, _name##_rf) 113#endif 114 115struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 116 117/* 118 * Maximum number of internal channels. Entries are per unique 119 * frequency so this might be need to be increased to handle all 120 * usage cases; typically no more than 32 are really needed but 121 * dynamically allocating the data structures is a bit painful 122 * right now. 123 */ 124#ifndef AH_MAXCHAN 125#define AH_MAXCHAN 96 126#endif 127 128/* 129 * Internal per-channel state. These are found 130 * using ic_devdata in the ieee80211_channel. 131 */ 132typedef struct { 133 uint16_t channel; /* h/w frequency, NB: may be mapped */ 134 uint8_t privFlags; 135#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 136#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 137#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 138 uint8_t calValid; /* bitmask of cal types */ 139 int8_t iCoff; 140 int8_t qCoff; 141 int16_t rawNoiseFloor; 142 int16_t noiseFloorAdjust; 143 uint16_t mainSpur; /* cached spur value for this channel */ 144} HAL_CHANNEL_INTERNAL; 145 146/* channel requires noise floor check */ 147#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 148 149/* all full-width channels */ 150#define IEEE80211_CHAN_ALLFULL \ 151 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 152#define IEEE80211_CHAN_ALLTURBOFULL \ 153 (IEEE80211_CHAN_ALLTURBO - \ 154 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 155 156typedef struct { 157 uint32_t halChanSpreadSupport : 1, 158 halSleepAfterBeaconBroken : 1, 159 halCompressSupport : 1, 160 halBurstSupport : 1, 161 halFastFramesSupport : 1, 162 halChapTuningSupport : 1, 163 halTurboGSupport : 1, 164 halTurboPrimeSupport : 1, 165 halMicAesCcmSupport : 1, 166 halMicCkipSupport : 1, 167 halMicTkipSupport : 1, 168 halTkipMicTxRxKeySupport : 1, 169 halCipherAesCcmSupport : 1, 170 halCipherCkipSupport : 1, 171 halCipherTkipSupport : 1, 172 halPSPollBroken : 1, 173 halVEOLSupport : 1, 174 halBssIdMaskSupport : 1, 175 halMcastKeySrchSupport : 1, 176 halTsfAddSupport : 1, 177 halChanHalfRate : 1, 178 halChanQuarterRate : 1, 179 halHTSupport : 1, 180 halRfSilentSupport : 1, 181 halHwPhyCounterSupport : 1, 182 halWowSupport : 1, 183 halWowMatchPatternExact : 1, 184 halAutoSleepSupport : 1, 185 halFastCCSupport : 1, 186 halBtCoexSupport : 1; 187 uint32_t halRxStbcSupport : 1, 188 halTxStbcSupport : 1, 189 halGTTSupport : 1, 190 halCSTSupport : 1, 191 halRifsRxSupport : 1, 192 halRifsTxSupport : 1, 193 halExtChanDfsSupport : 1, 194 halForcePpmSupport : 1, 195 halEnhancedPmSupport : 1, 196 halMbssidAggrSupport : 1; 197 uint32_t halWirelessModes; 198 uint16_t halTotalQueues; 199 uint16_t halKeyCacheSize; 200 uint16_t halLow5GhzChan, halHigh5GhzChan; 201 uint16_t halLow2GhzChan, halHigh2GhzChan; 202 int halTstampPrecision; 203 int halRtsAggrLimit; 204 uint8_t halTxChainMask; 205 uint8_t halRxChainMask; 206 uint8_t halNumGpioPins; 207 uint8_t halNumAntCfg2GHz; 208 uint8_t halNumAntCfg5GHz; 209} HAL_CAPABILITIES; 210 211struct regDomain; 212 213/* 214 * The ``private area'' follows immediately after the ``public area'' 215 * in the data structure returned by ath_hal_attach. Private data are 216 * used by device-independent code such as the regulatory domain support. 217 * In general, code within the HAL should never depend on data in the 218 * public area. Instead any public data needed internally should be 219 * shadowed here. 220 * 221 * When declaring a device-specific ath_hal data structure this structure 222 * is assumed to at the front; e.g. 223 * 224 * struct ath_hal_5212 { 225 * struct ath_hal_private ah_priv; 226 * ... 227 * }; 228 * 229 * It might be better to manage the method pointers in this structure 230 * using an indirect pointer to a read-only data structure but this would 231 * disallow class-style method overriding. 232 */ 233struct ath_hal_private { 234 struct ath_hal h; /* public area */ 235 236 /* NB: all methods go first to simplify initialization */ 237 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 238 uint16_t channelFlags, 239 uint16_t *lowChannel, uint16_t *highChannel); 240 u_int (*ah_getWirelessModes)(struct ath_hal*); 241 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 242 uint16_t *data); 243 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 244 uint16_t data); 245 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 246 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 247 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 248 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 249 uint32_t gpio, uint32_t val); 250 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 251 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 252 struct ieee80211_channel *); 253 int16_t (*ah_getNfAdjust)(struct ath_hal *, 254 const HAL_CHANNEL_INTERNAL*); 255 void (*ah_getNoiseFloor)(struct ath_hal *, 256 int16_t nfarray[]); 257 258 void *ah_eeprom; /* opaque EEPROM state */ 259 uint16_t ah_eeversion; /* EEPROM version */ 260 void (*ah_eepromDetach)(struct ath_hal *); 261 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 262 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 263 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 264 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 265 const void *args, uint32_t argsize, 266 void **result, uint32_t *resultsize); 267 268 /* 269 * Device revision information. 270 */ 271 uint16_t ah_devid; /* PCI device ID */ 272 uint16_t ah_subvendorid; /* PCI subvendor ID */ 273 uint32_t ah_macVersion; /* MAC version id */ 274 uint16_t ah_macRev; /* MAC revision */ 275 uint16_t ah_phyRev; /* PHY revision */ 276 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 277 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 278 279 HAL_OPMODE ah_opmode; /* operating mode from reset */ 280 const struct ieee80211_channel *ah_curchan;/* operating channel */ 281 HAL_CAPABILITIES ah_caps; /* device capabilities */ 282 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 283 int16_t ah_powerLimit; /* tx power cap */ 284 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 285 u_int ah_tpScale; /* tx power scale factor */ 286 uint32_t ah_11nCompat; /* 11n compat controls */ 287 288 /* 289 * State for regulatory domain handling. 290 */ 291 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 292 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 293 u_int ah_nchan; /* valid items in ah_channels */ 294 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 295 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 296 297 uint8_t ah_coverageClass; /* coverage class */ 298 /* 299 * RF Silent handling; setup according to the EEPROM. 300 */ 301 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 302 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 303 /* 304 * Diagnostic support for discriminating HIUERR reports. 305 */ 306 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 307 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 308}; 309 310#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 311 312#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 313 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 314#define ath_hal_getWirelessModes(_ah) \ 315 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 316#define ath_hal_eepromRead(_ah, _off, _data) \ 317 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 318#define ath_hal_eepromWrite(_ah, _off, _data) \ 319 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 320#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 321 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 322#define ath_hal_gpioCfgInput(_ah, _gpio) \ 323 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 324#define ath_hal_gpioGet(_ah, _gpio) \ 325 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 326#define ath_hal_gpioSet(_ah, _gpio, _val) \ 327 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 328#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 329 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 330#define ath_hal_getpowerlimits(_ah, _chan) \ 331 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 332#define ath_hal_getNfAdjust(_ah, _c) \ 333 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 334#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 335 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 336 337#define ath_hal_eepromDetach(_ah) \ 338 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 339#define ath_hal_eepromGet(_ah, _param, _val) \ 340 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 341#define ath_hal_eepromSet(_ah, _param, _val) \ 342 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 343#define ath_hal_eepromGetFlag(_ah, _param) \ 344 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 345#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 346 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 347#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 348 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 349 350#ifndef _NET_IF_IEEE80211_H_ 351/* 352 * Stuff that would naturally come from _ieee80211.h 353 */ 354#define IEEE80211_ADDR_LEN 6 355 356#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 357#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 358#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 359 360#define IEEE80211_CRC_LEN 4 361 362#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 363 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 364#endif /* _NET_IF_IEEE80211_H_ */ 365 366#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 367 368#define INIT_AIFS 2 369#define INIT_CWMIN 15 370#define INIT_CWMIN_11B 31 371#define INIT_CWMAX 1023 372#define INIT_SH_RETRY 10 373#define INIT_LG_RETRY 10 374#define INIT_SSH_RETRY 32 375#define INIT_SLG_RETRY 32 376 377typedef struct { 378 uint32_t tqi_ver; /* HAL TXQ verson */ 379 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 380 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 381 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 382 uint32_t tqi_priority; 383 uint32_t tqi_aifs; /* aifs */ 384 uint32_t tqi_cwmin; /* cwMin */ 385 uint32_t tqi_cwmax; /* cwMax */ 386 uint16_t tqi_shretry; /* frame short retry limit */ 387 uint16_t tqi_lgretry; /* frame long retry limit */ 388 uint32_t tqi_cbrPeriod; 389 uint32_t tqi_cbrOverflowLimit; 390 uint32_t tqi_burstTime; 391 uint32_t tqi_readyTime; 392 uint32_t tqi_physCompBuf; 393 uint32_t tqi_intFlags; /* flags for internal use */ 394} HAL_TX_QUEUE_INFO; 395 396extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 397 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 398extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 399 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 400 401typedef enum { 402 HAL_ANI_PRESENT, /* is ANI support present */ 403 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 404 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 405 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 406 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 407 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 408 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 409 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 410} HAL_ANI_CMD; 411 412#define HAL_SPUR_VAL_MASK 0x3FFF 413#define HAL_SPUR_CHAN_WIDTH 87 414#define HAL_BIN_WIDTH_BASE_100HZ 3125 415#define HAL_BIN_WIDTH_TURBO_100HZ 6250 416#define HAL_MAX_BINS_ALLOWED 28 417 418#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 419#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 420 421#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 422 423/* 424 * Deduce if the host cpu has big- or litt-endian byte order. 425 */ 426static __inline__ int 427isBigEndian(void) 428{ 429 union { 430 int32_t i; 431 char c[4]; 432 } u; 433 u.i = 1; 434 return (u.c[0] == 0); 435} 436 437/* unalligned little endian access */ 438#define LE_READ_2(p) \ 439 ((uint16_t) \ 440 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 441#define LE_READ_4(p) \ 442 ((uint32_t) \ 443 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 444 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 445 446/* 447 * Register manipulation macros that expect bit field defines 448 * to follow the convention that an _S suffix is appended for 449 * a shift count, while the field mask has no suffix. 450 */ 451#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 452#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 453#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 454 OS_REG_WRITE(_a, _r, \ 455 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 456#define OS_REG_SET_BIT(_a, _r, _f) \ 457 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 458#define OS_REG_CLR_BIT(_a, _r, _f) \ 459 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 460 461/* system-configurable parameters */ 462extern int ath_hal_dma_beacon_response_time; /* in TU's */ 463extern int ath_hal_sw_beacon_response_time; /* in TU's */ 464extern int ath_hal_additional_swba_backoff; /* in TU's */ 465 466/* wait for the register contents to have the specified value */ 467extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 468 uint32_t mask, uint32_t val); 469 470/* return the first n bits in val reversed */ 471extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 472 473/* printf interfaces */ 474extern void ath_hal_printf(struct ath_hal *, const char*, ...) 475 __printflike(2,3); 476extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 477 __printflike(2, 0); 478extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 479 480/* allocate and free memory */ 481extern void *ath_hal_malloc(size_t); 482extern void ath_hal_free(void *); 483 484/* common debugging interfaces */ 485#ifdef AH_DEBUG 486#include "ah_debug.h" 487extern int ath_hal_debug; 488extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 489 __printflike(3,4); 490#else 491#define HALDEBUG(_ah, __m, _fmt, ...) 492#endif /* AH_DEBUG */ 493 494/* 495 * Register logging definitions shared with ardecode. 496 */ 497#include "ah_decode.h" 498 499/* 500 * Common assertion interface. Note: it is a bad idea to generate 501 * an assertion failure for any recoverable event. Instead catch 502 * the violation and, if possible, fix it up or recover from it; either 503 * with an error return value or a diagnostic messages. System software 504 * does not panic unless the situation is hopeless. 505 */ 506#ifdef AH_ASSERT 507extern void ath_hal_assert_failed(const char* filename, 508 int lineno, const char* msg); 509 510#define HALASSERT(_x) do { \ 511 if (!(_x)) { \ 512 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 513 } \ 514} while (0) 515#else 516#define HALASSERT(_x) 517#endif /* AH_ASSERT */ 518 519/* 520 * Regulatory domain support. 521 */ 522 523/* 524 * Return the max allowed antenna gain and apply any regulatory 525 * domain specific changes. 526 */ 527u_int ath_hal_getantennareduction(struct ath_hal *ah, 528 const struct ieee80211_channel *chan, u_int twiceGain); 529 530/* 531 * Return the test group for the specific channel based on 532 * the current regulatory setup. 533 */ 534u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 535 536/* 537 * Map a public channel definition to the corresponding 538 * internal data structure. This implicitly specifies 539 * whether or not the specified channel is ok to use 540 * based on the current regulatory domain constraints. 541 */ 542#ifndef AH_DEBUG 543static OS_INLINE HAL_CHANNEL_INTERNAL * 544ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 545{ 546 HAL_CHANNEL_INTERNAL *cc; 547 548 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 549 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 550 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 551 return cc; 552} 553#else 554/* NB: non-inline version that checks state */ 555HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 556 const struct ieee80211_channel *); 557#endif /* AH_DEBUG */ 558 559/* 560 * Return the h/w frequency for a channel. This may be 561 * different from ic_freq if this is a GSM device that 562 * takes 2.4GHz frequencies and down-converts them. 563 */ 564static OS_INLINE uint16_t 565ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 566{ 567 return ath_hal_checkchannel(ah, c)->channel; 568} 569 570/* 571 * Convert between microseconds and core system clocks. 572 */ 573extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 574extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 575 576/* 577 * Generic get/set capability support. Each chip overrides 578 * this routine to support chip-specific capabilities. 579 */ 580extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 581 HAL_CAPABILITY_TYPE type, uint32_t capability, 582 uint32_t *result); 583extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 584 HAL_CAPABILITY_TYPE type, uint32_t capability, 585 uint32_t setting, HAL_STATUS *status); 586 587/* 588 * Diagnostic interface. This is an open-ended interface that 589 * is opaque to applications. Diagnostic programs use this to 590 * retrieve internal data structures, etc. There is no guarantee 591 * that calling conventions for calls other than HAL_DIAG_REVS 592 * are stable between HAL releases; a diagnostic application must 593 * use the HAL revision information to deal with ABI/API differences. 594 * 595 * NB: do not renumber these, certain codes are publicly used. 596 */ 597enum { 598 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 599 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 600 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 601 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 602 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 603 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 604 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 605 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 606 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 607 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 608 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 609 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 610 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 611 HAL_DIAG_REGS = 13, /* Registers */ 612 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 613 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 614 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 615 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 616 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 617 /* 19-26 removed, do not reuse */ 618 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 619 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 620 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 621 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 622 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 623 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 624 HAL_DIAG_SETREGS = 33, /* write registers */ 625}; 626 627enum { 628 HAL_BB_HANG_DFS = 0x0001, 629 HAL_BB_HANG_RIFS = 0x0002, 630 HAL_BB_HANG_RX_CLEAR = 0x0004, 631 HAL_BB_HANG_UNKNOWN = 0x0080, 632 633 HAL_MAC_HANG_SIG1 = 0x0100, 634 HAL_MAC_HANG_SIG2 = 0x0200, 635 HAL_MAC_HANG_UNKNOWN = 0x8000, 636 637 HAL_BB_HANGS = HAL_BB_HANG_DFS 638 | HAL_BB_HANG_RIFS 639 | HAL_BB_HANG_RX_CLEAR 640 | HAL_BB_HANG_UNKNOWN, 641 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 642 | HAL_MAC_HANG_SIG2 643 | HAL_MAC_HANG_UNKNOWN, 644}; 645 646/* 647 * Device revision information. 648 */ 649typedef struct { 650 uint16_t ah_devid; /* PCI device ID */ 651 uint16_t ah_subvendorid; /* PCI subvendor ID */ 652 uint32_t ah_macVersion; /* MAC version id */ 653 uint16_t ah_macRev; /* MAC revision */ 654 uint16_t ah_phyRev; /* PHY revision */ 655 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 656 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 657} HAL_REVS; 658 659/* 660 * Argument payload for HAL_DIAG_SETKEY. 661 */ 662typedef struct { 663 HAL_KEYVAL dk_keyval; 664 uint16_t dk_keyix; /* key index */ 665 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 666 int dk_xor; /* XOR key data */ 667} HAL_DIAG_KEYVAL; 668 669/* 670 * Argument payload for HAL_DIAG_EEWRITE. 671 */ 672typedef struct { 673 uint16_t ee_off; /* eeprom offset */ 674 uint16_t ee_data; /* write data */ 675} HAL_DIAG_EEVAL; 676 677 678typedef struct { 679 u_int offset; /* reg offset */ 680 uint32_t val; /* reg value */ 681} HAL_DIAG_REGVAL; 682 683/* 684 * 11n compatibility tweaks. 685 */ 686#define HAL_DIAG_11N_SERVICES 0x00000003 687#define HAL_DIAG_11N_SERVICES_S 0 688#define HAL_DIAG_11N_TXSTOMP 0x0000000c 689#define HAL_DIAG_11N_TXSTOMP_S 2 690 691typedef struct { 692 int maxNoiseImmunityLevel; /* [0..4] */ 693 int totalSizeDesired[5]; 694 int coarseHigh[5]; 695 int coarseLow[5]; 696 int firpwr[5]; 697 698 int maxSpurImmunityLevel; /* [0..7] */ 699 int cycPwrThr1[8]; 700 701 int maxFirstepLevel; /* [0..2] */ 702 int firstep[3]; 703 704 uint32_t ofdmTrigHigh; 705 uint32_t ofdmTrigLow; 706 int32_t cckTrigHigh; 707 int32_t cckTrigLow; 708 int32_t rssiThrLow; 709 int32_t rssiThrHigh; 710 711 int period; /* update listen period */ 712} HAL_ANI_PARAMS; 713 714extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 715 const void *args, uint32_t argsize, 716 void **result, uint32_t *resultsize); 717 718/* 719 * Setup a h/w rate table for use. 720 */ 721extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 722 723/* 724 * Common routine for implementing getChanNoise api. 725 */ 726int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 727 728/* 729 * Initialization support. 730 */ 731typedef struct { 732 const uint32_t *data; 733 int rows, cols; 734} HAL_INI_ARRAY; 735 736#define HAL_INI_INIT(_ia, _data, _cols) do { \ 737 (_ia)->data = (const uint32_t *)(_data); \ 738 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 739 (_ia)->cols = (_cols); \ 740} while (0) 741#define HAL_INI_VAL(_ia, _r, _c) \ 742 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 743 744/* 745 * OS_DELAY() does a PIO READ on the PCI bus which allows 746 * other cards' DMA reads to complete in the middle of our reset. 747 */ 748#define DMA_YIELD(x) do { \ 749 if ((++(x) % 64) == 0) \ 750 OS_DELAY(1); \ 751} while (0) 752 753#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 754 int r; \ 755 for (r = 0; r < N(regArray); r++) { \ 756 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 757 DMA_YIELD(regWr); \ 758 } \ 759} while (0) 760 761#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 762 int r; \ 763 for (r = 0; r < N(regArray); r++) { \ 764 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 765 DMA_YIELD(regWr); \ 766 } \ 767} while (0) 768 769extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 770 int col, int regWr); 771extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 772 int col); 773extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 774 const uint32_t data[], int regWr); 775 776#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 777#endif /* _ATH_AH_INTERAL_H_ */ 778