ah_internal.h revision 188504
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 188504 2009-02-11 22:34:22Z sam $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#include <net80211/_ieee80211.h> 31 32#ifndef NBBY 33#define NBBY 8 /* number of bits/byte */ 34#endif 35 36#ifndef roundup 37#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38#endif 39#ifndef howmany 40#define howmany(x, y) (((x)+((y)-1))/(y)) 41#endif 42 43#ifndef offsetof 44#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45#endif 46 47typedef struct { 48 uint16_t start; /* first register */ 49 uint16_t end; /* ending register or zero */ 50} HAL_REGRANGE; 51 52/* 53 * Transmit power scale factor. 54 * 55 * NB: This is not public because we want to discourage the use of 56 * scaling; folks should use the tx power limit interface. 57 */ 58typedef enum { 59 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 60 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 61 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 62 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 63 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 64} HAL_TP_SCALE; 65 66typedef enum { 67 HAL_CAP_RADAR = 0, /* Radar capability */ 68 HAL_CAP_AR = 1, /* AR capability */ 69} HAL_PHYDIAG_CAPS; 70 71/* 72 * Each chip or class of chips registers to offer support. 73 */ 74struct ath_hal_chip { 75 const char *name; 76 const char *(*probe)(uint16_t vendorid, uint16_t devid); 77 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 78 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 79}; 80#ifndef AH_CHIP 81#define AH_CHIP(_name, _probe, _attach) \ 82static struct ath_hal_chip _name##_chip = { \ 83 .name = #_name, \ 84 .probe = _probe, \ 85 .attach = _attach \ 86}; \ 87OS_DATA_SET(ah_chips, _name##_chip) 88#endif 89 90/* 91 * Each RF backend registers to offer support; this is mostly 92 * used by multi-chip 5212 solutions. Single-chip solutions 93 * have a fixed idea about which RF to use. 94 */ 95struct ath_hal_rf { 96 const char *name; 97 HAL_BOOL (*probe)(struct ath_hal *ah); 98 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 99}; 100#ifndef AH_RF 101#define AH_RF(_name, _probe, _attach) \ 102static struct ath_hal_rf _name##_rf = { \ 103 .name = __STRING(_name), \ 104 .probe = _probe, \ 105 .attach = _attach \ 106}; \ 107OS_DATA_SET(ah_rfs, _name##_rf) 108#endif 109 110struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 111 112/* 113 * Maximum number of internal channels. Entries are per unique 114 * frequency so this might be need to be increased to handle all 115 * usage cases; typically no more than 32 are really needed but 116 * dynamically allocating the data structures is a bit painful 117 * right now. 118 */ 119#ifndef AH_MAXCHAN 120#define AH_MAXCHAN 96 121#endif 122 123/* 124 * Internal per-channel state. These are found 125 * using ic_devdata in the ieee80211_channel. 126 */ 127typedef struct { 128 uint16_t channel; /* h/w frequency, NB: may be mapped */ 129 uint8_t privFlags; 130#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 131#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 132#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 133 uint8_t calValid; /* bitmask of cal types */ 134 int8_t iCoff; 135 int8_t qCoff; 136 int16_t rawNoiseFloor; 137 int16_t noiseFloorAdjust; 138 uint16_t mainSpur; /* cached spur value for this channel */ 139} HAL_CHANNEL_INTERNAL; 140 141/* channel requires noise floor check */ 142#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 143 144/* all full-width channels */ 145#define IEEE80211_CHAN_ALLFULL \ 146 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 147#define IEEE80211_CHAN_ALLTURBOFULL \ 148 (IEEE80211_CHAN_ALLTURBO - \ 149 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 150 151typedef struct { 152 uint32_t halChanSpreadSupport : 1, 153 halSleepAfterBeaconBroken : 1, 154 halCompressSupport : 1, 155 halBurstSupport : 1, 156 halFastFramesSupport : 1, 157 halChapTuningSupport : 1, 158 halTurboGSupport : 1, 159 halTurboPrimeSupport : 1, 160 halMicAesCcmSupport : 1, 161 halMicCkipSupport : 1, 162 halMicTkipSupport : 1, 163 halTkipMicTxRxKeySupport : 1, 164 halCipherAesCcmSupport : 1, 165 halCipherCkipSupport : 1, 166 halCipherTkipSupport : 1, 167 halPSPollBroken : 1, 168 halVEOLSupport : 1, 169 halBssIdMaskSupport : 1, 170 halMcastKeySrchSupport : 1, 171 halTsfAddSupport : 1, 172 halChanHalfRate : 1, 173 halChanQuarterRate : 1, 174 halHTSupport : 1, 175 halRfSilentSupport : 1, 176 halHwPhyCounterSupport : 1, 177 halWowSupport : 1, 178 halWowMatchPatternExact : 1, 179 halAutoSleepSupport : 1, 180 halFastCCSupport : 1, 181 halBtCoexSupport : 1; 182 uint32_t halRxStbcSupport : 1, 183 halTxStbcSupport : 1, 184 halGTTSupport : 1, 185 halCSTSupport : 1, 186 halRifsRxSupport : 1, 187 halRifsTxSupport : 1, 188 halExtChanDfsSupport : 1, 189 halForcePpmSupport : 1, 190 halEnhancedPmSupport : 1, 191 halMbssidAggrSupport : 1; 192 uint32_t halWirelessModes; 193 uint16_t halTotalQueues; 194 uint16_t halKeyCacheSize; 195 uint16_t halLow5GhzChan, halHigh5GhzChan; 196 uint16_t halLow2GhzChan, halHigh2GhzChan; 197 int halTstampPrecision; 198 int halRtsAggrLimit; 199 uint8_t halTxChainMask; 200 uint8_t halRxChainMask; 201 uint8_t halNumGpioPins; 202 uint8_t halNumAntCfg2GHz; 203 uint8_t halNumAntCfg5GHz; 204} HAL_CAPABILITIES; 205 206struct regDomain; 207 208/* 209 * The ``private area'' follows immediately after the ``public area'' 210 * in the data structure returned by ath_hal_attach. Private data are 211 * used by device-independent code such as the regulatory domain support. 212 * In general, code within the HAL should never depend on data in the 213 * public area. Instead any public data needed internally should be 214 * shadowed here. 215 * 216 * When declaring a device-specific ath_hal data structure this structure 217 * is assumed to at the front; e.g. 218 * 219 * struct ath_hal_5212 { 220 * struct ath_hal_private ah_priv; 221 * ... 222 * }; 223 * 224 * It might be better to manage the method pointers in this structure 225 * using an indirect pointer to a read-only data structure but this would 226 * disallow class-style method overriding. 227 */ 228struct ath_hal_private { 229 struct ath_hal h; /* public area */ 230 231 /* NB: all methods go first to simplify initialization */ 232 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 233 uint16_t channelFlags, 234 uint16_t *lowChannel, uint16_t *highChannel); 235 u_int (*ah_getWirelessModes)(struct ath_hal*); 236 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 237 uint16_t *data); 238 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 239 uint16_t data); 240 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 241 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 242 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 243 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 244 uint32_t gpio, uint32_t val); 245 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 246 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 247 struct ieee80211_channel *); 248 int16_t (*ah_getNfAdjust)(struct ath_hal *, 249 const HAL_CHANNEL_INTERNAL*); 250 void (*ah_getNoiseFloor)(struct ath_hal *, 251 int16_t nfarray[]); 252 253 void *ah_eeprom; /* opaque EEPROM state */ 254 uint16_t ah_eeversion; /* EEPROM version */ 255 void (*ah_eepromDetach)(struct ath_hal *); 256 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 257 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 258 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 259 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 260 const void *args, uint32_t argsize, 261 void **result, uint32_t *resultsize); 262 263 /* 264 * Device revision information. 265 */ 266 uint16_t ah_devid; /* PCI device ID */ 267 uint16_t ah_subvendorid; /* PCI subvendor ID */ 268 uint32_t ah_macVersion; /* MAC version id */ 269 uint16_t ah_macRev; /* MAC revision */ 270 uint16_t ah_phyRev; /* PHY revision */ 271 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 272 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 273 274 HAL_OPMODE ah_opmode; /* operating mode from reset */ 275 const struct ieee80211_channel *ah_curchan;/* operating channel */ 276 HAL_CAPABILITIES ah_caps; /* device capabilities */ 277 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 278 int16_t ah_powerLimit; /* tx power cap */ 279 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 280 u_int ah_tpScale; /* tx power scale factor */ 281 uint32_t ah_11nCompat; /* 11n compat controls */ 282 283 /* 284 * State for regulatory domain handling. 285 */ 286 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 287 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 288 u_int ah_nchan; /* valid items in ah_channels */ 289 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 290 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 291 292 uint8_t ah_coverageClass; /* coverage class */ 293 /* 294 * RF Silent handling; setup according to the EEPROM. 295 */ 296 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 297 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 298 /* 299 * Diagnostic support for discriminating HIUERR reports. 300 */ 301 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 302 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 303}; 304 305#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 306 307#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 308 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 309#define ath_hal_getWirelessModes(_ah) \ 310 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 311#define ath_hal_eepromRead(_ah, _off, _data) \ 312 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 313#define ath_hal_eepromWrite(_ah, _off, _data) \ 314 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 315#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 316 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 317#define ath_hal_gpioCfgInput(_ah, _gpio) \ 318 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 319#define ath_hal_gpioGet(_ah, _gpio) \ 320 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 321#define ath_hal_gpioSet(_ah, _gpio, _val) \ 322 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 323#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 324 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 325#define ath_hal_getpowerlimits(_ah, _chan) \ 326 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 327#define ath_hal_getNfAdjust(_ah, _c) \ 328 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 329#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 330 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 331 332#define ath_hal_eepromDetach(_ah) \ 333 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 334#define ath_hal_eepromGet(_ah, _param, _val) \ 335 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 336#define ath_hal_eepromSet(_ah, _param, _val) \ 337 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 338#define ath_hal_eepromGetFlag(_ah, _param) \ 339 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 340#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 341 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 342#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 343 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 344 345#ifndef _NET_IF_IEEE80211_H_ 346/* 347 * Stuff that would naturally come from _ieee80211.h 348 */ 349#define IEEE80211_ADDR_LEN 6 350 351#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 352#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 353#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 354 355#define IEEE80211_CRC_LEN 4 356 357#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 358 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 359#endif /* _NET_IF_IEEE80211_H_ */ 360 361#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 362 363#define INIT_AIFS 2 364#define INIT_CWMIN 15 365#define INIT_CWMIN_11B 31 366#define INIT_CWMAX 1023 367#define INIT_SH_RETRY 10 368#define INIT_LG_RETRY 10 369#define INIT_SSH_RETRY 32 370#define INIT_SLG_RETRY 32 371 372typedef struct { 373 uint32_t tqi_ver; /* HAL TXQ verson */ 374 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 375 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 376 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 377 uint32_t tqi_priority; 378 uint32_t tqi_aifs; /* aifs */ 379 uint32_t tqi_cwmin; /* cwMin */ 380 uint32_t tqi_cwmax; /* cwMax */ 381 uint16_t tqi_shretry; /* frame short retry limit */ 382 uint16_t tqi_lgretry; /* frame long retry limit */ 383 uint32_t tqi_cbrPeriod; 384 uint32_t tqi_cbrOverflowLimit; 385 uint32_t tqi_burstTime; 386 uint32_t tqi_readyTime; 387 uint32_t tqi_physCompBuf; 388 uint32_t tqi_intFlags; /* flags for internal use */ 389} HAL_TX_QUEUE_INFO; 390 391extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 392 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 393extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 394 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 395 396typedef enum { 397 HAL_ANI_PRESENT, /* is ANI support present */ 398 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 399 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 400 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 401 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 402 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 403 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 404 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 405} HAL_ANI_CMD; 406 407#define HAL_SPUR_VAL_MASK 0x3FFF 408#define HAL_SPUR_CHAN_WIDTH 87 409#define HAL_BIN_WIDTH_BASE_100HZ 3125 410#define HAL_BIN_WIDTH_TURBO_100HZ 6250 411#define HAL_MAX_BINS_ALLOWED 28 412 413#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 414#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 415 416#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 417 418/* 419 * Deduce if the host cpu has big- or litt-endian byte order. 420 */ 421static __inline__ int 422isBigEndian(void) 423{ 424 union { 425 int32_t i; 426 char c[4]; 427 } u; 428 u.i = 1; 429 return (u.c[0] == 0); 430} 431 432/* unalligned little endian access */ 433#define LE_READ_2(p) \ 434 ((uint16_t) \ 435 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 436#define LE_READ_4(p) \ 437 ((uint32_t) \ 438 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 439 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 440 441/* 442 * Register manipulation macros that expect bit field defines 443 * to follow the convention that an _S suffix is appended for 444 * a shift count, while the field mask has no suffix. 445 */ 446#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 447#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 448#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 449 OS_REG_WRITE(_a, _r, \ 450 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 451#define OS_REG_SET_BIT(_a, _r, _f) \ 452 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 453#define OS_REG_CLR_BIT(_a, _r, _f) \ 454 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 455 456/* system-configurable parameters */ 457extern int ath_hal_dma_beacon_response_time; /* in TU's */ 458extern int ath_hal_sw_beacon_response_time; /* in TU's */ 459extern int ath_hal_additional_swba_backoff; /* in TU's */ 460 461/* wait for the register contents to have the specified value */ 462extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 463 uint32_t mask, uint32_t val); 464 465/* return the first n bits in val reversed */ 466extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 467 468/* printf interfaces */ 469extern void ath_hal_printf(struct ath_hal *, const char*, ...) 470 __printflike(2,3); 471extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 472 __printflike(2, 0); 473extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 474 475/* allocate and free memory */ 476extern void *ath_hal_malloc(size_t); 477extern void ath_hal_free(void *); 478 479/* common debugging interfaces */ 480#ifdef AH_DEBUG 481#include "ah_debug.h" 482extern int ath_hal_debug; 483extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 484 __printflike(3,4); 485#else 486#define HALDEBUG(_ah, __m, _fmt, ...) 487#endif /* AH_DEBUG */ 488 489/* 490 * Register logging definitions shared with ardecode. 491 */ 492#include "ah_decode.h" 493 494/* 495 * Common assertion interface. Note: it is a bad idea to generate 496 * an assertion failure for any recoverable event. Instead catch 497 * the violation and, if possible, fix it up or recover from it; either 498 * with an error return value or a diagnostic messages. System software 499 * does not panic unless the situation is hopeless. 500 */ 501#ifdef AH_ASSERT 502extern void ath_hal_assert_failed(const char* filename, 503 int lineno, const char* msg); 504 505#define HALASSERT(_x) do { \ 506 if (!(_x)) { \ 507 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 508 } \ 509} while (0) 510#else 511#define HALASSERT(_x) 512#endif /* AH_ASSERT */ 513 514/* 515 * Regulatory domain support. 516 */ 517 518/* 519 * Return the max allowed antenna gain and apply any regulatory 520 * domain specific changes. 521 */ 522u_int ath_hal_getantennareduction(struct ath_hal *ah, 523 const struct ieee80211_channel *chan, u_int twiceGain); 524 525/* 526 * Return the test group for the specific channel based on 527 * the current regulatory setup. 528 */ 529u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 530 531/* 532 * Map a public channel definition to the corresponding 533 * internal data structure. This implicitly specifies 534 * whether or not the specified channel is ok to use 535 * based on the current regulatory domain constraints. 536 */ 537#ifndef AH_DEBUG 538static OS_INLINE HAL_CHANNEL_INTERNAL * 539ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 540{ 541 HAL_CHANNEL_INTERNAL *cc; 542 543 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 544 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 545 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 546 return cc; 547} 548#else 549/* NB: non-inline version that checks state */ 550HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 551 const struct ieee80211_channel *); 552#endif /* AH_DEBUG */ 553 554/* 555 * Return the h/w frequency for a channel. This may be 556 * different from ic_freq if this is a GSM device that 557 * takes 2.4GHz frequencies and down-converts them. 558 */ 559static OS_INLINE uint16_t 560ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 561{ 562 return ath_hal_checkchannel(ah, c)->channel; 563} 564 565/* 566 * Convert between microseconds and core system clocks. 567 */ 568extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 569extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 570 571/* 572 * Generic get/set capability support. Each chip overrides 573 * this routine to support chip-specific capabilities. 574 */ 575extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 576 HAL_CAPABILITY_TYPE type, uint32_t capability, 577 uint32_t *result); 578extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 579 HAL_CAPABILITY_TYPE type, uint32_t capability, 580 uint32_t setting, HAL_STATUS *status); 581 582/* 583 * Diagnostic interface. This is an open-ended interface that 584 * is opaque to applications. Diagnostic programs use this to 585 * retrieve internal data structures, etc. There is no guarantee 586 * that calling conventions for calls other than HAL_DIAG_REVS 587 * are stable between HAL releases; a diagnostic application must 588 * use the HAL revision information to deal with ABI/API differences. 589 * 590 * NB: do not renumber these, certain codes are publicly used. 591 */ 592enum { 593 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 594 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 595 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 596 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 597 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 598 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 599 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 600 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 601 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 602 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 603 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 604 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 605 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 606 HAL_DIAG_REGS = 13, /* Registers */ 607 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 608 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 609 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 610 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 611 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 612 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 613 HAL_DIAG_REGREAD = 24, /* Reg reads */ 614 HAL_DIAG_REGWRITE = 25, /* Reg writes */ 615 HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 616 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 617 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 618 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 619 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 620 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 621 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 622}; 623 624enum { 625 HAL_BB_HANG_DFS = 0x0001, 626 HAL_BB_HANG_RIFS = 0x0002, 627 HAL_BB_HANG_RX_CLEAR = 0x0004, 628 HAL_BB_HANG_UNKNOWN = 0x0080, 629 630 HAL_MAC_HANG_SIG1 = 0x0100, 631 HAL_MAC_HANG_SIG2 = 0x0200, 632 HAL_MAC_HANG_UNKNOWN = 0x8000, 633 634 HAL_BB_HANGS = HAL_BB_HANG_DFS 635 | HAL_BB_HANG_RIFS 636 | HAL_BB_HANG_RX_CLEAR 637 | HAL_BB_HANG_UNKNOWN, 638 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 639 | HAL_MAC_HANG_SIG2 640 | HAL_MAC_HANG_UNKNOWN, 641}; 642 643/* 644 * Device revision information. 645 */ 646typedef struct { 647 uint16_t ah_devid; /* PCI device ID */ 648 uint16_t ah_subvendorid; /* PCI subvendor ID */ 649 uint32_t ah_macVersion; /* MAC version id */ 650 uint16_t ah_macRev; /* MAC revision */ 651 uint16_t ah_phyRev; /* PHY revision */ 652 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 653 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 654} HAL_REVS; 655 656/* 657 * Argument payload for HAL_DIAG_SETKEY. 658 */ 659typedef struct { 660 HAL_KEYVAL dk_keyval; 661 uint16_t dk_keyix; /* key index */ 662 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 663 int dk_xor; /* XOR key data */ 664} HAL_DIAG_KEYVAL; 665 666/* 667 * Argument payload for HAL_DIAG_EEWRITE. 668 */ 669typedef struct { 670 uint16_t ee_off; /* eeprom offset */ 671 uint16_t ee_data; /* write data */ 672} HAL_DIAG_EEVAL; 673 674 675typedef struct { 676 u_int offset; /* reg offset */ 677 uint32_t val; /* reg value */ 678} HAL_DIAG_REGVAL; 679 680/* 681 * 11n compatibility tweaks. 682 */ 683#define HAL_DIAG_11N_SERVICES 0x00000003 684#define HAL_DIAG_11N_SERVICES_S 0 685#define HAL_DIAG_11N_TXSTOMP 0x0000000c 686#define HAL_DIAG_11N_TXSTOMP_S 2 687 688typedef struct { 689 int maxNoiseImmunityLevel; /* [0..4] */ 690 int totalSizeDesired[5]; 691 int coarseHigh[5]; 692 int coarseLow[5]; 693 int firpwr[5]; 694 695 int maxSpurImmunityLevel; /* [0..7] */ 696 int cycPwrThr1[8]; 697 698 int maxFirstepLevel; /* [0..2] */ 699 int firstep[3]; 700 701 uint32_t ofdmTrigHigh; 702 uint32_t ofdmTrigLow; 703 int32_t cckTrigHigh; 704 int32_t cckTrigLow; 705 int32_t rssiThrLow; 706 int32_t rssiThrHigh; 707 708 int period; /* update listen period */ 709} HAL_ANI_PARAMS; 710 711extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 712 const void *args, uint32_t argsize, 713 void **result, uint32_t *resultsize); 714 715/* 716 * Setup a h/w rate table for use. 717 */ 718extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 719 720/* 721 * Common routine for implementing getChanNoise api. 722 */ 723int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 724 725/* 726 * Initialization support. 727 */ 728typedef struct { 729 const uint32_t *data; 730 int rows, cols; 731} HAL_INI_ARRAY; 732 733#define HAL_INI_INIT(_ia, _data, _cols) do { \ 734 (_ia)->data = (const uint32_t *)(_data); \ 735 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 736 (_ia)->cols = (_cols); \ 737} while (0) 738#define HAL_INI_VAL(_ia, _r, _c) \ 739 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 740 741/* 742 * OS_DELAY() does a PIO READ on the PCI bus which allows 743 * other cards' DMA reads to complete in the middle of our reset. 744 */ 745#define DMA_YIELD(x) do { \ 746 if ((++(x) % 64) == 0) \ 747 OS_DELAY(1); \ 748} while (0) 749 750#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 751 int r; \ 752 for (r = 0; r < N(regArray); r++) { \ 753 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 754 DMA_YIELD(regWr); \ 755 } \ 756} while (0) 757 758#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 759 int r; \ 760 for (r = 0; r < N(regArray); r++) { \ 761 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 762 DMA_YIELD(regWr); \ 763 } \ 764} while (0) 765 766extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 767 int col, int regWr); 768extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 769 int col); 770extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 771 const uint32_t data[], int regWr); 772 773#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 774#endif /* _ATH_AH_INTERAL_H_ */ 775