ah_internal.h revision 187831
1156952Sume/* 2156952Sume * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3156952Sume * Copyright (c) 2002-2008 Atheros Communications, Inc. 4156952Sume * 5156952Sume * Permission to use, copy, modify, and/or distribute this software for any 6156952Sume * purpose with or without fee is hereby granted, provided that the above 7156952Sume * copyright notice and this permission notice appear in all copies. 8156952Sume * 9156952Sume * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10156952Sume * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11156952Sume * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12156952Sume * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13156952Sume * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14156952Sume * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15156952Sume * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16156952Sume * 17156952Sume * $FreeBSD: head/sys/dev/ath/ath_hal/ah_internal.h 187831 2009-01-28 18:00:22Z sam $ 18156952Sume */ 19156952Sume#ifndef _ATH_AH_INTERAL_H_ 20156952Sume#define _ATH_AH_INTERAL_H_ 21156952Sume/* 22156952Sume * Atheros Device Hardware Access Layer (HAL). 23156952Sume * 24156952Sume * Internal definitions. 25156952Sume */ 26156952Sume#define AH_NULL 0 27156952Sume#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28156952Sume#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29156952Sume 30156952Sume#include <net80211/_ieee80211.h> 31156952Sume 32156952Sume#ifndef NBBY 33156952Sume#define NBBY 8 /* number of bits/byte */ 34156952Sume#endif 35156952Sume 36156952Sume#ifndef roundup 37156952Sume#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 38156952Sume#endif 39156952Sume#ifndef howmany 40156952Sume#define howmany(x, y) (((x)+((y)-1))/(y)) 41156952Sume#endif 42156952Sume 43156952Sume#ifndef offsetof 44156952Sume#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 45156952Sume#endif 46156952Sume 47156952Sumetypedef struct { 48156952Sume uint16_t start; /* first register */ 49156952Sume uint16_t end; /* ending register or zero */ 50156952Sume} HAL_REGRANGE; 51156952Sume 52156952Sume/* 53156952Sume * Transmit power scale factor. 54156952Sume * 55156952Sume * NB: This is not public because we want to discourage the use of 56156952Sume * scaling; folks should use the tx power limit interface. 57156952Sume */ 58156952Sumetypedef enum { 59156952Sume HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 60156952Sume HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 61156952Sume HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 62156952Sume HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 63156952Sume HAL_TP_SCALE_MIN = 4, /* min, but still on */ 64156952Sume} HAL_TP_SCALE; 65156952Sume 66156952Sumetypedef enum { 67156952Sume HAL_CAP_RADAR = 0, /* Radar capability */ 68156952Sume HAL_CAP_AR = 1, /* AR capability */ 69174226Sume} HAL_PHYDIAG_CAPS; 70156952Sume 71156956Sume/* 72156956Sume * Each chip or class of chips registers to offer support. 73156952Sume */ 74156952Sumestruct ath_hal_chip { 75156952Sume const char *name; 76160965Sume const char *(*probe)(uint16_t vendorid, uint16_t devid); 77160965Sume struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 78156952Sume HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 79156952Sume}; 80156952Sume#ifndef AH_CHIP 81156952Sume#define AH_CHIP(_name, _probe, _attach) \ 82156952Sumestatic struct ath_hal_chip name##_chip = { \ 83156952Sume .name = #_name, \ 84156952Sume .probe = _probe, \ 85156952Sume .attach = _attach \ 86156952Sume}; \ 87156952SumeOS_DATA_SET(ah_chips, name##_chip) 88156952Sume#endif 89156952Sume 90156952Sume/* 91156952Sume * Each RF backend registers to offer support; this is mostly 92156952Sume * used by multi-chip 5212 solutions. Single-chip solutions 93156952Sume * have a fixed idea about which RF to use. 94160965Sume */ 95160965Sumestruct ath_hal_rf { 96156952Sume const char *name; 97156952Sume HAL_BOOL (*probe)(struct ath_hal *ah); 98156952Sume HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 99156952Sume}; 100156952Sume#ifndef AH_RF 101156952Sume#define AH_RF(_name, _probe, _attach) \ 102156952Sumestatic struct ath_hal_rf _name##_rf = { \ 103170244Sume .name = __STRING(_name), \ 104156952Sume .probe = _probe, \ 105156952Sume .attach = _attach \ 106156952Sume}; \ 107156952SumeOS_DATA_SET(ah_rfs, _name##_rf) 108156952Sume#endif 109156952Sume 110156952Sumestruct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 111156956Sume 112156952Sume/* 113156952Sume * Maximum number of internal channels. Entries are per unique 114156952Sume * frequency so this might be need to be increased to handle all 115156952Sume * usage cases; typically no more than 32 are really needed but 116156956Sume * dynamically allocating the data structures is a bit painful 117156952Sume * right now. 118156952Sume */ 119170244Sume#ifndef AH_MAXCHAN 120156952Sume#define AH_MAXCHAN 96 121156952Sume#endif 122156952Sume 123156952Sume/* 124156952Sume * Internal per-channel state. These are found 125156952Sume * using ic_devdata in the ieee80211_channel. 126156952Sume */ 127170244Sumetypedef struct { 128156952Sume uint16_t channel; /* h/w frequency, NB: may be mapped */ 129156952Sume uint8_t privFlags; 130156952Sume#define CHANNEL_IQVALID 0x01 /* IQ calibration valid */ 131156952Sume#define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */ 132156952Sume#define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */ 133156952Sume uint8_t calValid; /* bitmask of cal types */ 134156952Sume int8_t iCoff; 135156952Sume int8_t qCoff; 136156952Sume int16_t rawNoiseFloor; 137156952Sume int16_t noiseFloorAdjust; 138156952Sume uint16_t mainSpur; /* cached spur value for this channel */ 139156952Sume} HAL_CHANNEL_INTERNAL; 140156952Sume 141156952Sume/* channel requires noise floor check */ 142156952Sume#define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0 143156952Sume 144156952Sume/* all full-width channels */ 145156952Sume#define IEEE80211_CHAN_ALLFULL \ 146156952Sume (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 147156952Sume#define IEEE80211_CHAN_ALLTURBOFULL \ 148156952Sume (IEEE80211_CHAN_ALLTURBO - \ 149156952Sume (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER)) 150156952Sume 151156952Sumetypedef struct { 152156952Sume uint32_t halChanSpreadSupport : 1, 153156952Sume halSleepAfterBeaconBroken : 1, 154156952Sume halCompressSupport : 1, 155170244Sume halBurstSupport : 1, 156156952Sume halFastFramesSupport : 1, 157156952Sume halChapTuningSupport : 1, 158156956Sume halTurboGSupport : 1, 159156956Sume halTurboPrimeSupport : 1, 160156956Sume halMicAesCcmSupport : 1, 161156952Sume halMicCkipSupport : 1, 162170244Sume halMicTkipSupport : 1, 163156952Sume halTkipMicTxRxKeySupport : 1, 164156952Sume halCipherAesCcmSupport : 1, 165156952Sume halCipherCkipSupport : 1, 166156952Sume halCipherTkipSupport : 1, 167156952Sume halPSPollBroken : 1, 168156952Sume halVEOLSupport : 1, 169156952Sume halBssIdMaskSupport : 1, 170156952Sume halMcastKeySrchSupport : 1, 171174226Sume halTsfAddSupport : 1, 172156952Sume halChanHalfRate : 1, 173174226Sume halChanQuarterRate : 1, 174156952Sume halHTSupport : 1, 175156952Sume halRfSilentSupport : 1, 176156952Sume halHwPhyCounterSupport : 1, 177156952Sume halWowSupport : 1, 178156952Sume halWowMatchPatternExact : 1, 179156952Sume halAutoSleepSupport : 1, 180156952Sume halFastCCSupport : 1, 181156952Sume halBtCoexSupport : 1; 182156952Sume uint32_t halRxStbcSupport : 1, 183156952Sume halTxStbcSupport : 1, 184156952Sume halGTTSupport : 1, 185156952Sume halCSTSupport : 1, 186156952Sume halRifsRxSupport : 1, 187156952Sume halRifsTxSupport : 1, 188156952Sume halExtChanDfsSupport : 1, 189156952Sume halForcePpmSupport : 1, 190156952Sume halEnhancedPmSupport : 1, 191156952Sume halMbssidAggrSupport : 1; 192156952Sume uint32_t halWirelessModes; 193156952Sume uint16_t halTotalQueues; 194156952Sume uint16_t halKeyCacheSize; 195156952Sume uint16_t halLow5GhzChan, halHigh5GhzChan; 196156952Sume uint16_t halLow2GhzChan, halHigh2GhzChan; 197156952Sume int halTstampPrecision; 198156952Sume int halRtsAggrLimit; 199156952Sume uint8_t halTxChainMask; 200156952Sume uint8_t halRxChainMask; 201156952Sume uint8_t halNumGpioPins; 202156952Sume uint8_t halNumAntCfg2GHz; 203156952Sume uint8_t halNumAntCfg5GHz; 204156952Sume} HAL_CAPABILITIES; 205156952Sume 206156952Sumestruct regDomain; 207156952Sume 208156952Sume/* 209156952Sume * The ``private area'' follows immediately after the ``public area'' 210156952Sume * in the data structure returned by ath_hal_attach. Private data are 211156952Sume * used by device-independent code such as the regulatory domain support. 212156952Sume * In general, code within the HAL should never depend on data in the 213156952Sume * public area. Instead any public data needed internally should be 214156952Sume * shadowed here. 215156952Sume * 216156952Sume * When declaring a device-specific ath_hal data structure this structure 217156952Sume * is assumed to at the front; e.g. 218156952Sume * 219156952Sume * struct ath_hal_5212 { 220156952Sume * struct ath_hal_private ah_priv; 221156952Sume * ... 222156952Sume * }; 223174226Sume * 224174226Sume * It might be better to manage the method pointers in this structure 225174226Sume * using an indirect pointer to a read-only data structure but this would 226174226Sume * disallow class-style method overriding. 227174226Sume */ 228174226Sumestruct ath_hal_private { 229174226Sume struct ath_hal h; /* public area */ 230174226Sume 231174226Sume /* NB: all methods go first to simplify initialization */ 232174226Sume HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 233174226Sume uint16_t channelFlags, 234174226Sume uint16_t *lowChannel, uint16_t *highChannel); 235174226Sume u_int (*ah_getWirelessModes)(struct ath_hal*); 236174226Sume HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 237174226Sume uint16_t *data); 238174226Sume HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 239156952Sume uint16_t data); 240156952Sume HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 241156952Sume HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 242156952Sume uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 243156952Sume HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 244156952Sume uint32_t gpio, uint32_t val); 245156952Sume void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 246156952Sume HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 247156952Sume struct ieee80211_channel *); 248156952Sume int16_t (*ah_getNfAdjust)(struct ath_hal *, 249156952Sume const HAL_CHANNEL_INTERNAL*); 250156952Sume void (*ah_getNoiseFloor)(struct ath_hal *, 251156952Sume int16_t nfarray[]); 252156952Sume 253156952Sume void *ah_eeprom; /* opaque EEPROM state */ 254156952Sume uint16_t ah_eeversion; /* EEPROM version */ 255156952Sume void (*ah_eepromDetach)(struct ath_hal *); 256156952Sume HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 257156952Sume HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 258165258Sume uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 259174226Sume HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 260174226Sume const void *args, uint32_t argsize, 261174226Sume void **result, uint32_t *resultsize); 262156952Sume 263156952Sume /* 264156952Sume * Device revision information. 265156952Sume */ 266156952Sume uint16_t ah_devid; /* PCI device ID */ 267156956Sume uint16_t ah_subvendorid; /* PCI subvendor ID */ 268156952Sume uint32_t ah_macVersion; /* MAC version id */ 269156952Sume uint16_t ah_macRev; /* MAC revision */ 270156952Sume uint16_t ah_phyRev; /* PHY revision */ 271156952Sume uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 272156952Sume uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 273156952Sume 274156952Sume HAL_OPMODE ah_opmode; /* operating mode from reset */ 275156952Sume const struct ieee80211_channel *ah_curchan;/* operating channel */ 276156952Sume HAL_CAPABILITIES ah_caps; /* device capabilities */ 277156952Sume uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 278156952Sume int16_t ah_powerLimit; /* tx power cap */ 279156952Sume uint16_t ah_maxPowerLevel; /* calculated max tx power */ 280156952Sume u_int ah_tpScale; /* tx power scale factor */ 281156952Sume uint32_t ah_11nCompat; /* 11n compat controls */ 282156952Sume 283170244Sume /* 284156952Sume * State for regulatory domain handling. 285156952Sume */ 286156952Sume HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */ 287156952Sume HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */ 288156952Sume u_int ah_nchan; /* valid items in ah_channels */ 289156952Sume const struct regDomain *ah_rd2GHz; /* reg state for 2G band */ 290156952Sume const struct regDomain *ah_rd5GHz; /* reg state for 5G band */ 291156952Sume 292156952Sume uint8_t ah_coverageClass; /* coverage class */ 293156952Sume /* 294156952Sume * RF Silent handling; setup according to the EEPROM. 295156952Sume */ 296156952Sume uint16_t ah_rfsilent; /* GPIO pin + polarity */ 297156952Sume HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 298156952Sume /* 299156952Sume * Diagnostic support for discriminating HIUERR reports. 300156952Sume */ 301156952Sume uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 302156952Sume int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 303156952Sume}; 304156952Sume 305156952Sume#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 306156952Sume 307254700Sjilles#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 308156952Sume AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 309156952Sume#define ath_hal_getWirelessModes(_ah) \ 310156952Sume AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 311156952Sume#define ath_hal_eepromRead(_ah, _off, _data) \ 312156952Sume AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 313156952Sume#define ath_hal_eepromWrite(_ah, _off, _data) \ 314156952Sume AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 315170244Sume#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 316156952Sume AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 317156952Sume#define ath_hal_gpioCfgInput(_ah, _gpio) \ 318156952Sume AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 319156952Sume#define ath_hal_gpioGet(_ah, _gpio) \ 320156952Sume AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 321156952Sume#define ath_hal_gpioSet(_ah, _gpio, _val) \ 322156952Sume AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 323156952Sume#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 324156952Sume AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 325156952Sume#define ath_hal_getpowerlimits(_ah, _chan) \ 326156952Sume AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan) 327156952Sume#define ath_hal_getNfAdjust(_ah, _c) \ 328156952Sume AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 329156952Sume#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 330156952Sume AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 331170244Sume 332156952Sume#define ath_hal_eepromDetach(_ah) \ 333156952Sume AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 334156952Sume#define ath_hal_eepromGet(_ah, _param, _val) \ 335156952Sume AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 336156952Sume#define ath_hal_eepromSet(_ah, _param, _val) \ 337156952Sume AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 338156952Sume#define ath_hal_eepromGetFlag(_ah, _param) \ 339156952Sume (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 340156952Sume#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 341156952Sume AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 342156952Sume#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 343156952Sume AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 344156952Sume 345156952Sume#ifndef _NET_IF_IEEE80211_H_ 346156952Sume/* 347156952Sume * Stuff that would naturally come from _ieee80211.h 348156952Sume */ 349156952Sume#define IEEE80211_ADDR_LEN 6 350156952Sume 351156952Sume#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 352156952Sume#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 353156952Sume#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 354156952Sume 355156952Sume#define IEEE80211_CRC_LEN 4 356156952Sume 357156952Sume#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 358156952Sume (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 359156952Sume#endif /* _NET_IF_IEEE80211_H_ */ 360156952Sume 361156952Sume#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 362156952Sume 363156952Sume#define INIT_AIFS 2 364156952Sume#define INIT_CWMIN 15 365156952Sume#define INIT_CWMIN_11B 31 366156952Sume#define INIT_CWMAX 1023 367174226Sume#define INIT_SH_RETRY 10 368156952Sume#define INIT_LG_RETRY 10 369156952Sume#define INIT_SSH_RETRY 32 370156952Sume#define INIT_SLG_RETRY 32 371156952Sume 372156952Sumetypedef struct { 373156952Sume uint32_t tqi_ver; /* HAL TXQ verson */ 374156952Sume HAL_TX_QUEUE tqi_type; /* hw queue type*/ 375156952Sume HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 376156952Sume HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 377156952Sume uint32_t tqi_priority; 378156952Sume uint32_t tqi_aifs; /* aifs */ 379156952Sume uint32_t tqi_cwmin; /* cwMin */ 380156952Sume uint32_t tqi_cwmax; /* cwMax */ 381156952Sume uint16_t tqi_shretry; /* frame short retry limit */ 382156952Sume uint16_t tqi_lgretry; /* frame long retry limit */ 383156952Sume uint32_t tqi_cbrPeriod; 384156952Sume uint32_t tqi_cbrOverflowLimit; 385156952Sume uint32_t tqi_burstTime; 386156952Sume uint32_t tqi_readyTime; 387156952Sume uint32_t tqi_physCompBuf; 388156952Sume uint32_t tqi_intFlags; /* flags for internal use */ 389156952Sume} HAL_TX_QUEUE_INFO; 390156952Sume 391156952Sumeextern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 392156952Sume HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 393156952Sumeextern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 394156952Sume HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 395156952Sume 396156952Sumetypedef enum { 397156952Sume HAL_ANI_PRESENT, /* is ANI support present */ 398156952Sume HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 399156952Sume HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 400156952Sume HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 401156952Sume HAL_ANI_FIRSTEP_LEVEL, /* set level */ 402156952Sume HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 403156952Sume HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 404156956Sume HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 405156956Sume} HAL_ANI_CMD; 406156956Sume 407156956Sume#define HAL_SPUR_VAL_MASK 0x3FFF 408156952Sume#define HAL_SPUR_CHAN_WIDTH 87 409156952Sume#define HAL_BIN_WIDTH_BASE_100HZ 3125 410156952Sume#define HAL_BIN_WIDTH_TURBO_100HZ 6250 411156952Sume#define HAL_MAX_BINS_ALLOWED 28 412156952Sume 413156952Sume#define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900) 414156952Sume#define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) 415156952Sume 416156952Sume#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 417156952Sume 418156952Sume/* 419156952Sume * Deduce if the host cpu has big- or litt-endian byte order. 420156952Sume */ 421156952Sumestatic __inline__ int 422156952SumeisBigEndian(void) 423156952Sume{ 424156952Sume union { 425156952Sume int32_t i; 426156952Sume char c[4]; 427156952Sume } u; 428156952Sume u.i = 1; 429156952Sume return (u.c[0] == 0); 430156952Sume} 431156952Sume 432156952Sume/* unalligned little endian access */ 433156952Sume#define LE_READ_2(p) \ 434156952Sume ((uint16_t) \ 435156952Sume ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 436156952Sume#define LE_READ_4(p) \ 437156952Sume ((uint32_t) \ 438156952Sume ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 439156952Sume (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 440156952Sume 441156952Sume/* 442156956Sume * Register manipulation macros that expect bit field defines 443156956Sume * to follow the convention that an _S suffix is appended for 444156956Sume * a shift count, while the field mask has no suffix. 445156956Sume */ 446156956Sume#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 447156952Sume#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 448156952Sume#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 449156956Sume OS_REG_WRITE(_a, _r, \ 450156956Sume (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 451156956Sume#define OS_REG_SET_BIT(_a, _r, _f) \ 452156956Sume OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 453156956Sume#define OS_REG_CLR_BIT(_a, _r, _f) \ 454156956Sume OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 455156956Sume 456156956Sume/* system-configurable parameters */ 457156956Sumeextern int ath_hal_dma_beacon_response_time; /* in TU's */ 458156956Sumeextern int ath_hal_sw_beacon_response_time; /* in TU's */ 459156956Sumeextern int ath_hal_additional_swba_backoff; /* in TU's */ 460156956Sume 461156956Sume/* wait for the register contents to have the specified value */ 462156956Sumeextern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 463156956Sume uint32_t mask, uint32_t val); 464156956Sume 465156956Sume/* return the first n bits in val reversed */ 466156956Sumeextern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 467156956Sume 468156956Sume/* printf interfaces */ 469156956Sumeextern void ath_hal_printf(struct ath_hal *, const char*, ...) 470156956Sume __printflike(2,3); 471156956Sumeextern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 472156956Sume __printflike(2, 0); 473156956Sumeextern const char* ath_hal_ether_sprintf(const uint8_t *mac); 474156956Sume 475156956Sume/* allocate and free memory */ 476156956Sumeextern void *ath_hal_malloc(size_t); 477156956Sumeextern void ath_hal_free(void *); 478156956Sume 479156956Sume/* common debugging interfaces */ 480156956Sume#ifdef AH_DEBUG 481156956Sume#include "ah_debug.h" 482156956Sumeextern int ath_hal_debug; 483156956Sumeextern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 484156956Sume __printflike(3,4); 485156956Sume#else 486156956Sume#define HALDEBUG(_ah, __m, _fmt, ...) 487156956Sume#endif /* AH_DEBUG */ 488156956Sume 489156956Sume/* 490156956Sume * Register logging definitions shared with ardecode. 491156956Sume */ 492156956Sume#include "ah_decode.h" 493156956Sume 494156956Sume/* 495156952Sume * Common assertion interface. Note: it is a bad idea to generate 496156952Sume * an assertion failure for any recoverable event. Instead catch 497156952Sume * the violation and, if possible, fix it up or recover from it; either 498156952Sume * with an error return value or a diagnostic messages. System software 499156952Sume * does not panic unless the situation is hopeless. 500156952Sume */ 501156952Sume#ifdef AH_ASSERT 502156952Sumeextern void ath_hal_assert_failed(const char* filename, 503156952Sume int lineno, const char* msg); 504156952Sume 505156952Sume#define HALASSERT(_x) do { \ 506156952Sume if (!(_x)) { \ 507156952Sume ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 508156952Sume } \ 509156952Sume} while (0) 510156952Sume#else 511156952Sume#define HALASSERT(_x) 512156952Sume#endif /* AH_ASSERT */ 513156952Sume 514156952Sume/* 515156952Sume * Regulatory domain support. 516156952Sume */ 517156952Sume 518156952Sume/* 519156952Sume * Return the max allowed antenna gain and apply any regulatory 520156952Sume * domain specific changes. 521156952Sume */ 522156952Sumeu_int ath_hal_getantennareduction(struct ath_hal *ah, 523156952Sume const struct ieee80211_channel *chan, u_int twiceGain); 524156952Sume 525156952Sume/* 526156952Sume * Return the test group for the specific channel based on 527156952Sume * the current regulatory setup. 528156952Sume */ 529156952Sumeu_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *); 530156952Sume 531156952Sume/* 532156952Sume * Map a public channel definition to the corresponding 533156952Sume * internal data structure. This implicitly specifies 534156952Sume * whether or not the specified channel is ok to use 535156952Sume * based on the current regulatory domain constraints. 536156952Sume */ 537156952Sume#ifndef AH_DEBUG 538156952Sumestatic OS_INLINE HAL_CHANNEL_INTERNAL * 539156952Sumeath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 540170244Sume{ 541156952Sume HAL_CHANNEL_INTERNAL *cc; 542156952Sume 543156952Sume HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 544156952Sume cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 545156952Sume HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 546156952Sume return cc; 547156952Sume} 548156952Sume#else 549156952Sume/* NB: non-inline version that checks state */ 550156952SumeHAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 551156952Sume const struct ieee80211_channel *); 552156952Sume#endif /* AH_DEBUG */ 553156952Sume 554156952Sume/* 555156956Sume * Return the h/w frequency for a channel. This may be 556156956Sume * different from ic_freq if this is a GSM device that 557156956Sume * takes 2.4GHz frequencies and down-converts them. 558156952Sume */ 559156952Sumestatic OS_INLINE uint16_t 560174226Sumeath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 561156952Sume{ 562156952Sume return ath_hal_checkchannel(ah, c)->channel; 563156952Sume} 564156952Sume 565156952Sume/* 566156952Sume * Convert between microseconds and core system clocks. 567156952Sume */ 568156956Sumeextern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 569156952Sumeextern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 570156956Sume 571156952Sume/* 572156952Sume * Generic get/set capability support. Each chip overrides 573156952Sume * this routine to support chip-specific capabilities. 574156952Sume */ 575156952Sumeextern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 576156952Sume HAL_CAPABILITY_TYPE type, uint32_t capability, 577156952Sume uint32_t *result); 578156952Sumeextern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 579156952Sume HAL_CAPABILITY_TYPE type, uint32_t capability, 580156952Sume uint32_t setting, HAL_STATUS *status); 581156952Sume 582156952Sume/* 583156952Sume * Diagnostic interface. This is an open-ended interface that 584156952Sume * is opaque to applications. Diagnostic programs use this to 585156952Sume * retrieve internal data structures, etc. There is no guarantee 586156952Sume * that calling conventions for calls other than HAL_DIAG_REVS 587156952Sume * are stable between HAL releases; a diagnostic application must 588156952Sume * use the HAL revision information to deal with ABI/API differences. 589156952Sume * 590156952Sume * NB: do not renumber these, certain codes are publicly used. 591156952Sume */ 592156952Sumeenum { 593156952Sume HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 594156952Sume HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 595156952Sume HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 596156952Sume HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 597156952Sume HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 598156952Sume HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 599156952Sume HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 600156952Sume HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 601156952Sume HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 602156952Sume HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 603156952Sume HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 604156952Sume HAL_DIAG_PCDAC = 11, /* PCDAC table */ 605156952Sume HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 606156952Sume HAL_DIAG_REGS = 13, /* Registers */ 607156952Sume HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 608156952Sume HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 609156952Sume HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 610156952Sume HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 611156952Sume HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 612156952Sume /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 613156952Sume HAL_DIAG_REGREAD = 24, /* Reg reads */ 614156952Sume HAL_DIAG_REGWRITE = 25, /* Reg writes */ 615156952Sume HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 616156952Sume HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 617156952Sume HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 618156952Sume HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 619156952Sume HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 620156952Sume HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 621156952Sume HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 622156952Sume}; 623156952Sume 624156952Sumeenum { 625156952Sume HAL_BB_HANG_DFS = 0x0001, 626156952Sume HAL_BB_HANG_RIFS = 0x0002, 627156952Sume HAL_BB_HANG_RX_CLEAR = 0x0004, 628156952Sume HAL_BB_HANG_UNKNOWN = 0x0080, 629156952Sume 630156952Sume HAL_MAC_HANG_SIG1 = 0x0100, 631156952Sume HAL_MAC_HANG_SIG2 = 0x0200, 632156952Sume HAL_MAC_HANG_UNKNOWN = 0x8000, 633156952Sume 634156952Sume HAL_BB_HANGS = HAL_BB_HANG_DFS 635156952Sume | HAL_BB_HANG_RIFS 636156952Sume | HAL_BB_HANG_RX_CLEAR 637156952Sume | HAL_BB_HANG_UNKNOWN, 638156952Sume HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 639156952Sume | HAL_MAC_HANG_SIG2 640156952Sume | HAL_MAC_HANG_UNKNOWN, 641156952Sume}; 642156952Sume 643156952Sume/* 644156956Sume * Device revision information. 645156956Sume */ 646156956Sumetypedef struct { 647156956Sume uint16_t ah_devid; /* PCI device ID */ 648156952Sume uint16_t ah_subvendorid; /* PCI subvendor ID */ 649156952Sume uint32_t ah_macVersion; /* MAC version id */ 650156952Sume uint16_t ah_macRev; /* MAC revision */ 651156952Sume uint16_t ah_phyRev; /* PHY revision */ 652156952Sume uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 653156952Sume uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 654156952Sume} HAL_REVS; 655156952Sume 656156952Sume/* 657156952Sume * Argument payload for HAL_DIAG_SETKEY. 658156952Sume */ 659156956Sumetypedef struct { 660156952Sume HAL_KEYVAL dk_keyval; 661156952Sume uint16_t dk_keyix; /* key index */ 662156952Sume uint8_t dk_mac[IEEE80211_ADDR_LEN]; 663156952Sume int dk_xor; /* XOR key data */ 664156952Sume} HAL_DIAG_KEYVAL; 665156952Sume 666156952Sume/* 667156952Sume * Argument payload for HAL_DIAG_EEWRITE. 668156952Sume */ 669156952Sumetypedef struct { 670156952Sume uint16_t ee_off; /* eeprom offset */ 671156952Sume uint16_t ee_data; /* write data */ 672156952Sume} HAL_DIAG_EEVAL; 673156952Sume 674156952Sume 675156952Sumetypedef struct { 676156952Sume u_int offset; /* reg offset */ 677156952Sume uint32_t val; /* reg value */ 678156952Sume} HAL_DIAG_REGVAL; 679156952Sume 680156952Sume/* 681156952Sume * 11n compatibility tweaks. 682156952Sume */ 683156952Sume#define HAL_DIAG_11N_SERVICES 0x00000003 684156952Sume#define HAL_DIAG_11N_SERVICES_S 0 685156952Sume#define HAL_DIAG_11N_TXSTOMP 0x0000000c 686156952Sume#define HAL_DIAG_11N_TXSTOMP_S 2 687156952Sume 688156952Sumetypedef struct { 689156956Sume int maxNoiseImmunityLevel; /* [0..4] */ 690156952Sume int totalSizeDesired[5]; 691156952Sume int coarseHigh[5]; 692156952Sume int coarseLow[5]; 693156956Sume int firpwr[5]; 694156952Sume 695156956Sume int maxSpurImmunityLevel; /* [0..7] */ 696156952Sume int cycPwrThr1[8]; 697156952Sume 698156952Sume int maxFirstepLevel; /* [0..2] */ 699156952Sume int firstep[3]; 700156952Sume 701156952Sume uint32_t ofdmTrigHigh; 702156952Sume uint32_t ofdmTrigLow; 703156952Sume int32_t cckTrigHigh; 704156952Sume int32_t cckTrigLow; 705170244Sume int32_t rssiThrLow; 706156952Sume int32_t rssiThrHigh; 707156952Sume 708156956Sume int period; /* update listen period */ 709156952Sume} HAL_ANI_PARAMS; 710156952Sume 711156952Sumeextern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 712156952Sume const void *args, uint32_t argsize, 713156952Sume void **result, uint32_t *resultsize); 714156952Sume 715156952Sume/* 716156952Sume * Setup a h/w rate table for use. 717156952Sume */ 718156952Sumeextern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 719156952Sume 720156952Sume/* 721156952Sume * Common routine for implementing getChanNoise api. 722156952Sume */ 723156952Sumeint16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *); 724156952Sume 725156952Sume/* 726170244Sume * Initialization support. 727156952Sume */ 728156952Sumetypedef struct { 729156952Sume const uint32_t *data; 730156952Sume int rows, cols; 731156952Sume} HAL_INI_ARRAY; 732156952Sume 733156952Sume#define HAL_INI_INIT(_ia, _data, _cols) do { \ 734156952Sume (_ia)->data = (const uint32_t *)(_data); \ 735156952Sume (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 736156952Sume (_ia)->cols = (_cols); \ 737156952Sume} while (0) 738160965Sume#define HAL_INI_VAL(_ia, _r, _c) \ 739156952Sume ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 740156952Sume 741156952Sume/* 742156952Sume * OS_DELAY() does a PIO READ on the PCI bus which allows 743156952Sume * other cards' DMA reads to complete in the middle of our reset. 744160965Sume */ 745156952Sume#define DMA_YIELD(x) do { \ 746156952Sume if ((++(x) % 64) == 0) \ 747156952Sume OS_DELAY(1); \ 748156952Sume} while (0) 749156952Sume 750156952Sume#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 751156952Sume int r; \ 752156952Sume for (r = 0; r < N(regArray); r++) { \ 753156952Sume OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 754156952Sume DMA_YIELD(regWr); \ 755156952Sume } \ 756156952Sume} while (0) 757156952Sume 758156952Sume#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 759156956Sume int r; \ 760156952Sume for (r = 0; r < N(regArray); r++) { \ 761156952Sume OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 762156952Sume DMA_YIELD(regWr); \ 763156952Sume } \ 764156952Sume} while (0) 765156952Sume 766156952Sumeextern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 767156952Sume int col, int regWr); 768156952Sumeextern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 769156952Sume int col); 770156952Sumeextern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 771156952Sume const uint32_t data[], int regWr); 772156952Sume 773156956Sume#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 774156952Sume#endif /* _ATH_AH_INTERAL_H_ */ 775156952Sume