ah_internal.h revision 185521
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ah_internal.h,v 1.21 2008/11/27 22:29:27 sam Exp $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#ifndef NBBY 31#define NBBY 8 /* number of bits/byte */ 32#endif 33 34#ifndef roundup 35#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 36#endif 37#ifndef howmany 38#define howmany(x, y) (((x)+((y)-1))/(y)) 39#endif 40 41#ifndef offsetof 42#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 43#endif 44 45/* 46 * Remove const in a way that keeps the compiler happy. 47 * This works for gcc but may require other magic for 48 * other compilers (not sure where this should reside). 49 * Note that uintptr_t is C99. 50 */ 51#ifndef __DECONST 52#ifndef _UINTPTR_T 53#if AH_WORDSIZE == 64 54typedef unsigned long int uintptr_t; 55#else 56typedef unsigned int uintptr_t; 57#endif 58#endif 59#define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var)) 60#endif 61 62typedef struct { 63 uint16_t start; /* first register */ 64 uint16_t end; /* ending register or zero */ 65} HAL_REGRANGE; 66 67/* 68 * Transmit power scale factor. 69 * 70 * NB: This is not public because we want to discourage the use of 71 * scaling; folks should use the tx power limit interface. 72 */ 73typedef enum { 74 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 75 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 76 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 77 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 78 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 79} HAL_TP_SCALE; 80 81typedef enum { 82 HAL_CAP_RADAR = 0, /* Radar capability */ 83 HAL_CAP_AR = 1, /* AR capability */ 84} HAL_PHYDIAG_CAPS; 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *name; 91 const char *(*probe)(uint16_t vendorid, uint16_t devid); 92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 93 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 94}; 95#ifndef AH_CHIP 96#define AH_CHIP(_name, _probe, _attach) \ 97static struct ath_hal_chip name##_chip = { \ 98 .name = #_name, \ 99 .probe = _probe, \ 100 .attach = _attach \ 101}; \ 102OS_DATA_SET(ah_chips, name##_chip) 103#endif 104 105/* 106 * Each RF backend registers to offer support; this is mostly 107 * used by multi-chip 5212 solutions. Single-chip solutions 108 * have a fixed idea about which RF to use. 109 */ 110struct ath_hal_rf { 111 const char *name; 112 HAL_BOOL (*probe)(struct ath_hal *ah); 113 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 114}; 115#ifndef AH_RF 116#define AH_RF(_name, _probe, _attach) \ 117static struct ath_hal_rf name##_rf = { \ 118 .name = #_name, \ 119 .probe = _probe, \ 120 .attach = _attach \ 121}; \ 122OS_DATA_SET(ah_rfs, name##_rf) 123#endif 124 125struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 126 127/* 128 * Internal form of a HAL_CHANNEL. Note that the structure 129 * must be defined such that you can cast references to a 130 * HAL_CHANNEL so don't shuffle the first two members. 131 */ 132typedef struct { 133 uint32_t channelFlags; 134 uint16_t channel; /* NB: must be first for casting */ 135 uint8_t privFlags; 136 int8_t maxRegTxPower; 137 int8_t maxTxPower; 138 int8_t minTxPower; /* as above... */ 139 140 HAL_BOOL bssSendHere; 141 uint8_t gainI; 142 HAL_BOOL iqCalValid; 143 uint8_t calValid; /* bitmask of cal types */ 144 int8_t iCoff; 145 int8_t qCoff; 146 int16_t rawNoiseFloor; 147 int16_t noiseFloorAdjust; 148 int8_t antennaMax; 149 uint32_t regDmnFlags; /* Flags for channel use in reg */ 150 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ 151 uint16_t mainSpur; /* cached spur value for this cahnnel */ 152} HAL_CHANNEL_INTERNAL; 153 154typedef struct { 155 uint32_t halChanSpreadSupport : 1, 156 halSleepAfterBeaconBroken : 1, 157 halCompressSupport : 1, 158 halBurstSupport : 1, 159 halFastFramesSupport : 1, 160 halChapTuningSupport : 1, 161 halTurboGSupport : 1, 162 halTurboPrimeSupport : 1, 163 halMicAesCcmSupport : 1, 164 halMicCkipSupport : 1, 165 halMicTkipSupport : 1, 166 halTkipMicTxRxKeySupport : 1, 167 halCipherAesCcmSupport : 1, 168 halCipherCkipSupport : 1, 169 halCipherTkipSupport : 1, 170 halPSPollBroken : 1, 171 halVEOLSupport : 1, 172 halBssIdMaskSupport : 1, 173 halMcastKeySrchSupport : 1, 174 halTsfAddSupport : 1, 175 halChanHalfRate : 1, 176 halChanQuarterRate : 1, 177 halHTSupport : 1, 178 halRfSilentSupport : 1, 179 halHwPhyCounterSupport : 1, 180 halWowSupport : 1, 181 halWowMatchPatternExact : 1, 182 halAutoSleepSupport : 1, 183 halFastCCSupport : 1, 184 halBtCoexSupport : 1; 185 uint32_t halRxStbcSupport : 1, 186 halTxStbcSupport : 1, 187 halGTTSupport : 1, 188 halCSTSupport : 1, 189 halRifsRxSupport : 1, 190 halRifsTxSupport : 1, 191 halExtChanDfsSupport : 1, 192 halForcePpmSupport : 1, 193 halEnhancedPmSupport : 1, 194 halMbssidAggrSupport : 1; 195 uint32_t halWirelessModes; 196 uint16_t halTotalQueues; 197 uint16_t halKeyCacheSize; 198 uint16_t halLow5GhzChan, halHigh5GhzChan; 199 uint16_t halLow2GhzChan, halHigh2GhzChan; 200 int halTstampPrecision; 201 int halRtsAggrLimit; 202 uint8_t halTxChainMask; 203 uint8_t halRxChainMask; 204 uint8_t halNumGpioPins; 205 uint8_t halNumAntCfg2GHz; 206 uint8_t halNumAntCfg5GHz; 207} HAL_CAPABILITIES; 208 209/* 210 * The ``private area'' follows immediately after the ``public area'' 211 * in the data structure returned by ath_hal_attach. Private data are 212 * used by device-independent code such as the regulatory domain support. 213 * In general, code within the HAL should never depend on data in the 214 * public area. Instead any public data needed internally should be 215 * shadowed here. 216 * 217 * When declaring a device-specific ath_hal data structure this structure 218 * is assumed to at the front; e.g. 219 * 220 * struct ath_hal_5212 { 221 * struct ath_hal_private ah_priv; 222 * ... 223 * }; 224 * 225 * It might be better to manage the method pointers in this structure 226 * using an indirect pointer to a read-only data structure but this would 227 * disallow class-style method overriding. 228 */ 229struct ath_hal_private { 230 struct ath_hal h; /* public area */ 231 232 /* NB: all methods go first to simplify initialization */ 233 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 234 uint16_t channelFlags, 235 uint16_t *lowChannel, uint16_t *highChannel); 236 u_int (*ah_getWirelessModes)(struct ath_hal*); 237 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 238 uint16_t *data); 239 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 240 uint16_t data); 241 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 242 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 243 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 244 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 245 uint32_t gpio, uint32_t val); 246 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 247 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 248 HAL_CHANNEL *, uint32_t); 249 int16_t (*ah_getNfAdjust)(struct ath_hal *, 250 const HAL_CHANNEL_INTERNAL*); 251 void (*ah_getNoiseFloor)(struct ath_hal *, 252 int16_t nfarray[]); 253 254 void *ah_eeprom; /* opaque EEPROM state */ 255 uint16_t ah_eeversion; /* EEPROM version */ 256 void (*ah_eepromDetach)(struct ath_hal *); 257 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 258 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 259 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 260 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 261 const void *args, uint32_t argsize, 262 void **result, uint32_t *resultsize); 263 264 /* 265 * Device revision information. 266 */ 267 uint16_t ah_devid; /* PCI device ID */ 268 uint16_t ah_subvendorid; /* PCI subvendor ID */ 269 uint32_t ah_macVersion; /* MAC version id */ 270 uint16_t ah_macRev; /* MAC revision */ 271 uint16_t ah_phyRev; /* PHY revision */ 272 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 273 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 274 275 276 HAL_OPMODE ah_opmode; /* operating mode from reset */ 277 HAL_CAPABILITIES ah_caps; /* device capabilities */ 278 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 279 int16_t ah_powerLimit; /* tx power cap */ 280 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 281 u_int ah_tpScale; /* tx power scale factor */ 282 uint32_t ah_11nCompat; /* 11n compat controls */ 283 284 /* 285 * State for regulatory domain handling. 286 */ 287 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */ 288 HAL_CTRY_CODE ah_countryCode; /* current country code */ 289 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */ 290 u_int ah_nchan; /* valid channels in list */ 291 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ 292 293 uint8_t ah_coverageClass; /* coverage class */ 294 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */ 295 /* 296 * RF Silent handling; setup according to the EEPROM. 297 */ 298 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 299 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 300 /* 301 * Diagnostic support for discriminating HIUERR reports. 302 */ 303 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 304 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 305}; 306 307#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 308 309#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 310 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 311#define ath_hal_getWirelessModes(_ah) \ 312 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 313#define ath_hal_eepromRead(_ah, _off, _data) \ 314 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 315#define ath_hal_eepromWrite(_ah, _off, _data) \ 316 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 317#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 318 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 319#define ath_hal_gpioCfgInput(_ah, _gpio) \ 320 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 321#define ath_hal_gpioGet(_ah, _gpio) \ 322 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 323#define ath_hal_gpioSet(_ah, _gpio, _val) \ 324 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 325#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 326 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 327#define ath_hal_getpowerlimits(_ah, _chans, _nchan) \ 328 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan) 329#define ath_hal_getNfAdjust(_ah, _c) \ 330 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 331#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 332 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 333 334#define ath_hal_eepromDetach(_ah) \ 335 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 336#define ath_hal_eepromGet(_ah, _param, _val) \ 337 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 338#define ath_hal_eepromSet(_ah, _param, _val) \ 339 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 340#define ath_hal_eepromGetFlag(_ah, _param) \ 341 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 342#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 343 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 344#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 345 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 346 347#if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) 348/* 349 * Stuff that would naturally come from _ieee80211.h 350 */ 351#define IEEE80211_ADDR_LEN 6 352 353#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ 354#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 355#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 356#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 357 358#define IEEE80211_CRC_LEN 4 359 360#define IEEE80211_MTU 1500 361#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 362 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 363 364enum { 365 IEEE80211_T_DS, /* direct sequence spread spectrum */ 366 IEEE80211_T_FH, /* frequency hopping */ 367 IEEE80211_T_OFDM, /* frequency division multiplexing */ 368 IEEE80211_T_TURBO, /* high rate DS */ 369 IEEE80211_T_HT, /* HT - full GI */ 370}; 371#define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ 372#endif /* _NET_IF_IEEE80211_H_ */ 373 374/* NB: these are defined privately until XR support is announced */ 375enum { 376 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */ 377}; 378 379#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 380 381#define INIT_AIFS 2 382#define INIT_CWMIN 15 383#define INIT_CWMIN_11B 31 384#define INIT_CWMAX 1023 385#define INIT_SH_RETRY 10 386#define INIT_LG_RETRY 10 387#define INIT_SSH_RETRY 32 388#define INIT_SLG_RETRY 32 389 390typedef struct { 391 uint32_t tqi_ver; /* HAL TXQ verson */ 392 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 393 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 394 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 395 uint32_t tqi_priority; 396 uint32_t tqi_aifs; /* aifs */ 397 uint32_t tqi_cwmin; /* cwMin */ 398 uint32_t tqi_cwmax; /* cwMax */ 399 uint16_t tqi_shretry; /* frame short retry limit */ 400 uint16_t tqi_lgretry; /* frame long retry limit */ 401 uint32_t tqi_cbrPeriod; 402 uint32_t tqi_cbrOverflowLimit; 403 uint32_t tqi_burstTime; 404 uint32_t tqi_readyTime; 405 uint32_t tqi_physCompBuf; 406 uint32_t tqi_intFlags; /* flags for internal use */ 407} HAL_TX_QUEUE_INFO; 408 409extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 410 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 411extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 412 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 413 414typedef enum { 415 HAL_ANI_PRESENT, /* is ANI support present */ 416 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 417 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 418 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 419 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 420 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 421 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 422 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 423} HAL_ANI_CMD; 424 425#define HAL_SPUR_VAL_MASK 0x3FFF 426#define HAL_SPUR_CHAN_WIDTH 87 427#define HAL_BIN_WIDTH_BASE_100HZ 3125 428#define HAL_BIN_WIDTH_TURBO_100HZ 6250 429#define HAL_MAX_BINS_ALLOWED 28 430 431/* 432 * A = 5GHZ|OFDM 433 * T = 5GHZ|OFDM|TURBO 434 * 435 * IS_CHAN_A(T) will return TRUE. This is probably 436 * not the default behavior we want. We should migrate to a better mask -- 437 * perhaps CHANNEL_ALL. 438 * 439 * For now, IS_CHAN_G() masks itself with CHANNEL_108G. 440 * 441 */ 442 443#define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) 444#define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) 445#define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) 446#define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) 447#define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) 448#define IS_CHAN_PUREG(_c) \ 449 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) 450 451#define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) 452#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) 453#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 454#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 455#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 456#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) 457#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 458#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 459 460#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 461 462#define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) 463#define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40) 464#define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0) 465#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20) 466#define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) 467 468/* 469 * Deduce if the host cpu has big- or litt-endian byte order. 470 */ 471static __inline__ int 472isBigEndian(void) 473{ 474 union { 475 int32_t i; 476 char c[4]; 477 } u; 478 u.i = 1; 479 return (u.c[0] == 0); 480} 481 482/* unalligned little endian access */ 483#define LE_READ_2(p) \ 484 ((uint16_t) \ 485 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 486#define LE_READ_4(p) \ 487 ((uint32_t) \ 488 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 489 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 490 491/* 492 * Register manipulation macros that expect bit field defines 493 * to follow the convention that an _S suffix is appended for 494 * a shift count, while the field mask has no suffix. 495 */ 496#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 497#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 498#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 499 OS_REG_WRITE(_a, _r, \ 500 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 501#define OS_REG_SET_BIT(_a, _r, _f) \ 502 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 503#define OS_REG_CLR_BIT(_a, _r, _f) \ 504 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 505 506/* 507 * Regulatory domain support. 508 */ 509 510/* 511 * Return the max allowed antenna gain based on the current 512 * regulatory domain. 513 */ 514extern u_int ath_hal_getantennareduction(struct ath_hal *, 515 HAL_CHANNEL *, u_int twiceGain); 516/* 517 * Return the test group for the specific channel based on 518 * the current regulator domain. 519 */ 520extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *); 521/* 522 * Return whether or not a noise floor check is required 523 * based on the current regulatory domain for the specified 524 * channel. 525 */ 526extern u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *); 527 528/* 529 * Map a public channel definition to the corresponding 530 * internal data structure. This implicitly specifies 531 * whether or not the specified channel is ok to use 532 * based on the current regulatory domain constraints. 533 */ 534extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 535 const HAL_CHANNEL *); 536 537/* system-configurable parameters */ 538extern int ath_hal_dma_beacon_response_time; /* in TU's */ 539extern int ath_hal_sw_beacon_response_time; /* in TU's */ 540extern int ath_hal_additional_swba_backoff; /* in TU's */ 541 542/* wait for the register contents to have the specified value */ 543extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 544 uint32_t mask, uint32_t val); 545 546/* return the first n bits in val reversed */ 547extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 548 549/* printf interfaces */ 550extern void ath_hal_printf(struct ath_hal *, const char*, ...) 551 __printflike(2,3); 552extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 553 __printflike(2, 0); 554extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 555 556/* allocate and free memory */ 557extern void *ath_hal_malloc(size_t); 558extern void ath_hal_free(void *); 559 560/* common debugging interfaces */ 561#ifdef AH_DEBUG 562#include "ah_debug.h" 563extern int ath_hal_debug; 564extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 565 __printflike(3,4); 566#else 567#define HALDEBUG(_ah, __m, _fmt, ...) 568#endif /* AH_DEBUG */ 569 570/* 571 * Register logging definitions shared with ardecode. 572 */ 573#include "ah_decode.h" 574 575/* 576 * Common assertion interface. Note: it is a bad idea to generate 577 * an assertion failure for any recoverable event. Instead catch 578 * the violation and, if possible, fix it up or recover from it; either 579 * with an error return value or a diagnostic messages. System software 580 * does not panic unless the situation is hopeless. 581 */ 582#ifdef AH_ASSERT 583extern void ath_hal_assert_failed(const char* filename, 584 int lineno, const char* msg); 585 586#define HALASSERT(_x) do { \ 587 if (!(_x)) { \ 588 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 589 } \ 590} while (0) 591#else 592#define HALASSERT(_x) 593#endif /* AH_ASSERT */ 594 595/* 596 * Convert between microseconds and core system clocks. 597 */ 598extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 599extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 600 601/* 602 * Generic get/set capability support. Each chip overrides 603 * this routine to support chip-specific capabilities. 604 */ 605extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 606 HAL_CAPABILITY_TYPE type, uint32_t capability, 607 uint32_t *result); 608extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 609 HAL_CAPABILITY_TYPE type, uint32_t capability, 610 uint32_t setting, HAL_STATUS *status); 611 612/* 613 * Diagnostic interface. This is an open-ended interface that 614 * is opaque to applications. Diagnostic programs use this to 615 * retrieve internal data structures, etc. There is no guarantee 616 * that calling conventions for calls other than HAL_DIAG_REVS 617 * are stable between HAL releases; a diagnostic application must 618 * use the HAL revision information to deal with ABI/API differences. 619 * 620 * NB: do not renumber these, certain codes are publicly used. 621 */ 622enum { 623 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 624 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 625 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 626 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 627 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 628 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 629 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 630 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 631 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 632 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 633 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 634 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 635 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 636 HAL_DIAG_REGS = 13, /* Registers */ 637 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 638 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 639 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 640 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 641 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 642 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 643 HAL_DIAG_REGREAD = 24, /* Reg reads */ 644 HAL_DIAG_REGWRITE = 25, /* Reg writes */ 645 HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 646 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 647 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 648 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 649 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 650 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 651 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 652}; 653 654enum { 655 HAL_BB_HANG_DFS = 0x0001, 656 HAL_BB_HANG_RIFS = 0x0002, 657 HAL_BB_HANG_RX_CLEAR = 0x0004, 658 HAL_BB_HANG_UNKNOWN = 0x0080, 659 660 HAL_MAC_HANG_SIG1 = 0x0100, 661 HAL_MAC_HANG_SIG2 = 0x0200, 662 HAL_MAC_HANG_UNKNOWN = 0x8000, 663 664 HAL_BB_HANGS = HAL_BB_HANG_DFS 665 | HAL_BB_HANG_RIFS 666 | HAL_BB_HANG_RX_CLEAR 667 | HAL_BB_HANG_UNKNOWN, 668 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 669 | HAL_MAC_HANG_SIG2 670 | HAL_MAC_HANG_UNKNOWN, 671}; 672 673/* 674 * Device revision information. 675 */ 676typedef struct { 677 uint16_t ah_devid; /* PCI device ID */ 678 uint16_t ah_subvendorid; /* PCI subvendor ID */ 679 uint32_t ah_macVersion; /* MAC version id */ 680 uint16_t ah_macRev; /* MAC revision */ 681 uint16_t ah_phyRev; /* PHY revision */ 682 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 683 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 684} HAL_REVS; 685 686/* 687 * Argument payload for HAL_DIAG_SETKEY. 688 */ 689typedef struct { 690 HAL_KEYVAL dk_keyval; 691 uint16_t dk_keyix; /* key index */ 692 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 693 int dk_xor; /* XOR key data */ 694} HAL_DIAG_KEYVAL; 695 696/* 697 * Argument payload for HAL_DIAG_EEWRITE. 698 */ 699typedef struct { 700 uint16_t ee_off; /* eeprom offset */ 701 uint16_t ee_data; /* write data */ 702} HAL_DIAG_EEVAL; 703 704 705typedef struct { 706 u_int offset; /* reg offset */ 707 uint32_t val; /* reg value */ 708} HAL_DIAG_REGVAL; 709 710/* 711 * 11n compatibility tweaks. 712 */ 713#define HAL_DIAG_11N_SERVICES 0x00000003 714#define HAL_DIAG_11N_SERVICES_S 0 715#define HAL_DIAG_11N_TXSTOMP 0x0000000c 716#define HAL_DIAG_11N_TXSTOMP_S 2 717 718typedef struct { 719 int maxNoiseImmunityLevel; /* [0..4] */ 720 int totalSizeDesired[5]; 721 int coarseHigh[5]; 722 int coarseLow[5]; 723 int firpwr[5]; 724 725 int maxSpurImmunityLevel; /* [0..7] */ 726 int cycPwrThr1[8]; 727 728 int maxFirstepLevel; /* [0..2] */ 729 int firstep[3]; 730 731 uint32_t ofdmTrigHigh; 732 uint32_t ofdmTrigLow; 733 int32_t cckTrigHigh; 734 int32_t cckTrigLow; 735 int32_t rssiThrLow; 736 int32_t rssiThrHigh; 737 738 int period; /* update listen period */ 739} HAL_ANI_PARAMS; 740 741extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 742 const void *args, uint32_t argsize, 743 void **result, uint32_t *resultsize); 744 745/* 746 * Setup a h/w rate table for use. 747 */ 748extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 749 750/* 751 * Common routine for implementing getChanNoise api. 752 */ 753extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan); 754 755/* 756 * Initialization support. 757 */ 758typedef struct { 759 const uint32_t *data; 760 int rows, cols; 761} HAL_INI_ARRAY; 762 763#define HAL_INI_INIT(_ia, _data, _cols) do { \ 764 (_ia)->data = (const uint32_t *)(_data); \ 765 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 766 (_ia)->cols = (_cols); \ 767} while (0) 768#define HAL_INI_VAL(_ia, _r, _c) \ 769 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 770 771/* 772 * OS_DELAY() does a PIO READ on the PCI bus which allows 773 * other cards' DMA reads to complete in the middle of our reset. 774 */ 775#define DMA_YIELD(x) do { \ 776 if ((++(x) % 64) == 0) \ 777 OS_DELAY(1); \ 778} while (0) 779 780#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 781 int r; \ 782 for (r = 0; r < N(regArray); r++) { \ 783 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 784 DMA_YIELD(regWr); \ 785 } \ 786} while (0) 787 788#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 789 int r; \ 790 for (r = 0; r < N(regArray); r++) { \ 791 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 792 DMA_YIELD(regWr); \ 793 } \ 794} while (0) 795 796extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 797 int col, int regWr); 798extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 799 int col); 800extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 801 const uint32_t data[], int regWr); 802 803#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 804#endif /* _ATH_AH_INTERAL_H_ */ 805