ah_internal.h revision 185406
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ah_internal.h,v 1.21 2008/11/27 22:29:27 sam Exp $ 18 */ 19#ifndef _ATH_AH_INTERAL_H_ 20#define _ATH_AH_INTERAL_H_ 21/* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26#define AH_NULL 0 27#define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28#define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30#ifndef NBBY 31#define NBBY 8 /* number of bits/byte */ 32#endif 33 34#ifndef roundup 35#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 36#endif 37#ifndef howmany 38#define howmany(x, y) (((x)+((y)-1))/(y)) 39#endif 40 41#ifndef offsetof 42#define offsetof(type, field) ((size_t)(&((type *)0)->field)) 43#endif 44 45/* 46 * Remove const in a way that keeps the compiler happy. 47 * This works for gcc but may require other magic for 48 * other compilers (not sure where this should reside). 49 * Note that uintptr_t is C99. 50 */ 51#ifndef __DECONST 52#ifndef _UINTPTR_T 53#if AH_WORDSIZE == 64 54typedef unsigned long int uintptr_t; 55#else 56typedef unsigned int uintptr_t; 57#endif 58#endif 59#define __DECONST(type, var) ((type)(uintptr_t)(const void *)(var)) 60#endif 61 62typedef struct { 63 uint16_t start; /* first register */ 64 uint16_t end; /* ending register or zero */ 65} HAL_REGRANGE; 66 67/* 68 * Transmit power scale factor. 69 * 70 * NB: This is not public because we want to discourage the use of 71 * scaling; folks should use the tx power limit interface. 72 */ 73typedef enum { 74 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 75 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 76 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 77 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 78 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 79} HAL_TP_SCALE; 80 81typedef enum { 82 HAL_CAP_RADAR = 0, /* Radar capability */ 83 HAL_CAP_AR = 1, /* AR capability */ 84} HAL_PHYDIAG_CAPS; 85 86/* 87 * Each chip or class of chips registers to offer support. 88 */ 89struct ath_hal_chip { 90 const char *(*probe)(uint16_t vendorid, uint16_t devid); 91 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 92 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 93}; 94#ifndef AH_CHIP 95#define AH_CHIP(name, _probe, _attach) \ 96static struct ath_hal_chip name##_chip = { \ 97 .probe = _probe, \ 98 .attach = _attach \ 99}; \ 100OS_DATA_SET(ah_chips, name##_chip) 101#endif 102 103/* 104 * Each RF backend registers to offer support; this is mostly 105 * used by multi-chip 5212 solutions. Single-chip solutions 106 * have a fixed idea about which RF to use. 107 */ 108struct ath_hal_rf { 109 HAL_BOOL (*probe)(struct ath_hal *ah); 110 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 111}; 112#ifndef AH_RF 113#define AH_RF(name, _probe, _attach) \ 114static struct ath_hal_rf name##_rf = { \ 115 .probe = _probe, \ 116 .attach = _attach \ 117}; \ 118OS_DATA_SET(ah_rfs, name##_rf) 119#endif 120 121struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 122 123/* 124 * Internal form of a HAL_CHANNEL. Note that the structure 125 * must be defined such that you can cast references to a 126 * HAL_CHANNEL so don't shuffle the first two members. 127 */ 128typedef struct { 129 uint32_t channelFlags; 130 uint16_t channel; /* NB: must be first for casting */ 131 uint8_t privFlags; 132 int8_t maxRegTxPower; 133 int8_t maxTxPower; 134 int8_t minTxPower; /* as above... */ 135 136 HAL_BOOL bssSendHere; 137 uint8_t gainI; 138 HAL_BOOL iqCalValid; 139 uint8_t calValid; /* bitmask of cal types */ 140 int8_t iCoff; 141 int8_t qCoff; 142 int16_t rawNoiseFloor; 143 int16_t noiseFloorAdjust; 144 int8_t antennaMax; 145 uint32_t regDmnFlags; /* Flags for channel use in reg */ 146 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ 147 uint16_t mainSpur; /* cached spur value for this cahnnel */ 148} HAL_CHANNEL_INTERNAL; 149 150typedef struct { 151 uint32_t halChanSpreadSupport : 1, 152 halSleepAfterBeaconBroken : 1, 153 halCompressSupport : 1, 154 halBurstSupport : 1, 155 halFastFramesSupport : 1, 156 halChapTuningSupport : 1, 157 halTurboGSupport : 1, 158 halTurboPrimeSupport : 1, 159 halMicAesCcmSupport : 1, 160 halMicCkipSupport : 1, 161 halMicTkipSupport : 1, 162 halTkipMicTxRxKeySupport : 1, 163 halCipherAesCcmSupport : 1, 164 halCipherCkipSupport : 1, 165 halCipherTkipSupport : 1, 166 halPSPollBroken : 1, 167 halVEOLSupport : 1, 168 halBssIdMaskSupport : 1, 169 halMcastKeySrchSupport : 1, 170 halTsfAddSupport : 1, 171 halChanHalfRate : 1, 172 halChanQuarterRate : 1, 173 halHTSupport : 1, 174 halRfSilentSupport : 1, 175 halHwPhyCounterSupport : 1, 176 halWowSupport : 1, 177 halWowMatchPatternExact : 1, 178 halAutoSleepSupport : 1, 179 halFastCCSupport : 1, 180 halBtCoexSupport : 1; 181 uint32_t halRxStbcSupport : 1, 182 halTxStbcSupport : 1, 183 halGTTSupport : 1, 184 halCSTSupport : 1, 185 halRifsRxSupport : 1, 186 halRifsTxSupport : 1, 187 halExtChanDfsSupport : 1, 188 halForcePpmSupport : 1, 189 halEnhancedPmSupport : 1, 190 halMbssidAggrSupport : 1; 191 uint32_t halWirelessModes; 192 uint16_t halTotalQueues; 193 uint16_t halKeyCacheSize; 194 uint16_t halLow5GhzChan, halHigh5GhzChan; 195 uint16_t halLow2GhzChan, halHigh2GhzChan; 196 int halTstampPrecision; 197 int halRtsAggrLimit; 198 uint8_t halTxChainMask; 199 uint8_t halRxChainMask; 200 uint8_t halNumGpioPins; 201 uint8_t halNumAntCfg2GHz; 202 uint8_t halNumAntCfg5GHz; 203} HAL_CAPABILITIES; 204 205/* 206 * The ``private area'' follows immediately after the ``public area'' 207 * in the data structure returned by ath_hal_attach. Private data are 208 * used by device-independent code such as the regulatory domain support. 209 * In general, code within the HAL should never depend on data in the 210 * public area. Instead any public data needed internally should be 211 * shadowed here. 212 * 213 * When declaring a device-specific ath_hal data structure this structure 214 * is assumed to at the front; e.g. 215 * 216 * struct ath_hal_5212 { 217 * struct ath_hal_private ah_priv; 218 * ... 219 * }; 220 * 221 * It might be better to manage the method pointers in this structure 222 * using an indirect pointer to a read-only data structure but this would 223 * disallow class-style method overriding. 224 */ 225struct ath_hal_private { 226 struct ath_hal h; /* public area */ 227 228 /* NB: all methods go first to simplify initialization */ 229 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 230 uint16_t channelFlags, 231 uint16_t *lowChannel, uint16_t *highChannel); 232 u_int (*ah_getWirelessModes)(struct ath_hal*); 233 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 234 uint16_t *data); 235 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 236 uint16_t data); 237 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 238 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 239 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 240 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 241 uint32_t gpio, uint32_t val); 242 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 243 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 244 HAL_CHANNEL *, uint32_t); 245 int16_t (*ah_getNfAdjust)(struct ath_hal *, 246 const HAL_CHANNEL_INTERNAL*); 247 void (*ah_getNoiseFloor)(struct ath_hal *, 248 int16_t nfarray[]); 249 250 void *ah_eeprom; /* opaque EEPROM state */ 251 uint16_t ah_eeversion; /* EEPROM version */ 252 void (*ah_eepromDetach)(struct ath_hal *); 253 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 254 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 255 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 256 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 257 const void *args, uint32_t argsize, 258 void **result, uint32_t *resultsize); 259 260 /* 261 * Device revision information. 262 */ 263 uint16_t ah_devid; /* PCI device ID */ 264 uint16_t ah_subvendorid; /* PCI subvendor ID */ 265 uint32_t ah_macVersion; /* MAC version id */ 266 uint16_t ah_macRev; /* MAC revision */ 267 uint16_t ah_phyRev; /* PHY revision */ 268 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 269 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 270 271 272 HAL_OPMODE ah_opmode; /* operating mode from reset */ 273 HAL_CAPABILITIES ah_caps; /* device capabilities */ 274 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 275 int16_t ah_powerLimit; /* tx power cap */ 276 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 277 u_int ah_tpScale; /* tx power scale factor */ 278 uint32_t ah_11nCompat; /* 11n compat controls */ 279 280 /* 281 * State for regulatory domain handling. 282 */ 283 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */ 284 HAL_CTRY_CODE ah_countryCode; /* current country code */ 285 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */ 286 u_int ah_nchan; /* valid channels in list */ 287 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ 288 289 uint8_t ah_coverageClass; /* coverage class */ 290 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */ 291 /* 292 * RF Silent handling; setup according to the EEPROM. 293 */ 294 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 295 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 296 /* 297 * Diagnostic support for discriminating HIUERR reports. 298 */ 299 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 300 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 301}; 302 303#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 304 305#define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 306 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 307#define ath_hal_getWirelessModes(_ah) \ 308 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 309#define ath_hal_eepromRead(_ah, _off, _data) \ 310 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 311#define ath_hal_eepromWrite(_ah, _off, _data) \ 312 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 313#define ath_hal_gpioCfgOutput(_ah, _gpio) \ 314 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 315#define ath_hal_gpioCfgInput(_ah, _gpio) \ 316 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 317#define ath_hal_gpioGet(_ah, _gpio) \ 318 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 319#define ath_hal_gpioSet(_ah, _gpio, _val) \ 320 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 321#define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 322 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 323#define ath_hal_getpowerlimits(_ah, _chans, _nchan) \ 324 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan) 325#define ath_hal_getNfAdjust(_ah, _c) \ 326 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 327#define ath_hal_getNoiseFloor(_ah, _nfArray) \ 328 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 329 330#define ath_hal_eepromDetach(_ah) \ 331 AH_PRIVATE(_ah)->ah_eepromDetach(_ah) 332#define ath_hal_eepromGet(_ah, _param, _val) \ 333 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 334#define ath_hal_eepromSet(_ah, _param, _val) \ 335 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 336#define ath_hal_eepromGetFlag(_ah, _param) \ 337 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 338#define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 339 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 340#define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 341 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 342 343#if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) 344/* 345 * Stuff that would naturally come from _ieee80211.h 346 */ 347#define IEEE80211_ADDR_LEN 6 348 349#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ 350#define IEEE80211_WEP_IVLEN 3 /* 24bit */ 351#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 352#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 353 354#define IEEE80211_CRC_LEN 4 355 356#define IEEE80211_MTU 1500 357#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 358 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 359 360enum { 361 IEEE80211_T_DS, /* direct sequence spread spectrum */ 362 IEEE80211_T_FH, /* frequency hopping */ 363 IEEE80211_T_OFDM, /* frequency division multiplexing */ 364 IEEE80211_T_TURBO, /* high rate DS */ 365 IEEE80211_T_HT, /* HT - full GI */ 366}; 367#define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ 368#endif /* _NET_IF_IEEE80211_H_ */ 369 370/* NB: these are defined privately until XR support is announced */ 371enum { 372 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */ 373}; 374 375#define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 376 377#define INIT_AIFS 2 378#define INIT_CWMIN 15 379#define INIT_CWMIN_11B 31 380#define INIT_CWMAX 1023 381#define INIT_SH_RETRY 10 382#define INIT_LG_RETRY 10 383#define INIT_SSH_RETRY 32 384#define INIT_SLG_RETRY 32 385 386typedef struct { 387 uint32_t tqi_ver; /* HAL TXQ verson */ 388 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 389 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 390 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 391 uint32_t tqi_priority; 392 uint32_t tqi_aifs; /* aifs */ 393 uint32_t tqi_cwmin; /* cwMin */ 394 uint32_t tqi_cwmax; /* cwMax */ 395 uint16_t tqi_shretry; /* frame short retry limit */ 396 uint16_t tqi_lgretry; /* frame long retry limit */ 397 uint32_t tqi_cbrPeriod; 398 uint32_t tqi_cbrOverflowLimit; 399 uint32_t tqi_burstTime; 400 uint32_t tqi_readyTime; 401 uint32_t tqi_physCompBuf; 402 uint32_t tqi_intFlags; /* flags for internal use */ 403} HAL_TX_QUEUE_INFO; 404 405extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 406 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 407extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 408 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 409 410typedef enum { 411 HAL_ANI_PRESENT, /* is ANI support present */ 412 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 413 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 414 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 415 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 416 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 417 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 418 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 419} HAL_ANI_CMD; 420 421#define HAL_SPUR_VAL_MASK 0x3FFF 422#define HAL_SPUR_CHAN_WIDTH 87 423#define HAL_BIN_WIDTH_BASE_100HZ 3125 424#define HAL_BIN_WIDTH_TURBO_100HZ 6250 425#define HAL_MAX_BINS_ALLOWED 28 426 427/* 428 * A = 5GHZ|OFDM 429 * T = 5GHZ|OFDM|TURBO 430 * 431 * IS_CHAN_A(T) will return TRUE. This is probably 432 * not the default behavior we want. We should migrate to a better mask -- 433 * perhaps CHANNEL_ALL. 434 * 435 * For now, IS_CHAN_G() masks itself with CHANNEL_108G. 436 * 437 */ 438 439#define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) 440#define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) 441#define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) 442#define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) 443#define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) 444#define IS_CHAN_PUREG(_c) \ 445 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) 446 447#define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) 448#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) 449#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 450#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 451#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 452#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) 453#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 454#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 455 456#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 457 458#define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) 459#define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40) 460#define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0) 461#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20) 462#define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) 463 464/* 465 * Deduce if the host cpu has big- or litt-endian byte order. 466 */ 467static __inline__ int 468isBigEndian(void) 469{ 470 union { 471 int32_t i; 472 char c[4]; 473 } u; 474 u.i = 1; 475 return (u.c[0] == 0); 476} 477 478/* unalligned little endian access */ 479#define LE_READ_2(p) \ 480 ((uint16_t) \ 481 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 482#define LE_READ_4(p) \ 483 ((uint32_t) \ 484 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 485 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 486 487/* 488 * Register manipulation macros that expect bit field defines 489 * to follow the convention that an _S suffix is appended for 490 * a shift count, while the field mask has no suffix. 491 */ 492#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 493#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 494#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 495 OS_REG_WRITE(_a, _r, \ 496 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 497#define OS_REG_SET_BIT(_a, _r, _f) \ 498 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 499#define OS_REG_CLR_BIT(_a, _r, _f) \ 500 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 501 502/* 503 * Regulatory domain support. 504 */ 505 506/* 507 * Return the max allowed antenna gain based on the current 508 * regulatory domain. 509 */ 510extern u_int ath_hal_getantennareduction(struct ath_hal *, 511 HAL_CHANNEL *, u_int twiceGain); 512/* 513 * Return the test group for the specific channel based on 514 * the current regulator domain. 515 */ 516extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *); 517/* 518 * Return whether or not a noise floor check is required 519 * based on the current regulatory domain for the specified 520 * channel. 521 */ 522extern u_int ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *); 523 524/* 525 * Map a public channel definition to the corresponding 526 * internal data structure. This implicitly specifies 527 * whether or not the specified channel is ok to use 528 * based on the current regulatory domain constraints. 529 */ 530extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 531 const HAL_CHANNEL *); 532 533/* system-configurable parameters */ 534extern int ath_hal_dma_beacon_response_time; /* in TU's */ 535extern int ath_hal_sw_beacon_response_time; /* in TU's */ 536extern int ath_hal_additional_swba_backoff; /* in TU's */ 537 538/* wait for the register contents to have the specified value */ 539extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 540 uint32_t mask, uint32_t val); 541 542/* return the first n bits in val reversed */ 543extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 544 545/* printf interfaces */ 546extern void ath_hal_printf(struct ath_hal *, const char*, ...) 547 __printflike(2,3); 548extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) 549 __printflike(2, 0); 550extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 551 552/* allocate and free memory */ 553extern void *ath_hal_malloc(size_t); 554extern void ath_hal_free(void *); 555 556/* common debugging interfaces */ 557#ifdef AH_DEBUG 558#include "ah_debug.h" 559extern int ath_hal_debug; 560extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 561 __printflike(3,4); 562#else 563#define HALDEBUG(_ah, __m, _fmt, ...) 564#endif /* AH_DEBUG */ 565 566/* 567 * Register logging definitions shared with ardecode. 568 */ 569#include "ah_decode.h" 570 571/* 572 * Common assertion interface. Note: it is a bad idea to generate 573 * an assertion failure for any recoverable event. Instead catch 574 * the violation and, if possible, fix it up or recover from it; either 575 * with an error return value or a diagnostic messages. System software 576 * does not panic unless the situation is hopeless. 577 */ 578#ifdef AH_ASSERT 579extern void ath_hal_assert_failed(const char* filename, 580 int lineno, const char* msg); 581 582#define HALASSERT(_x) do { \ 583 if (!(_x)) { \ 584 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 585 } \ 586} while (0) 587#else 588#define HALASSERT(_x) 589#endif /* AH_ASSERT */ 590 591/* 592 * Convert between microseconds and core system clocks. 593 */ 594extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 595extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 596 597/* 598 * Generic get/set capability support. Each chip overrides 599 * this routine to support chip-specific capabilities. 600 */ 601extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 602 HAL_CAPABILITY_TYPE type, uint32_t capability, 603 uint32_t *result); 604extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 605 HAL_CAPABILITY_TYPE type, uint32_t capability, 606 uint32_t setting, HAL_STATUS *status); 607 608/* 609 * Diagnostic interface. This is an open-ended interface that 610 * is opaque to applications. Diagnostic programs use this to 611 * retrieve internal data structures, etc. There is no guarantee 612 * that calling conventions for calls other than HAL_DIAG_REVS 613 * are stable between HAL releases; a diagnostic application must 614 * use the HAL revision information to deal with ABI/API differences. 615 * 616 * NB: do not renumber these, certain codes are publicly used. 617 */ 618enum { 619 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 620 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 621 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 622 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 623 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 624 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 625 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 626 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 627 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 628 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 629 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 630 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 631 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 632 HAL_DIAG_REGS = 13, /* Registers */ 633 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 634 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 635 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 636 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 637 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 638 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 639 HAL_DIAG_REGREAD = 24, /* Reg reads */ 640 HAL_DIAG_REGWRITE = 25, /* Reg writes */ 641 HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 642 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 643 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 644 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 645 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 646 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 647 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 648}; 649 650enum { 651 HAL_BB_HANG_DFS = 0x0001, 652 HAL_BB_HANG_RIFS = 0x0002, 653 HAL_BB_HANG_RX_CLEAR = 0x0004, 654 HAL_BB_HANG_UNKNOWN = 0x0080, 655 656 HAL_MAC_HANG_SIG1 = 0x0100, 657 HAL_MAC_HANG_SIG2 = 0x0200, 658 HAL_MAC_HANG_UNKNOWN = 0x8000, 659 660 HAL_BB_HANGS = HAL_BB_HANG_DFS 661 | HAL_BB_HANG_RIFS 662 | HAL_BB_HANG_RX_CLEAR 663 | HAL_BB_HANG_UNKNOWN, 664 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 665 | HAL_MAC_HANG_SIG2 666 | HAL_MAC_HANG_UNKNOWN, 667}; 668 669/* 670 * Device revision information. 671 */ 672typedef struct { 673 uint16_t ah_devid; /* PCI device ID */ 674 uint16_t ah_subvendorid; /* PCI subvendor ID */ 675 uint32_t ah_macVersion; /* MAC version id */ 676 uint16_t ah_macRev; /* MAC revision */ 677 uint16_t ah_phyRev; /* PHY revision */ 678 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 679 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 680} HAL_REVS; 681 682/* 683 * Argument payload for HAL_DIAG_SETKEY. 684 */ 685typedef struct { 686 HAL_KEYVAL dk_keyval; 687 uint16_t dk_keyix; /* key index */ 688 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 689 int dk_xor; /* XOR key data */ 690} HAL_DIAG_KEYVAL; 691 692/* 693 * Argument payload for HAL_DIAG_EEWRITE. 694 */ 695typedef struct { 696 uint16_t ee_off; /* eeprom offset */ 697 uint16_t ee_data; /* write data */ 698} HAL_DIAG_EEVAL; 699 700 701typedef struct { 702 u_int offset; /* reg offset */ 703 uint32_t val; /* reg value */ 704} HAL_DIAG_REGVAL; 705 706/* 707 * 11n compatibility tweaks. 708 */ 709#define HAL_DIAG_11N_SERVICES 0x00000003 710#define HAL_DIAG_11N_SERVICES_S 0 711#define HAL_DIAG_11N_TXSTOMP 0x0000000c 712#define HAL_DIAG_11N_TXSTOMP_S 2 713 714typedef struct { 715 int maxNoiseImmunityLevel; /* [0..4] */ 716 int totalSizeDesired[5]; 717 int coarseHigh[5]; 718 int coarseLow[5]; 719 int firpwr[5]; 720 721 int maxSpurImmunityLevel; /* [0..7] */ 722 int cycPwrThr1[8]; 723 724 int maxFirstepLevel; /* [0..2] */ 725 int firstep[3]; 726 727 uint32_t ofdmTrigHigh; 728 uint32_t ofdmTrigLow; 729 int32_t cckTrigHigh; 730 int32_t cckTrigLow; 731 int32_t rssiThrLow; 732 int32_t rssiThrHigh; 733 734 int period; /* update listen period */ 735} HAL_ANI_PARAMS; 736 737extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 738 const void *args, uint32_t argsize, 739 void **result, uint32_t *resultsize); 740 741/* 742 * Setup a h/w rate table for use. 743 */ 744extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 745 746/* 747 * Common routine for implementing getChanNoise api. 748 */ 749extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan); 750 751/* 752 * Initialization support. 753 */ 754typedef struct { 755 const uint32_t *data; 756 int rows, cols; 757} HAL_INI_ARRAY; 758 759#define HAL_INI_INIT(_ia, _data, _cols) do { \ 760 (_ia)->data = (const uint32_t *)(_data); \ 761 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 762 (_ia)->cols = (_cols); \ 763} while (0) 764#define HAL_INI_VAL(_ia, _r, _c) \ 765 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 766 767/* 768 * OS_DELAY() does a PIO READ on the PCI bus which allows 769 * other cards' DMA reads to complete in the middle of our reset. 770 */ 771#define DMA_YIELD(x) do { \ 772 if ((++(x) % 64) == 0) \ 773 OS_DELAY(1); \ 774} while (0) 775 776#define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 777 int r; \ 778 for (r = 0; r < N(regArray); r++) { \ 779 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 780 DMA_YIELD(regWr); \ 781 } \ 782} while (0) 783 784#define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 785 int r; \ 786 for (r = 0; r < N(regArray); r++) { \ 787 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 788 DMA_YIELD(regWr); \ 789 } \ 790} while (0) 791 792extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 793 int col, int regWr); 794extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 795 int col); 796extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 797 const uint32_t data[], int regWr); 798 799#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 800#endif /* _ATH_AH_INTERAL_H_ */ 801