1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17194135Ssam * $FreeBSD$ 18185377Ssam */ 19185377Ssam 20185377Ssam#ifndef _DEV_ATH_DESC_H 21185377Ssam#define _DEV_ATH_DESC_H 22185377Ssam 23185377Ssam#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ 24185377Ssam 25185377Ssam/* 26229790Sadrian * For now, define this for the structure definitions. 27229790Sadrian * Because of how the HAL / driver module currently builds, 28229790Sadrian * it's not very feasible to build the module without 29229790Sadrian * this defined. The rest of the code (eg in the driver 30229790Sadrian * body) can work fine with these fields being uninitialised; 31229790Sadrian * they'll be initialised to 0 anyway. 32229790Sadrian */ 33229790Sadrian 34229791Sadrian#ifndef AH_SUPPORT_AR5416 35229790Sadrian#define AH_SUPPORT_AR5416 1 36229791Sadrian#endif 37229790Sadrian 38229790Sadrian/* 39185377Ssam * Transmit descriptor status. This structure is filled 40185377Ssam * in only after the tx descriptor process method finds a 41185377Ssam * ``done'' descriptor; at which point it returns something 42185377Ssam * other than HAL_EINPROGRESS. 43185377Ssam * 44185377Ssam * Note that ts_antenna may not be valid for all h/w. It 45185377Ssam * should be used only if non-zero. 46185377Ssam */ 47185377Ssamstruct ath_tx_status { 48185377Ssam uint16_t ts_seqnum; /* h/w assigned sequence number */ 49185377Ssam uint16_t ts_tstamp; /* h/w assigned timestamp */ 50185377Ssam uint8_t ts_status; /* frame status, 0 => xmit ok */ 51185377Ssam uint8_t ts_rate; /* h/w transmit rate index */ 52185377Ssam int8_t ts_rssi; /* tx ack RSSI */ 53185377Ssam uint8_t ts_shortretry; /* # short retries */ 54185377Ssam uint8_t ts_longretry; /* # long retries */ 55185377Ssam uint8_t ts_virtcol; /* virtual collision count */ 56185377Ssam uint8_t ts_antenna; /* antenna information */ 57185377Ssam uint8_t ts_finaltsi; /* final transmit series index */ 58185377Ssam#ifdef AH_SUPPORT_AR5416 59185377Ssam /* 802.11n status */ 60238843Sadrian uint8_t ts_flags; /* misc flags */ 61238843Sadrian uint8_t ts_queue_id; /* AR9300: TX queue id */ 62238843Sadrian uint8_t ts_desc_id; /* AR9300: TX descriptor id */ 63238843Sadrian uint8_t ts_tid; /* TID */ 64185377Ssam/* #define ts_rssi ts_rssi_combined */ 65238843Sadrian uint32_t ts_ba_low; /* blockack bitmap low */ 66238843Sadrian uint32_t ts_ba_high; /* blockack bitmap high */ 67238843Sadrian uint32_t ts_evm0; /* evm bytes */ 68238843Sadrian uint32_t ts_evm1; 69238843Sadrian uint32_t ts_evm2; 70238843Sadrian int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 71238843Sadrian int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 72238843Sadrian uint8_t ts_pad[2]; 73185377Ssam#endif /* AH_SUPPORT_AR5416 */ 74185377Ssam}; 75185377Ssam 76185377Ssam/* bits found in ts_status */ 77185377Ssam#define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 78185377Ssam#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 79185377Ssam#define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 80185377Ssam#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 81185377Ssam#define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */ 82185377Ssam 83185377Ssam/* bits found in ts_flags */ 84185377Ssam#define HAL_TX_BA 0x01 /* Block Ack seen */ 85185377Ssam#define HAL_TX_AGGR 0x02 /* Aggregate */ 86185377Ssam#define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 87185377Ssam#define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 88185377Ssam#define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 89185377Ssam 90185377Ssam/* 91185377Ssam * Receive descriptor status. This structure is filled 92185377Ssam * in only after the rx descriptor process method finds a 93185377Ssam * ``done'' descriptor; at which point it returns something 94185377Ssam * other than HAL_EINPROGRESS. 95185377Ssam * 96185377Ssam * If rx_status is zero, then the frame was received ok; 97185377Ssam * otherwise the error information is indicated and rs_phyerr 98185377Ssam * contains a phy error code if HAL_RXERR_PHY is set. In general 99185377Ssam * the frame contents is undefined when an error occurred thought 100185377Ssam * for some errors (e.g. a decryption error), it may be meaningful. 101185377Ssam * 102185377Ssam * Note that the receive timestamp is expanded using the TSF to 103185377Ssam * at least 15 bits (regardless of what the h/w provides directly). 104185377Ssam * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 105185377Ssam * find out if the hardware is capable. 106185377Ssam * 107185377Ssam * rx_rssi is in units of dbm above the noise floor. This value 108185377Ssam * is measured during the preamble and PLCP; i.e. with the initial 109185377Ssam * 4us of detection. The noise floor is typically a consistent 110185377Ssam * -96dBm absolute power in a 20MHz channel. 111185377Ssam */ 112185377Ssamstruct ath_rx_status { 113185377Ssam uint16_t rs_datalen; /* rx frame length */ 114185377Ssam uint8_t rs_status; /* rx status, 0 => recv ok */ 115185377Ssam uint8_t rs_phyerr; /* phy error code */ 116185377Ssam int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ 117185377Ssam uint8_t rs_keyix; /* key cache index */ 118185377Ssam uint8_t rs_rate; /* h/w receive rate index */ 119185377Ssam uint8_t rs_more; /* more descriptors follow */ 120185377Ssam uint32_t rs_tstamp; /* h/w assigned timestamp */ 121185377Ssam uint32_t rs_antenna; /* antenna information */ 122185377Ssam#ifdef AH_SUPPORT_AR5416 123185377Ssam /* 802.11n status */ 124185377Ssam int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 125185377Ssam int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 126185377Ssam uint8_t rs_isaggr; /* is part of the aggregate */ 127185377Ssam uint8_t rs_moreaggr; /* more frames in aggr to follow */ 128238314Sadrian uint16_t rs_flags; /* misc flags */ 129185377Ssam uint8_t rs_num_delims; /* number of delims in aggr */ 130238314Sadrian uint8_t rs_spare0; /* padding */ 131185377Ssam uint32_t rs_evm0; /* evm bytes */ 132185377Ssam uint32_t rs_evm1; 133238314Sadrian uint32_t rs_evm2; 134220438Sadrian uint32_t rs_evm3; /* needed for ar9300 and later */ 135220438Sadrian uint32_t rs_evm4; /* needed for ar9300 and later */ 136185377Ssam#endif /* AH_SUPPORT_AR5416 */ 137185377Ssam}; 138185377Ssam 139185377Ssam/* bits found in rs_status */ 140185377Ssam#define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 141185377Ssam#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 142185377Ssam#define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 143185377Ssam#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 144185377Ssam#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 145238314Sadrian#define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */ 146238314Sadrian#define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */ 147185377Ssam 148185377Ssam/* bits found in rs_flags */ 149238314Sadrian#define HAL_RX_MORE 0x0001 /* more descriptors follow */ 150238314Sadrian#define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */ 151238314Sadrian#define HAL_RX_GI 0x0004 /* full gi */ 152238314Sadrian#define HAL_RX_2040 0x0008 /* 40 Mhz */ 153238314Sadrian#define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */ 154238314Sadrian#define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */ 155238314Sadrian#define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */ 156238314Sadrian#define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */ 157238314Sadrian#define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */ 158250346Sadrian#define HAL_RX_STBC 0x0200 /* Is an STBC frame */ 159185377Ssam 160251399Sadrian/* 161251399Sadrian * This is the format of RSSI[2] on the AR9285/AR9485. 162251399Sadrian * It encodes the LNA configuration information. 163251399Sadrian * 164251399Sadrian * For boards with an external diversity antenna switch, 165251399Sadrian * HAL_RX_LNA_EXTCFG encodes which configuration was 166251399Sadrian * used (antenna 1 or antenna 2.) This feeds into the 167251399Sadrian * switch table and ensures that the given antenna was 168251399Sadrian * connected to an LNA. 169251399Sadrian */ 170251399Sadrian#define HAL_RX_LNA_LNACFG 0x80 /* 1 = main LNA config used, 0 = ALT */ 171251399Sadrian#define HAL_RX_LNA_EXTCFG 0x40 /* 0 = external diversity ant1, 1 = ant2 */ 172251399Sadrian#define HAL_RX_LNA_CFG_USED 0x30 /* 2 bits; LNA config used on RX */ 173251399Sadrian#define HAL_RX_LNA_CFG_USED_S 4 174251399Sadrian#define HAL_RX_LNA_CFG_MAIN 0x0c /* 2 bits; "Main" LNA config */ 175251399Sadrian#define HAL_RX_LNA_CFG_ALT 0x02 /* 2 bits; "Alt" LNA config */ 176251399Sadrian 177251399Sadrian/* 178251399Sadrian * This is the format of RSSI_EXT[2] on the AR9285/AR9485. 179251399Sadrian * It encodes the switch table configuration and fast diversity 180251399Sadrian * value. 181251399Sadrian */ 182251399Sadrian#define HAL_RX_LNA_FASTDIV 0x40 /* 1 = fast diversity measurement done */ 183251399Sadrian#define HAL_RX_LNA_SWITCH_0 0x30 /* 2 bits; sw_0[1:0] */ 184251399Sadrian#define HAL_RX_LNA_SWITCH_COM 0x0f /* 4 bits, sw_com[3:0] */ 185251399Sadrian 186185377Ssamenum { 187185377Ssam HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 188185377Ssam HAL_PHYERR_TIMING = 1, /* Timing error */ 189185377Ssam HAL_PHYERR_PARITY = 2, /* Illegal parity */ 190185377Ssam HAL_PHYERR_RATE = 3, /* Illegal rate */ 191185377Ssam HAL_PHYERR_LENGTH = 4, /* Illegal length */ 192185377Ssam HAL_PHYERR_RADAR = 5, /* Radar detect */ 193185377Ssam HAL_PHYERR_SERVICE = 6, /* Illegal service */ 194185377Ssam HAL_PHYERR_TOR = 7, /* Transmit override receive */ 195222584Sadrian /* NB: these are specific to the 5212 and later */ 196185377Ssam HAL_PHYERR_OFDM_TIMING = 17, /* */ 197185377Ssam HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 198185377Ssam HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 199185377Ssam HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 200185377Ssam HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 201185377Ssam HAL_PHYERR_OFDM_SERVICE = 22, /* */ 202185377Ssam HAL_PHYERR_OFDM_RESTART = 23, /* */ 203222584Sadrian HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */ 204185377Ssam HAL_PHYERR_CCK_TIMING = 25, /* */ 205185377Ssam HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 206185377Ssam HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 207185377Ssam HAL_PHYERR_CCK_SERVICE = 30, /* */ 208185377Ssam HAL_PHYERR_CCK_RESTART = 31, /* */ 209224538Sadrian HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */ 210224538Sadrian HAL_PHYERR_CCK_POWER_DROP = 33, /* */ 211224538Sadrian /* AR5416 and later */ 212224538Sadrian HAL_PHYERR_HT_CRC_ERROR = 34, /* */ 213224538Sadrian HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */ 214224538Sadrian HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */ 215238314Sadrian 216238314Sadrian HAL_PHYERR_SPECTRAL = 38, 217185377Ssam}; 218185377Ssam 219185377Ssam/* value found in rs_keyix to mark invalid entries */ 220185377Ssam#define HAL_RXKEYIX_INVALID ((uint8_t) -1) 221185377Ssam/* value used to specify no encryption key for xmit */ 222185377Ssam#define HAL_TXKEYIX_INVALID ((u_int) -1) 223185377Ssam 224185377Ssam/* XXX rs_antenna definitions */ 225185377Ssam 226185377Ssam/* 227185377Ssam * Definitions for the software frame/packet descriptors used by 228185380Ssam * the Atheros HAL. This definition obscures hardware-specific 229185380Ssam * details from the driver. Drivers are expected to fillin the 230185377Ssam * portions of a descriptor that are not opaque then use HAL calls 231185377Ssam * to complete the work. Status for completed frames is returned 232185377Ssam * in a device-independent format. 233185377Ssam */ 234185377Ssam#ifdef AH_SUPPORT_AR5416 235185377Ssam#define HAL_DESC_HW_SIZE 20 236185377Ssam#else 237185377Ssam#define HAL_DESC_HW_SIZE 4 238185377Ssam#endif /* AH_SUPPORT_AR5416 */ 239185377Ssam 240185377Ssamstruct ath_desc { 241185377Ssam /* 242185377Ssam * The following definitions are passed directly 243185377Ssam * the hardware and managed by the HAL. Drivers 244185377Ssam * should not touch those elements marked opaque. 245185377Ssam */ 246185377Ssam uint32_t ds_link; /* phys address of next descriptor */ 247185377Ssam uint32_t ds_data; /* phys address of data buffer */ 248185377Ssam uint32_t ds_ctl0; /* opaque DMA control 0 */ 249185377Ssam uint32_t ds_ctl1; /* opaque DMA control 1 */ 250185377Ssam uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 251185377Ssam}; 252185377Ssam 253239381Sadrianstruct ath_desc_txedma { 254239381Sadrian uint32_t ds_info; 255239381Sadrian uint32_t ds_link; 256239381Sadrian uint32_t ds_hw[21]; /* includes buf/len */ 257239381Sadrian}; 258239381Sadrian 259185377Ssamstruct ath_desc_status { 260185377Ssam union { 261185377Ssam struct ath_tx_status tx;/* xmit status */ 262185377Ssam struct ath_rx_status rx;/* recv status */ 263185377Ssam } ds_us; 264185377Ssam}; 265185377Ssam 266185377Ssam#define ds_txstat ds_us.tx 267185377Ssam#define ds_rxstat ds_us.rx 268185377Ssam 269185377Ssam/* flags passed to tx descriptor setup methods */ 270237153Sadrian/* This is a uint16_t field in ath_buf, just be warned! */ 271185377Ssam#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 272185377Ssam#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 273185377Ssam#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 274185377Ssam#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 275185377Ssam#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 276185377Ssam#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 277185377Ssam/* NB: this only affects frame, not any RTS/CTS */ 278185377Ssam#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 279185377Ssam#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 280185377Ssam#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 281185377Ssam#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 282238843Sadrian#define HAL_TXDESC_LOWRXCHAIN 0x0400 /* switch to low RX chain */ 283301041Sadrian#define HAL_TXDESC_LDPC 0x1000 /* Set LDPC TX for all rates */ 284301041Sadrian#define HAL_TXDESC_HWTS 0x2000 /* Request Azimuth Timestamp in TX payload */ 285185377Ssam 286185377Ssam/* flags passed to rx descriptor setup methods */ 287185377Ssam#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 288185377Ssam#endif /* _DEV_ATH_DESC_H */ 289