ah_btcoex.h revision 301089
1/* 2 * Copyright (c) 2014 Qualcomm Atheros, Inc. 3 * All Rights Reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah_btcoex.h 301089 2016-06-01 01:43:46Z adrian $ 18 */ 19#ifndef __ATH_HAL_BTCOEX_H__ 20#define __ATH_HAL_BTCOEX_H__ 21 22/* 23 * General BT coexistence definitions. 24 */ 25typedef enum { 26 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 27 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 28 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 29 HAL_MAX_BT_MODULES 30} HAL_BT_MODULE; 31 32typedef struct { 33 HAL_BT_MODULE bt_module; 34 u_int8_t bt_coex_config; 35 u_int8_t bt_gpio_bt_active; 36 u_int8_t bt_gpio_bt_priority; 37 u_int8_t bt_gpio_wlan_active; 38 u_int8_t bt_active_polarity; 39 HAL_BOOL bt_single_ant; 40 u_int8_t bt_dutyCycle; 41 u_int8_t bt_isolation; 42 u_int8_t bt_period; 43} HAL_BT_COEX_INFO; 44 45typedef enum { 46 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 47 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 48 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 49 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 50} HAL_BT_COEX_MODE; 51 52typedef enum { 53 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 54 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 55 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 56 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 57 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 58 HAL_BT_COEX_CFG_MCI /* MCI */ 59} HAL_BT_COEX_CFG; 60 61typedef enum { 62 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 63 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 64 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 65 HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */ 66 HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */ 67} HAL_BT_COEX_SET_PARAMETER; 68 69/* 70 * MCI specific coexistence definitions. 71 */ 72 73#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 74#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 75/* Check Rx Diversity is allowed */ 76#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 77/* Check Diversity is on or off */ 78#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 79 80#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 81/* main: LNA1, alt: LNA2 */ 82#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 83#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 84#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 85#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 86#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 87 88#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 89 90#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 91 92#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 93 94#define HAL_BT_COEX_LOW_ACK_POWER 0x0 95#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 96 97typedef enum { 98 HAL_BT_COEX_NO_STOMP = 0, 99 HAL_BT_COEX_STOMP_ALL, 100 HAL_BT_COEX_STOMP_LOW, 101 HAL_BT_COEX_STOMP_NONE, 102 HAL_BT_COEX_STOMP_ALL_FORCE, 103 HAL_BT_COEX_STOMP_LOW_FORCE, 104} HAL_BT_COEX_STOMP_TYPE; 105 106typedef struct { 107 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 108 u_int8_t bt_time_extend; 109 110 /* 111 * extend rx_clear as long as txsm is 112 * transmitting or waiting for ack. 113 */ 114 HAL_BOOL bt_txstate_extend; 115 116 /* 117 * extend rx_clear so that when tx_frame 118 * is asserted, rx_clear will drop. 119 */ 120 HAL_BOOL bt_txframe_extend; 121 122 /* 123 * coexistence mode 124 */ 125 HAL_BT_COEX_MODE bt_mode; 126 127 /* 128 * treat BT high priority traffic as 129 * a quiet collision 130 */ 131 HAL_BOOL bt_quiet_collision; 132 133 /* 134 * invert rx_clear as WLAN_ACTIVE 135 */ 136 HAL_BOOL bt_rxclear_polarity; 137 138 /* 139 * slotted mode only. indicate the time in usec 140 * from the rising edge of BT_ACTIVE to the time 141 * BT_PRIORITY can be sampled to indicate priority. 142 */ 143 u_int8_t bt_priority_time; 144 145 /* 146 * slotted mode only. indicate the time in usec 147 * from the rising edge of BT_ACTIVE to the time 148 * BT_PRIORITY can be sampled to indicate tx/rx and 149 * BT_FREQ is sampled. 150 */ 151 u_int8_t bt_first_slot_time; 152 153 /* 154 * slotted mode only. rx_clear and bt_ant decision 155 * will be held the entire time that BT_ACTIVE is asserted, 156 * otherwise the decision is made before every slot boundary. 157 */ 158 HAL_BOOL bt_hold_rxclear; 159} HAL_BT_COEX_CONFIG; 160 161#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 162#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 163#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */ 164#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */ 165#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010 166#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020 167 168#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ 169 170typedef enum mci_message_header { 171 MCI_LNA_CTRL = 0x10, /* len = 0 */ 172 MCI_CONT_NACK = 0x20, /* len = 0 */ 173 MCI_CONT_INFO = 0x30, /* len = 4 */ 174 MCI_CONT_RST = 0x40, /* len = 0 */ 175 MCI_SCHD_INFO = 0x50, /* len = 16 */ 176 MCI_CPU_INT = 0x60, /* len = 4 */ 177 MCI_SYS_WAKING = 0x70, /* len = 0 */ 178 MCI_GPM = 0x80, /* len = 16 */ 179 MCI_LNA_INFO = 0x90, /* len = 1 */ 180 MCI_LNA_STATE = 0x94, 181 MCI_LNA_TAKE = 0x98, 182 MCI_LNA_TRANS = 0x9c, 183 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 184 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 185 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 186 MCI_REMOTE_RESET = 0xff /* len = 16 */ 187} MCI_MESSAGE_HEADER; 188 189/* Default remote BT device MCI COEX version */ 190#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 191#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 192/* Local WLAN MCI COEX version */ 193#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 194#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 195 196typedef enum mci_gpm_subtype { 197 MCI_GPM_BT_CAL_REQ = 0, 198 MCI_GPM_BT_CAL_GRANT = 1, 199 MCI_GPM_BT_CAL_DONE = 2, 200 MCI_GPM_WLAN_CAL_REQ = 3, 201 MCI_GPM_WLAN_CAL_GRANT = 4, 202 MCI_GPM_WLAN_CAL_DONE = 5, 203 MCI_GPM_COEX_AGENT = 0x0C, 204 MCI_GPM_RSVD_PATTERN = 0xFE, 205 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE, 206 MCI_GPM_BT_DEBUG = 0xFF 207} MCI_GPM_SUBTYPE_T; 208 209typedef enum mci_gpm_coex_opcode { 210 MCI_GPM_COEX_VERSION_QUERY = 0, 211 MCI_GPM_COEX_VERSION_RESPONSE = 1, 212 MCI_GPM_COEX_STATUS_QUERY = 2, 213 MCI_GPM_COEX_HALT_BT_GPM = 3, 214 MCI_GPM_COEX_WLAN_CHANNELS = 4, 215 MCI_GPM_COEX_BT_PROFILE_INFO = 5, 216 MCI_GPM_COEX_BT_STATUS_UPDATE = 6, 217 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7 218} MCI_GPM_COEX_OPCODE_T; 219 220typedef enum mci_gpm_coex_query_type { 221 /* WLAN information */ 222 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01, 223 /* BT information */ 224 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01, 225 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02, 226 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04 227} MCI_GPM_COEX_QUERY_TYPE_T; 228 229typedef enum mci_gpm_coex_halt_bt_gpm { 230 MCI_GPM_COEX_BT_GPM_UNHALT = 0, 231 MCI_GPM_COEX_BT_GPM_HALT = 1 232} MCI_GPM_COEX_HALT_BT_GPM_T; 233 234typedef enum mci_gpm_coex_profile_type { 235 MCI_GPM_COEX_PROFILE_UNKNOWN = 0, 236 MCI_GPM_COEX_PROFILE_RFCOMM = 1, 237 MCI_GPM_COEX_PROFILE_A2DP = 2, 238 MCI_GPM_COEX_PROFILE_HID = 3, 239 MCI_GPM_COEX_PROFILE_BNEP = 4, 240 MCI_GPM_COEX_PROFILE_VOICE = 5, 241 MCI_GPM_COEX_PROFILE_MAX 242} MCI_GPM_COEX_PROFILE_TYPE_T; 243 244typedef enum mci_gpm_coex_profile_state { 245 MCI_GPM_COEX_PROFILE_STATE_END = 0, 246 MCI_GPM_COEX_PROFILE_STATE_START = 1 247} MCI_GPM_COEX_PROFILE_STATE_T; 248 249typedef enum mci_gpm_coex_profile_role { 250 MCI_GPM_COEX_PROFILE_SLAVE = 0, 251 MCI_GPM_COEX_PROFILE_MASTER = 1 252} MCI_GPM_COEX_PROFILE_ROLE_T; 253 254typedef enum mci_gpm_coex_bt_status_type { 255 MCI_GPM_COEX_BT_NONLINK_STATUS = 0, 256 MCI_GPM_COEX_BT_LINK_STATUS = 1 257} MCI_GPM_COEX_BT_STATUS_TYPE_T; 258 259typedef enum mci_gpm_coex_bt_status_state { 260 MCI_GPM_COEX_BT_NORMAL_STATUS = 0, 261 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1 262} MCI_GPM_COEX_BT_STATUS_STATE_T; 263 264#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff 265 266typedef enum mci_gpm_coex_bt_updata_flags_op { 267 MCI_GPM_COEX_BT_FLAGS_READ = 0x00, 268 MCI_GPM_COEX_BT_FLAGS_SET = 0x01, 269 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02 270} MCI_GPM_COEX_BT_FLAGS_OP_T; 271 272/* MCI GPM/Coex opcode/type definitions */ 273enum { 274 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 275 MCI_GPM_COEX_B_GPM_TYPE = 4, 276 MCI_GPM_COEX_B_GPM_OPCODE = 5, 277 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 278 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 279 /* MCI_GPM_COEX_VERSION_QUERY */ 280 /* MCI_GPM_COEX_VERSION_RESPONSE */ 281 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 282 MCI_GPM_COEX_B_MINOR_VERSION = 7, 283 /* MCI_GPM_COEX_STATUS_QUERY */ 284 MCI_GPM_COEX_B_BT_BITMAP = 6, 285 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 286 /* MCI_GPM_COEX_HALT_BT_GPM */ 287 MCI_GPM_COEX_B_HALT_STATE = 6, 288 /* MCI_GPM_COEX_WLAN_CHANNELS */ 289 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 290 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 291 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 292 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 293 MCI_GPM_COEX_B_PROFILE_STATE = 8, 294 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 295 MCI_GPM_COEX_B_PROFILE_RATE = 10, 296 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 297 MCI_GPM_COEX_H_PROFILE_T = 12, 298 MCI_GPM_COEX_B_PROFILE_W = 14, 299 MCI_GPM_COEX_B_PROFILE_A = 15, 300 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 301 MCI_GPM_COEX_B_STATUS_TYPE = 6, 302 MCI_GPM_COEX_B_STATUS_LINKID = 7, 303 MCI_GPM_COEX_B_STATUS_STATE = 8, 304 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 305 MCI_GPM_COEX_B_BT_FLAGS_OP = 10, 306 MCI_GPM_COEX_W_BT_FLAGS = 6 307}; 308 309#define MCI_GPM_RECYCLE(_p_gpm) \ 310 { \ 311 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \ 312 } 313#define MCI_GPM_TYPE(_p_gpm) \ 314 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 315#define MCI_GPM_OPCODE(_p_gpm) \ 316 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 317 318#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \ 319 { \ 320 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \ 321 } 322#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \ 323 { \ 324 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 325 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \ 326 } 327#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 328 329#define MCI_NUM_BT_CHANNELS 79 330 331#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ 332 { \ 333 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 334 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 335 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \ 336 } \ 337 } 338 339#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \ 340 { \ 341 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 342 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 343 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \ 344 } \ 345 } 346 347#define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 348#define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 349#define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004 350#define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 351#define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 352#define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 353#define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 354#define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 355#define HAL_MCI_INTERRUPT_RX_MSG 0x00000200 356#define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 357#define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 358#define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 359 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 360 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 361 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 362 363#define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 364#define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 365#define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 366#define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 367#define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 368#define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 369#define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 370#define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 371#define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 372#define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 373#define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 374#define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 375#define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 376 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 377 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 378 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 379 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST) 380 381typedef enum mci_bt_state { 382 MCI_BT_SLEEP, 383 MCI_BT_AWAKE, 384 MCI_BT_CAL_START, 385 MCI_BT_CAL 386} MCI_BT_STATE_T; 387 388/* Type of state query */ 389typedef enum mci_state_type { 390 HAL_MCI_STATE_ENABLE, 391 HAL_MCI_STATE_INIT_GPM_OFFSET, 392 HAL_MCI_STATE_NEXT_GPM_OFFSET, 393 HAL_MCI_STATE_LAST_GPM_OFFSET, 394 HAL_MCI_STATE_BT, 395 HAL_MCI_STATE_SET_BT_SLEEP, 396 HAL_MCI_STATE_SET_BT_AWAKE, 397 HAL_MCI_STATE_SET_BT_CAL_START, 398 HAL_MCI_STATE_SET_BT_CAL, 399 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET, 400 HAL_MCI_STATE_REMOTE_SLEEP, 401 HAL_MCI_STATE_CONT_RSSI_POWER, 402 HAL_MCI_STATE_CONT_PRIORITY, 403 HAL_MCI_STATE_CONT_TXRX, 404 HAL_MCI_STATE_RESET_REQ_WAKE, 405 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION, 406 HAL_MCI_STATE_SET_BT_COEX_VERSION, 407 HAL_MCI_STATE_SEND_WLAN_CHANNELS, 408 HAL_MCI_STATE_SEND_VERSION_QUERY, 409 HAL_MCI_STATE_SEND_STATUS_QUERY, 410 HAL_MCI_STATE_NEED_FLUSH_BT_INFO, 411 HAL_MCI_STATE_SET_CONCUR_TX_PRI, 412 HAL_MCI_STATE_RECOVER_RX, 413 HAL_MCI_STATE_NEED_FTP_STOMP, 414 HAL_MCI_STATE_NEED_TUNING, 415 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX, 416 HAL_MCI_STATE_DEBUG, 417 HAL_MCI_STATE_MAX 418} HAL_MCI_STATE_TYPE; 419 420#define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1 421 422#define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 423#define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 424#define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 425#define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 426#define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020 427#define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 428#define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 429#define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 430#define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 431#define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 432#define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800 433#define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000 434#define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000 435 436#define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde 437/* 438 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1 439 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1 440 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1 441 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1 442 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0 443 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1 444 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1 445 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1 446 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0 447 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1 448 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1 449 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1 450 HAL_MCI_BT_MCI_FLAGS_OTHER = 1 451*/ 452 453#define HAL_MCI_TOGGLE_BT_MCI_FLAGS \ 454 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \ 455 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \ 456 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \ 457 HAL_MCI_BT_MCI_FLAGS_MCI_MODE ) 458 459#define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000 460#define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 461#define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS 462 463#define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 464#define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000 465#define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \ 466 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS) 467 468#define HAL_MCI_GPM_NOMORE 0 469#define HAL_MCI_GPM_MORE 1 470#define HAL_MCI_GPM_INVALID 0xffffffff 471 472#define ATH_AIC_MAX_BT_CHANNEL 79 473 474/* 475 * Default value for Jupiter is 0x00002201 476 * Default value for Aphrodite is 0x00002282 477 */ 478#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 479#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 480#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 481#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 482#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 483#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 484#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 485#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 486#define ATH_MCI_CONFIG_AGGR_THRESH_S 8 487#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 488#define ATH_MCI_CONFIG_CLK_DIV 0x00003000 489#define ATH_MCI_CONFIG_CLK_DIV_S 12 490#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 491#define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000 492#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000 493#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16 494#define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000 495#define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23 496#define ATH_MCI_CONFIG_ANT_ARCH 0x07000000 497#define ATH_MCI_CONFIG_ANT_ARCH_S 24 498#define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000 499#define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27 500#define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000 501#define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000 502#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 503#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 504 505#define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \ 506 ATH_MCI_CONFIG_MCI_OBS_TXRX | \ 507 ATH_MCI_CONFIG_MCI_OBS_BT ) 508#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F 509 510#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00 511#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01 512#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02 513#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03 514#define ATH_MCI_ANT_ARCH_3_ANT 0x04 515 516#define MCI_ANT_ARCH_PA_LNA_SHARED(c) \ 517 ((MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \ 518 (MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED)) 519 520#define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01 521#define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02 522#define ATH_MCI_CONCUR_TX_DEBUG 0x03 523 524#endif 525