amrreg.h revision 70285
1/*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/amr/amrreg.h 70285 2000-12-22 22:23:56Z msmith $ 28 */ 29 30/******************************************************************************** 31 ******************************************************************************** 32 Driver parameters 33 ******************************************************************************** 34 ********************************************************************************/ 35 36/* 37 * We could actually use all 17 segments, but using only 16 means that 38 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 39 * maps crossing page boundaries. 40 * 41 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 42 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 43 * since we allocate the s/g maps contiguously anyway? 44 */ 45#define AMR_NSEG 16 46 47#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 48#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 49#define AMR_MAXLD 40 50 51#define AMR_MAX_CHANNELS 4 52#define AMR_MAX_TARGETS 15 53#define AMR_MAX_LUNS 7 54#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 55 56#define AMR_MAX_CDB_LEN 0x0a 57#define AMR_MAX_REQ_SENSE_LEN 0x20 58 59#define AMR_BLKSIZE 512 /* constant for all controllers */ 60 61/* 62 * Perform at-startup board initialisation. 63 * At this point in time, this code doesn't work correctly, so leave it disabled. 64 */ 65/*#define AMR_BOARD_INIT*/ 66 67/******************************************************************************** 68 ******************************************************************************** 69 Interface Magic Numbers 70 ******************************************************************************** 71 ********************************************************************************/ 72 73/* 74 * Mailbox commands 75 */ 76#define AMR_CMD_LREAD 0x01 77#define AMR_CMD_LWRITE 0x02 78#define AMR_CMD_PASS 0x03 79#define AMR_CMD_EXT_ENQUIRY 0x04 80#define AMR_CMD_ENQUIRY 0x05 81#define AMR_CMD_FLUSH 0x0a 82#define AMR_CMD_EXT_ENQUIRY2 0x0c 83#define AMR_CONFIG_PRODINFO 0x0e 84#define AMR_CMD_GET_MACHINEID 0x36 85#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 86#define AMR_CMD_CONFIG 0xa1 87#define AMR_CONFIG_PRODUCT_INFO 0x0e 88#define AMR_CONFIG_ENQ3 0x0f 89#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 90#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 91#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 92 93/* 94 * Command results 95 */ 96#define AMR_STATUS_SUCCESS 0x00 97#define AMR_STATUS_ABORTED 0x02 98#define AMR_STATUS_FAILED 0x80 99 100/* 101 * Physical/logical drive states 102 */ 103#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 104#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 105#define AMR_DRV_OFFLINE 0x00 106#define AMR_DRV_DEGRADED 0x01 107#define AMR_DRV_OPTIMAL 0x02 108#define AMR_DRV_ONLINE 0x03 109#define AMR_DRV_FAILED 0x04 110#define AMR_DRV_REBUILD 0x05 111#define AMR_DRV_HOTSPARE 0x06 112 113/* 114 * Logical drive properties 115 */ 116#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 117#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 118#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 119#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 120 121/* 122 * Battery status 123 */ 124#define AMR_BATT_MODULE_MISSING 0x01 125#define AMR_BATT_LOW_VOLTAGE 0x02 126#define AMR_BATT_TEMP_HIGH 0x04 127#define AMR_BATT_PACK_MISSING 0x08 128#define AMR_BATT_CHARGE_MASK 0x30 129#define AMR_BATT_CHARGE_DONE 0x00 130#define AMR_BATT_CHARGE_INPROG 0x10 131#define AMR_BATT_CHARGE_FAIL 0x20 132#define AMR_BATT_CYCLES_EXCEEDED 0x40 133 134 135/******************************************************************************** 136 ******************************************************************************** 137 8LD Firmware Interface 138 ******************************************************************************** 139 ********************************************************************************/ 140 141/* 142 * Array constraints 143 */ 144#define AMR_8LD_MAXDRIVES 8 145#define AMR_8LD_MAXCHAN 5 146#define AMR_8LD_MAXTARG 15 147#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 148 149/* 150 * Adapter Info structure 151 */ 152struct amr_adapter_info 153{ 154 u_int8_t aa_maxio; 155 u_int8_t aa_rebuild_rate; 156 u_int8_t aa_maxtargchan; 157 u_int8_t aa_channels; 158 u_int8_t aa_firmware[4]; 159 u_int16_t aa_flashage; 160 u_int8_t aa_chipsetvalue; 161 u_int8_t aa_memorysize; 162 u_int8_t aa_cacheflush; 163 u_int8_t aa_bios[4]; 164 u_int8_t aa_boardtype; 165 u_int8_t aa_scsisensealert; 166 u_int8_t aa_writeconfigcount; 167 u_int8_t aa_driveinsertioncount; 168 u_int8_t aa_inserteddrive; 169 u_int8_t aa_batterystatus; 170 u_int8_t res1; 171} __attribute__ ((packed)); 172 173/* 174 * Logical Drive info structure 175 */ 176struct amr_logdrive_info 177{ 178 u_int8_t al_numdrives; 179 u_int8_t res1[3]; 180 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 181 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 182 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 183} __attribute__ ((packed)); 184 185/* 186 * Physical Drive info structure 187 */ 188struct amr_physdrive_info 189{ 190 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 191 u_int8_t ap_predictivefailure; 192} __attribute__ ((packed)); 193 194/* 195 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 196 * AMR_CMD_EXT_ENQUIRY2. 197 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 198 */ 199struct amr_enquiry 200{ 201 struct amr_adapter_info ae_adapter; /* X X X */ 202 struct amr_logdrive_info ae_ldrv; /* X X X */ 203 struct amr_physdrive_info ae_pdrv; /* X X X */ 204 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 205 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 206 u_int32_t ae_extlen; /* X */ 207 u_int16_t ae_subsystem; /* X */ 208 u_int16_t ae_subvendor; /* X */ 209 u_int32_t ae_signature; /* X */ 210#define AMR_SIG_431 0xfffe0001 211#define AMR_SIG_438 0xfffd0002 212#define AMR_SIG_762 0xfffc0003 213#define AMR_SIG_T5 0xfffb0004 214#define AMR_SIG_466 0xfffa0005 215#define AMR_SIG_467 0xfff90006 216#define AMR_SIG_T7 0xfff80007 217#define AMR_SIG_490 0xfff70008 218 u_int8_t res2[844]; /* X */ 219} __attribute__ ((packed)); 220 221 222/******************************************************************************** 223 ******************************************************************************** 224 40LD Firmware Interface 225 ******************************************************************************** 226 ********************************************************************************/ 227 228/* 229 * Array constraints 230 */ 231#define AMR_40LD_MAXDRIVES 40 232#define AMR_40LD_MAXCHAN 16 233#define AMR_40LD_MAXTARG 16 234#define AMR_40LD_MAXPHYSDRIVES 256 235 236/* 237 * Product Info structure 238 */ 239struct amr_prodinfo 240{ 241 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 242 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 243 * logical drives, 0x20 maximum stripes and 0x08 244 * maximum spans */ 245 u_int8_t ap_firmware[16]; /* printable identifiers */ 246 u_int8_t ap_bios[16]; 247 u_int8_t ap_product[80]; 248 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 249 u_int8_t ap_nschan; /* number of SCSI channels present */ 250 u_int8_t ap_fcloops; /* number of fibre loops present */ 251 u_int8_t ap_memtype; /* memory type */ 252 u_int32_t ap_signature; 253 u_int16_t ap_memsize; /* onboard memory in MB */ 254 u_int16_t ap_subsystem; /* subsystem identifier */ 255 u_int16_t ap_subvendor; /* subsystem vendor ID */ 256 u_int8_t ap_numnotifyctr; /* number of notify counters */ 257} __attribute__((packed)); 258 259/* 260 * Notify structure 261 */ 262struct amr_notify 263{ 264 u_int32_t an_globalcounter; /* change counter */ 265 266 u_int8_t an_paramcounter; /* parameter change counter */ 267 u_int8_t an_paramid; 268#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 269#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 270#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 271#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 272#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 273 u_int16_t an_paramval; 274 275 u_int8_t an_writeconfigcounter; /* write config occurred */ 276 u_int8_t res1[3]; 277 278 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 279 u_int8_t an_ldrvopid; 280 u_int8_t an_ldrvopcmd; 281#define AMR_LDRVOP_CHECK 0x01 282#define AMR_LDRVOP_INIT 0x02 283#define AMR_LDRVOP_REBUILD 0x03 284 u_int8_t an_ldrvopstatus; 285#define AMR_LDRVOP_SUCCESS 0x00 286#define AMR_LDRVOP_FAILED 0x01 287#define AMR_LDRVOP_ABORTED 0x02 288#define AMR_LDRVOP_CORRECTED 0x03 289#define AMR_LDRVOP_STARTED 0x04 290 291 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 292 u_int8_t an_ldrvstateid; 293 u_int8_t an_ldrvstatenew; 294 u_int8_t an_ldrvstateold; 295 296 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 297 u_int8_t an_pdrvstateid; 298 u_int8_t an_pdrvstatenew; 299 u_int8_t an_pdrvstateold; 300 301 u_int8_t an_pdrvfmtcounter; 302 u_int8_t an_pdrvfmtid; 303 u_int8_t an_pdrvfmtval; 304#define AMR_FORMAT_START 0x01 305#define AMR_FORMAT_COMPLETE 0x02 306 u_int8_t res2; 307 308 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 309 u_int8_t an_targxferid; 310 u_int8_t an_targxferval; 311 u_int8_t res3; 312 313 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 314 u_int8_t an_fcloopidpdrvid; 315 u_int8_t an_fcloopid0; 316 u_int8_t an_fcloopid1; 317 318 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 319 u_int8_t an_fcloopstate0; 320 u_int8_t an_fcloopstate1; 321 u_int8_t res4; 322} __attribute__((packed)); 323 324/* 325 * Enquiry3 structure 326 */ 327struct amr_enquiry3 328{ 329 u_int32_t ae_datasize; /* valid data size in this structure */ 330 union { /* event notify structure */ 331 struct amr_notify n; 332 u_int8_t pad[0x80]; 333 } ae_notify; 334 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 335 u_int8_t ae_cacheflush; /* flush interval in seconds */ 336 u_int8_t ae_sensealert; 337 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 338 u_int8_t ae_batterystatus; 339 u_int8_t ae_numldrives; 340 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 341 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 342 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 343 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 344 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */ 345 u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES]; 346 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 347 348 u_int8_t res1[263]; /* pad to 1024 bytes */ 349} __attribute__ ((packed)); 350 351 352/******************************************************************************** 353 ******************************************************************************** 354 Mailbox and Command Structures 355 ******************************************************************************** 356 ********************************************************************************/ 357 358#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 359 360struct amr_mailbox 361{ 362 u_int8_t mb_command; 363 u_int8_t mb_ident; 364 u_int16_t mb_blkcount; 365 u_int32_t mb_lba; 366 u_int32_t mb_physaddr; 367 u_int8_t mb_drive; 368 u_int8_t mb_nsgelem; 369 u_int8_t res1; 370 u_int8_t mb_busy; 371 u_int8_t mb_nstatus; 372 u_int8_t mb_status; 373 u_int8_t mb_completed[46]; 374 u_int8_t mb_poll; 375 u_int8_t mb_ack; 376 u_int8_t res2[16]; 377} __attribute__ ((packed)); 378 379struct amr_mailbox64 380{ 381 u_int32_t mb64_segment; /* for 64-bit controllers */ 382 struct amr_mailbox mb; 383} __attribute__ ((packed)); 384 385struct amr_mailbox_ioctl 386{ 387 u_int8_t mb_command; 388 u_int8_t mb_ident; 389 u_int8_t mb_channel; 390 u_int8_t mb_param; 391 u_int8_t mb_pad[4]; 392 u_int32_t mb_physaddr; 393 u_int8_t mb_drive; 394 u_int8_t mb_nsgelem; 395 u_int8_t res1; 396 u_int8_t mb_busy; 397 u_int8_t mb_nstatus; 398 u_int8_t mb_completed[46]; 399 u_int8_t mb_poll; 400 u_int8_t mb_ack; 401 u_int8_t res4[16]; 402} __attribute__ ((packed)); 403 404struct amr_sgentry 405{ 406 u_int32_t sg_addr; 407 u_int32_t sg_count; 408} __attribute__ ((packed)); 409 410struct amr_passthrough 411{ 412 u_int8_t ap_timeout:3; 413 u_int8_t ap_ars:1; 414 u_int8_t ap_dummy:3; 415 u_int8_t ap_islogical:1; 416 u_int8_t ap_logical_drive_no; 417 u_int8_t ap_channel; 418 u_int8_t ap_scsi_id; 419 u_int8_t ap_queue_tag; 420 u_int8_t ap_queue_action; 421 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 422 u_int8_t ap_cdb_length; 423 u_int8_t ap_request_sense_length; 424 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 425 u_int8_t ap_no_sg_elements; 426 u_int8_t ap_scsi_status; 427 u_int32_t ap_data_transfer_address; 428 u_int32_t ap_data_transfer_length; 429} __attribute__ ((packed)); 430 431#ifdef _KERNEL 432/******************************************************************************** 433 ******************************************************************************** 434 "Quartz" i960 PCI bridge interface 435 ******************************************************************************** 436 ********************************************************************************/ 437 438#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 439#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 440#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 441 442/* 443 * Doorbell registers 444 */ 445#define AMR_QIDB 0x20 446#define AMR_QODB 0x2c 447#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 448#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 449#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 450 451/* 452 * Initialisation status 453 */ 454#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 455#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 456#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 457#define AMR_QINIT_INPROG 0xdc /* init in progress */ 458#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 459#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 460#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 461#define AMR_QINIT_DONE 0x9c /* init successfully done */ 462 463/* 464 * I/O primitives 465 */ 466#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 467#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 468#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 469#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 470 471#ifdef AMR_BOARD_INIT 472#define AMR_QRESET(sc) \ 473 do { \ 474 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 475 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 476 } while (0) 477#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 478#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 479#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 480#endif 481 482/******************************************************************************** 483 ******************************************************************************** 484 "Standard" old-style ASIC bridge interface 485 ******************************************************************************** 486 ********************************************************************************/ 487 488/* 489 * I/O registers 490 */ 491#define AMR_SCMD 0x10 /* command/ack register (write) */ 492#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 493#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 494#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 495#define AMR_SMBOX_1 0x15 496#define AMR_SMBOX_2 0x16 497#define AMR_SMBOX_3 0x17 /* high byte */ 498#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 499#define AMR_SINTR 0x1a /* interrupt status */ 500 501/* 502 * I/O magic numbers 503 */ 504#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 505#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 506#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 507#define AMR_SINTR_VALID 0x40 /* in SINTR */ 508#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 509#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 510 511/* 512 * Initialisation status 513 */ 514#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 515#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 516#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 517#define AMR_SINIT_INPROG 0x11 /* init in progress */ 518#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 519#define AMR_SINIT_DONE 0x99 /* init successfully done */ 520 521/* 522 * I/O primitives 523 */ 524#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 525#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 526#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 527#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 528#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 529#define AMR_SENABLE_INTR(sc) \ 530 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 531 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 532#define AMR_SDISABLE_INTR(sc) \ 533 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 534 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 535#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 536 537#ifdef AMR_BOARD_INIT 538#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 539#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 540#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 541#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 542#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 543#endif 544 545#endif _KERNEL 546