amrreg.h revision 302408
1/*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Copyright (c) 2002 Eric Moore 28 * Copyright (c) 2002 LSI Logic Corporation 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The party using or redistributing the source code and binary forms 40 * agrees to the disclaimer below and the terms and conditions set forth 41 * herein. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 * 55 * 56 * $FreeBSD: stable/11/sys/dev/amr/amrreg.h 176041 2008-02-06 14:26:31Z scottl $ 57 */ 58 59/******************************************************************************** 60 ******************************************************************************** 61 Driver parameters 62 ******************************************************************************** 63 ********************************************************************************/ 64 65/* 66 * We could actually use all 17 segments, but using only 16 means that 67 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 68 * maps crossing page boundaries. 69 * 70 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 71 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 72 * since we allocate the s/g maps contiguously anyway? 73 */ 74/* 75 * emoore - Oct 21, 2002 76 * firmware doesn't have sglist boundary restrictions. 77 * The sgelem can be set to 26 78 */ 79#define AMR_NSEG 26 80 81#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 82#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 83#define AMR_MAXLD 40 84 85#define AMR_MAX_CHANNELS 8 86#define AMR_MAX_TARGETS 15 87#define AMR_MAX_LUNS 7 88#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 89 90#define AMR_MAX_CDB_LEN 0x0a 91#define AMR_MAX_EXTCDB_LEN 0x10 92#define AMR_MAX_REQ_SENSE_LEN 0x20 93 94#define AMR_BLKSIZE 512 /* constant for all controllers */ 95 96/* 97 * Perform at-startup board initialisation. 98 * At this point in time, this code doesn't work correctly, so leave it disabled. 99 */ 100/*#define AMR_BOARD_INIT*/ 101 102/******************************************************************************** 103 ******************************************************************************** 104 Interface Magic Numbers 105 ******************************************************************************** 106 ********************************************************************************/ 107 108/* 109 * Mailbox commands 110 */ 111#define AMR_CMD_LREAD 0x01 112#define AMR_CMD_LWRITE 0x02 113#define AMR_CMD_PASS 0x03 114#define AMR_CMD_EXT_ENQUIRY 0x04 115#define AMR_CMD_ENQUIRY 0x05 116#define AMR_CMD_FLUSH 0x0a 117#define AMR_CMD_EXT_ENQUIRY2 0x0c 118#define AMR_CONFIG_PRODINFO 0x0e 119#define AMR_CMD_GET_MACHINEID 0x36 120#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 121#define AMR_CMD_CONFIG 0xa1 122#define AMR_CMD_LREAD64 0xa7 123#define AMR_CMD_LWRITE64 0xa8 124#define AMR_CMD_PASS_64 0xc3 125#define AMR_CMD_EXTPASS 0xe3 126 127#define AMR_CONFIG_READ_NVRAM_CONFIG 0x04 128#define AMR_CONFIG_WRITE_NVRAM_CONFIG 0x0d 129#define AMR_CONFIG_PRODUCT_INFO 0x0e 130#define AMR_CONFIG_ENQ3 0x0f 131#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 132#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 133#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 134 135/* 136 * Command for random deletion of logical drives 137 */ 138#define FC_DEL_LOGDRV 0xA4 139#define OP_SUP_DEL_LOGDRV 0x2A 140#define OP_GET_LDID_MAP 0x18 141#define OP_DEL_LOGDRV 0x1C 142 143/* 144 * Command for random deletion of logical drives 145 */ 146#define FC_DEL_LOGDRV 0xA4 147#define OP_SUP_DEL_LOGDRV 0x2A 148#define OP_GET_LDID_MAP 0x18 149#define OP_DEL_LOGDRV 0x1C 150 151/* 152 * Command results 153 */ 154#define AMR_STATUS_SUCCESS 0x00 155#define AMR_STATUS_ABORTED 0x02 156#define AMR_STATUS_FAILED 0x80 157 158/* 159 * Physical/logical drive states 160 */ 161#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 162#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 163#define AMR_DRV_OFFLINE 0x00 164#define AMR_DRV_DEGRADED 0x01 165#define AMR_DRV_OPTIMAL 0x02 166#define AMR_DRV_ONLINE 0x03 167#define AMR_DRV_FAILED 0x04 168#define AMR_DRV_REBUILD 0x05 169#define AMR_DRV_HOTSPARE 0x06 170 171/* 172 * Logical drive properties 173 */ 174#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 175#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 176#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 177#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 178 179/* 180 * Battery status 181 */ 182#define AMR_BATT_MODULE_MISSING 0x01 183#define AMR_BATT_LOW_VOLTAGE 0x02 184#define AMR_BATT_TEMP_HIGH 0x04 185#define AMR_BATT_PACK_MISSING 0x08 186#define AMR_BATT_CHARGE_MASK 0x30 187#define AMR_BATT_CHARGE_DONE 0x00 188#define AMR_BATT_CHARGE_INPROG 0x10 189#define AMR_BATT_CHARGE_FAIL 0x20 190#define AMR_BATT_CYCLES_EXCEEDED 0x40 191 192 193/******************************************************************************** 194 ******************************************************************************** 195 8LD Firmware Interface 196 ******************************************************************************** 197 ********************************************************************************/ 198 199/* 200 * Array constraints 201 */ 202#define AMR_8LD_MAXDRIVES 8 203#define AMR_8LD_MAXCHAN 5 204#define AMR_8LD_MAXTARG 15 205#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 206 207/* 208 * Adapter Info structure 209 */ 210struct amr_adapter_info 211{ 212 u_int8_t aa_maxio; 213 u_int8_t aa_rebuild_rate; 214 u_int8_t aa_maxtargchan; 215 u_int8_t aa_channels; 216 u_int8_t aa_firmware[4]; 217 u_int16_t aa_flashage; 218 u_int8_t aa_chipsetvalue; 219 u_int8_t aa_memorysize; 220 u_int8_t aa_cacheflush; 221 u_int8_t aa_bios[4]; 222 u_int8_t aa_boardtype; 223 u_int8_t aa_scsisensealert; 224 u_int8_t aa_writeconfigcount; 225 u_int8_t aa_driveinsertioncount; 226 u_int8_t aa_inserteddrive; 227 u_int8_t aa_batterystatus; 228 u_int8_t res1; 229} __packed; 230 231/* 232 * Logical Drive info structure 233 */ 234struct amr_logdrive_info 235{ 236 u_int8_t al_numdrives; 237 u_int8_t res1[3]; 238 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 239 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 240 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 241} __packed; 242 243/* 244 * Physical Drive info structure 245 */ 246struct amr_physdrive_info 247{ 248 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 249 u_int8_t ap_predictivefailure; 250} __packed; 251 252/* 253 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 254 * AMR_CMD_EXT_ENQUIRY2. 255 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 256 */ 257struct amr_enquiry 258{ 259 struct amr_adapter_info ae_adapter; /* X X X */ 260 struct amr_logdrive_info ae_ldrv; /* X X X */ 261 struct amr_physdrive_info ae_pdrv; /* X X X */ 262 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 263 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 264 u_int32_t ae_extlen; /* X */ 265 u_int16_t ae_subsystem; /* X */ 266 u_int16_t ae_subvendor; /* X */ 267 u_int32_t ae_signature; /* X */ 268#define AMR_SIG_431 0xfffe0001 269#define AMR_SIG_438 0xfffd0002 270#define AMR_SIG_762 0xfffc0003 271#define AMR_SIG_T5 0xfffb0004 272#define AMR_SIG_466 0xfffa0005 273#define AMR_SIG_467 0xfff90006 274#define AMR_SIG_T7 0xfff80007 275#define AMR_SIG_490 0xfff70008 276 u_int8_t res2[844]; /* X */ 277} __packed; 278 279 280/******************************************************************************** 281 ******************************************************************************** 282 40LD Firmware Interface 283 ******************************************************************************** 284 ********************************************************************************/ 285 286/* 287 * Array constraints 288 */ 289#define AMR_40LD_MAXDRIVES 40 290#define AMR_40LD_MAXCHAN 16 291#define AMR_40LD_MAXTARG 16 292#define AMR_40LD_MAXPHYSDRIVES 256 293 294/* 295 * Product Info structure 296 */ 297struct amr_prodinfo 298{ 299 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 300 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 301 * logical drives, 0x20 maximum stripes and 0x08 302 * maximum spans */ 303 u_int8_t ap_firmware[16]; /* printable identifiers */ 304 u_int8_t ap_bios[16]; 305 u_int8_t ap_product[80]; 306 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 307 u_int8_t ap_nschan; /* number of SCSI channels present */ 308 u_int8_t ap_fcloops; /* number of fibre loops present */ 309 u_int8_t ap_memtype; /* memory type */ 310 u_int32_t ap_signature; 311 u_int16_t ap_memsize; /* onboard memory in MB */ 312 u_int16_t ap_subsystem; /* subsystem identifier */ 313 u_int16_t ap_subvendor; /* subsystem vendor ID */ 314 u_int8_t ap_numnotifyctr; /* number of notify counters */ 315} __packed; 316 317/* 318 * Notify structure 319 */ 320struct amr_notify 321{ 322 u_int32_t an_globalcounter; /* change counter */ 323 324 u_int8_t an_paramcounter; /* parameter change counter */ 325 u_int8_t an_paramid; 326#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 327#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 328#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 329#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 330#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 331 u_int16_t an_paramval; 332 333 u_int8_t an_writeconfigcounter; /* write config occurred */ 334 u_int8_t res1[3]; 335 336 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 337 u_int8_t an_ldrvopid; 338 u_int8_t an_ldrvopcmd; 339#define AMR_LDRVOP_CHECK 0x01 340#define AMR_LDRVOP_INIT 0x02 341#define AMR_LDRVOP_REBUILD 0x03 342 u_int8_t an_ldrvopstatus; 343#define AMR_LDRVOP_SUCCESS 0x00 344#define AMR_LDRVOP_FAILED 0x01 345#define AMR_LDRVOP_ABORTED 0x02 346#define AMR_LDRVOP_CORRECTED 0x03 347#define AMR_LDRVOP_STARTED 0x04 348 349 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 350 u_int8_t an_ldrvstateid; 351 u_int8_t an_ldrvstatenew; 352 u_int8_t an_ldrvstateold; 353 354 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 355 u_int8_t an_pdrvstateid; 356 u_int8_t an_pdrvstatenew; 357 u_int8_t an_pdrvstateold; 358 359 u_int8_t an_pdrvfmtcounter; 360 u_int8_t an_pdrvfmtid; 361 u_int8_t an_pdrvfmtval; 362#define AMR_FORMAT_START 0x01 363#define AMR_FORMAT_COMPLETE 0x02 364 u_int8_t res2; 365 366 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 367 u_int8_t an_targxferid; 368 u_int8_t an_targxferval; 369 u_int8_t res3; 370 371 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 372 u_int8_t an_fcloopidpdrvid; 373 u_int8_t an_fcloopid0; 374 u_int8_t an_fcloopid1; 375 376 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 377 u_int8_t an_fcloopstate0; 378 u_int8_t an_fcloopstate1; 379 u_int8_t res4; 380} __packed; 381 382/* 383 * Enquiry3 structure 384 */ 385struct amr_enquiry3 386{ 387 u_int32_t ae_datasize; /* valid data size in this structure */ 388 union { /* event notify structure */ 389 struct amr_notify n; 390 u_int8_t pad[0x80]; 391 } ae_notify; 392 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 393 u_int8_t ae_cacheflush; /* flush interval in seconds */ 394 u_int8_t ae_sensealert; 395 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 396 u_int8_t ae_batterystatus; 397 u_int8_t ae_numldrives; 398 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 399 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 400 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 401 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 402 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* logical drive state */ 403 u_int8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */ 404 u_int16_t ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES / 16]; 405 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 406 407 u_int8_t res1[263]; /* pad to 1024 bytes */ 408} __packed; 409 410 411/******************************************************************************** 412 ******************************************************************************** 413 Mailbox and Command Structures 414 ******************************************************************************** 415 ********************************************************************************/ 416 417#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 418 419struct amr_mailbox 420{ 421 u_int8_t mb_command; 422 u_int8_t mb_ident; 423 u_int16_t mb_blkcount; /* u_int8_t opcode */ 424 /* u_int8_t subopcode */ 425 u_int32_t mb_lba; 426 u_int32_t mb_physaddr; 427 u_int8_t mb_drive; 428 u_int8_t mb_nsgelem; /* u_int8_t rserv[0] */ 429 u_int8_t res1; /* u_int8_t rserv[1] */ 430 u_int8_t mb_busy; /* u_int8_t rserv[2] */ 431 u_int8_t mb_nstatus; 432 u_int8_t mb_status; 433 u_int8_t mb_completed[46]; 434 u_int8_t mb_poll; 435 u_int8_t mb_ack; 436 u_int8_t res2[16]; 437} __packed; 438 439struct amr_mailbox64 440{ 441 u_int8_t pad[8]; /* Needed for alignment */ 442 u_int32_t sg64_lo; /* S/G pointer for 64-bit commands */ 443 u_int32_t sg64_hi; /* S/G pointer for 64-bit commands */ 444 struct amr_mailbox mb; 445} __packed; 446 447struct amr_mailbox_ioctl 448{ 449 u_int8_t mb_command; 450 u_int8_t mb_ident; 451 u_int8_t mb_channel; 452 u_int8_t mb_param; 453 u_int8_t mb_pad[4]; 454 u_int32_t mb_physaddr; 455 u_int8_t mb_drive; 456 u_int8_t mb_nsgelem; 457 u_int8_t res1; 458 u_int8_t mb_busy; 459 u_int8_t mb_nstatus; 460 u_int8_t mb_completed[46]; 461 u_int8_t mb_poll; 462 u_int8_t mb_ack; 463 u_int8_t res4[16]; 464} __packed; 465 466struct amr_sgentry 467{ 468 u_int32_t sg_addr; 469 u_int32_t sg_count; 470} __packed; 471 472struct amr_sg64entry 473{ 474 u_int64_t sg_addr; 475 u_int32_t sg_count; 476} __packed; 477 478struct amr_passthrough 479{ 480 u_int8_t ap_timeout:3; 481 u_int8_t ap_ars:1; 482 u_int8_t ap_dummy:3; 483 u_int8_t ap_islogical:1; 484 u_int8_t ap_logical_drive_no; 485 u_int8_t ap_channel; 486 u_int8_t ap_scsi_id; 487 u_int8_t ap_queue_tag; 488 u_int8_t ap_queue_action; 489 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 490 u_int8_t ap_cdb_length; 491 u_int8_t ap_request_sense_length; 492 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 493 u_int8_t ap_no_sg_elements; 494 u_int8_t ap_scsi_status; 495 u_int32_t ap_data_transfer_address; 496 u_int32_t ap_data_transfer_length; 497} __packed; 498 499struct amr_ext_passthrough 500{ 501 u_int8_t ap_timeout:3; 502 u_int8_t ap_ars:1; 503 u_int8_t ap_rsvd1:1; 504 u_int8_t ap_cd_rom:1; 505 u_int8_t ap_rsvd2:1; 506 u_int8_t ap_islogical:1; 507 u_int8_t ap_logical_drive_no; 508 u_int8_t ap_channel; 509 u_int8_t ap_scsi_id; 510 u_int8_t ap_queue_tag; 511 u_int8_t ap_queue_action; 512 u_int8_t ap_cdb_length; 513 u_int8_t ap_rsvd3; 514 u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN]; 515 u_int8_t ap_no_sg_elements; 516 u_int8_t ap_scsi_status; 517 u_int8_t ap_request_sense_length; 518 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 519 u_int8_t ap_rsvd4; 520 u_int32_t ap_data_transfer_address; 521 u_int32_t ap_data_transfer_length; 522} __packed; 523 524struct amr_linux_ioctl { 525 u_int32_t inlen; 526 u_int32_t outlen; 527 union { 528 u_int8_t fca[16]; 529 struct { 530 u_int8_t opcode; 531 u_int8_t subopcode; 532 u_int16_t adapno; 533 u_int32_t buffer; 534 u_int8_t pad[4]; 535 u_int32_t length; 536 } __packed fcs; 537 } __packed ui; 538 u_int8_t mbox[18]; 539 struct amr_passthrough pthru; 540 u_int32_t data; 541 u_int8_t pad[4]; 542} __packed; 543 544#ifdef _KERNEL 545/******************************************************************************** 546 ******************************************************************************** 547 "Quartz" i960 PCI bridge interface 548 ******************************************************************************** 549 ********************************************************************************/ 550 551#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 552#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 553#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 554 555/* 556 * Doorbell registers 557 */ 558#define AMR_QIDB 0x20 559#define AMR_QODB 0x2c 560#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 561#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 562#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 563 564/* 565 * Initialisation status 566 */ 567#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 568#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 569#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 570#define AMR_QINIT_INPROG 0xdc /* init in progress */ 571#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 572#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 573#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 574#define AMR_QINIT_DONE 0x9c /* init successfully done */ 575 576/* 577 * I/O primitives 578 */ 579#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 580#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 581#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 582#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 583 584#ifdef AMR_BOARD_INIT 585#define AMR_QRESET(sc) \ 586 do { \ 587 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 588 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 589 } while (0) 590#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 591#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 592#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 593#endif 594 595/******************************************************************************** 596 ******************************************************************************** 597 "Standard" old-style ASIC bridge interface 598 ******************************************************************************** 599 ********************************************************************************/ 600 601/* 602 * I/O registers 603 */ 604#define AMR_SCMD 0x10 /* command/ack register (write) */ 605#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 606#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 607#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 608#define AMR_SMBOX_1 0x15 609#define AMR_SMBOX_2 0x16 610#define AMR_SMBOX_3 0x17 /* high byte */ 611#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 612#define AMR_SINTR 0x1a /* interrupt status */ 613 614/* 615 * I/O magic numbers 616 */ 617#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 618#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 619#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 620#define AMR_SINTR_VALID 0x40 /* in SINTR */ 621#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 622#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 623 624/* 625 * Initialisation status 626 */ 627#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 628#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 629#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 630#define AMR_SINIT_INPROG 0x11 /* init in progress */ 631#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 632#define AMR_SINIT_DONE 0x99 /* init successfully done */ 633 634/* 635 * I/O primitives 636 */ 637#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 638#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 639#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 640#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 641#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 642#define AMR_SENABLE_INTR(sc) \ 643 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 644 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 645#define AMR_SDISABLE_INTR(sc) \ 646 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 647 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 648#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 649 650#ifdef AMR_BOARD_INIT 651#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 652#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 653#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 654#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 655#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 656#endif 657 658#endif /* _KERNEL */ 659