amrreg.h revision 175622
1/*- 2 * Copyright (c) 1999,2000 Michael Smith 3 * Copyright (c) 2000 BSDi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Copyright (c) 2002 Eric Moore 28 * Copyright (c) 2002 LSI Logic Corporation 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * 2. Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in the 38 * documentation and/or other materials provided with the distribution. 39 * 3. The party using or redistributing the source code and binary forms 40 * agrees to the disclaimer below and the terms and conditions set forth 41 * herein. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 44 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 45 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 46 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 47 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 48 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 49 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 51 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 52 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 53 * SUCH DAMAGE. 54 * 55 * 56 * $FreeBSD: head/sys/dev/amr/amrreg.h 175622 2008-01-24 07:26:53Z scottl $ 57 */ 58 59/******************************************************************************** 60 ******************************************************************************** 61 Driver parameters 62 ******************************************************************************** 63 ********************************************************************************/ 64 65/* 66 * We could actually use all 17 segments, but using only 16 means that 67 * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about 68 * maps crossing page boundaries. 69 * 70 * The AMI documentation says that the limit is 26. Unfortunately, there's no way to 71 * cleanly fit more than 16 entries in without a page boundary. But is this a concern, 72 * since we allocate the s/g maps contiguously anyway? 73 */ 74/* 75 * emoore - Oct 21, 2002 76 * firmware doesn't have sglist boundary restrictions. 77 * The sgelem can be set to 26 78 */ 79#define AMR_NSEG 26 80 81#define AMR_MAXCMD 255 /* ident = 0 not allowed */ 82#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */ 83#define AMR_MAXLD 40 84 85#define AMR_MAX_CHANNELS 8 86#define AMR_MAX_TARGETS 15 87#define AMR_MAX_LUNS 7 88#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */ 89 90#define AMR_MAX_CDB_LEN 0x0a 91#define AMR_MAX_EXTCDB_LEN 0x10 92#define AMR_MAX_REQ_SENSE_LEN 0x20 93 94#define AMR_BLKSIZE 512 /* constant for all controllers */ 95 96/* 97 * Perform at-startup board initialisation. 98 * At this point in time, this code doesn't work correctly, so leave it disabled. 99 */ 100/*#define AMR_BOARD_INIT*/ 101 102/******************************************************************************** 103 ******************************************************************************** 104 Interface Magic Numbers 105 ******************************************************************************** 106 ********************************************************************************/ 107 108/* 109 * Mailbox commands 110 */ 111#define AMR_CMD_LREAD 0x01 112#define AMR_CMD_LWRITE 0x02 113#define AMR_CMD_PASS 0x03 114#define AMR_CMD_EXT_ENQUIRY 0x04 115#define AMR_CMD_ENQUIRY 0x05 116#define AMR_CMD_FLUSH 0x0a 117#define AMR_CMD_EXT_ENQUIRY2 0x0c 118#define AMR_CONFIG_PRODINFO 0x0e 119#define AMR_CMD_GET_MACHINEID 0x36 120#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */ 121#define AMR_CMD_CONFIG 0xa1 122#define AMR_CMD_LREAD64 0xa7 123#define AMR_CMD_LWRITE64 0xa8 124#define AMR_CMD_PASS_64 0xc3 125#define AMR_CMD_EXTPASS 0xe3 126 127#define AMR_CONFIG_READ_NVRAM_CONFIG 0x04 128#define AMR_CONFIG_WRITE_NVRAM_CONFIG 0x0d 129#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 130#define AMR_CONFIG_PRODUCT_INFO 0x0e 131#define AMR_CONFIG_ENQ3 0x0f 132#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01 133#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02 134#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03 135 136/* 137 * Command for random deletion of logical drives 138 */ 139#define FC_DEL_LOGDRV 0xA4 140#define OP_SUP_DEL_LOGDRV 0x2A 141#define OP_GET_LDID_MAP 0x18 142#define OP_DEL_LOGDRV 0x1C 143 144/* 145 * Command for random deletion of logical drives 146 */ 147#define FC_DEL_LOGDRV 0xA4 148#define OP_SUP_DEL_LOGDRV 0x2A 149#define OP_GET_LDID_MAP 0x18 150#define OP_DEL_LOGDRV 0x1C 151 152/* 153 * Command results 154 */ 155#define AMR_STATUS_SUCCESS 0x00 156#define AMR_STATUS_ABORTED 0x02 157#define AMR_STATUS_FAILED 0x80 158 159/* 160 * Physical/logical drive states 161 */ 162#define AMR_DRV_CURSTATE(x) ((x) & 0x0f) 163#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f) 164#define AMR_DRV_OFFLINE 0x00 165#define AMR_DRV_DEGRADED 0x01 166#define AMR_DRV_OPTIMAL 0x02 167#define AMR_DRV_ONLINE 0x03 168#define AMR_DRV_FAILED 0x04 169#define AMR_DRV_REBUILD 0x05 170#define AMR_DRV_HOTSPARE 0x06 171 172/* 173 * Logical drive properties 174 */ 175#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */ 176#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */ 177#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */ 178#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */ 179 180/* 181 * Battery status 182 */ 183#define AMR_BATT_MODULE_MISSING 0x01 184#define AMR_BATT_LOW_VOLTAGE 0x02 185#define AMR_BATT_TEMP_HIGH 0x04 186#define AMR_BATT_PACK_MISSING 0x08 187#define AMR_BATT_CHARGE_MASK 0x30 188#define AMR_BATT_CHARGE_DONE 0x00 189#define AMR_BATT_CHARGE_INPROG 0x10 190#define AMR_BATT_CHARGE_FAIL 0x20 191#define AMR_BATT_CYCLES_EXCEEDED 0x40 192 193 194/******************************************************************************** 195 ******************************************************************************** 196 8LD Firmware Interface 197 ******************************************************************************** 198 ********************************************************************************/ 199 200/* 201 * Array constraints 202 */ 203#define AMR_8LD_MAXDRIVES 8 204#define AMR_8LD_MAXCHAN 5 205#define AMR_8LD_MAXTARG 15 206#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG) 207 208/* 209 * Adapter Info structure 210 */ 211struct amr_adapter_info 212{ 213 u_int8_t aa_maxio; 214 u_int8_t aa_rebuild_rate; 215 u_int8_t aa_maxtargchan; 216 u_int8_t aa_channels; 217 u_int8_t aa_firmware[4]; 218 u_int16_t aa_flashage; 219 u_int8_t aa_chipsetvalue; 220 u_int8_t aa_memorysize; 221 u_int8_t aa_cacheflush; 222 u_int8_t aa_bios[4]; 223 u_int8_t aa_boardtype; 224 u_int8_t aa_scsisensealert; 225 u_int8_t aa_writeconfigcount; 226 u_int8_t aa_driveinsertioncount; 227 u_int8_t aa_inserteddrive; 228 u_int8_t aa_batterystatus; 229 u_int8_t res1; 230} __packed; 231 232/* 233 * Logical Drive info structure 234 */ 235struct amr_logdrive_info 236{ 237 u_int8_t al_numdrives; 238 u_int8_t res1[3]; 239 u_int32_t al_size[AMR_8LD_MAXDRIVES]; 240 u_int8_t al_properties[AMR_8LD_MAXDRIVES]; 241 u_int8_t al_state[AMR_8LD_MAXDRIVES]; 242} __packed; 243 244/* 245 * Physical Drive info structure 246 */ 247struct amr_physdrive_info 248{ 249 u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */ 250 u_int8_t ap_predictivefailure; 251} __packed; 252 253/* 254 * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and 255 * AMR_CMD_EXT_ENQUIRY2. 256 * ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2 257 */ 258struct amr_enquiry 259{ 260 struct amr_adapter_info ae_adapter; /* X X X */ 261 struct amr_logdrive_info ae_ldrv; /* X X X */ 262 struct amr_physdrive_info ae_pdrv; /* X X X */ 263 u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */ 264 u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */ 265 u_int32_t ae_extlen; /* X */ 266 u_int16_t ae_subsystem; /* X */ 267 u_int16_t ae_subvendor; /* X */ 268 u_int32_t ae_signature; /* X */ 269#define AMR_SIG_431 0xfffe0001 270#define AMR_SIG_438 0xfffd0002 271#define AMR_SIG_762 0xfffc0003 272#define AMR_SIG_T5 0xfffb0004 273#define AMR_SIG_466 0xfffa0005 274#define AMR_SIG_467 0xfff90006 275#define AMR_SIG_T7 0xfff80007 276#define AMR_SIG_490 0xfff70008 277 u_int8_t res2[844]; /* X */ 278} __packed; 279 280 281/******************************************************************************** 282 ******************************************************************************** 283 40LD Firmware Interface 284 ******************************************************************************** 285 ********************************************************************************/ 286 287/* 288 * Array constraints 289 */ 290#define AMR_40LD_MAXDRIVES 40 291#define AMR_40LD_MAXCHAN 16 292#define AMR_40LD_MAXTARG 16 293#define AMR_40LD_MAXPHYSDRIVES 256 294 295/* 296 * Product Info structure 297 */ 298struct amr_prodinfo 299{ 300 u_int32_t ap_size; /* current size in bytes (not including resvd) */ 301 u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum 302 * logical drives, 0x20 maximum stripes and 0x08 303 * maximum spans */ 304 u_int8_t ap_firmware[16]; /* printable identifiers */ 305 u_int8_t ap_bios[16]; 306 u_int8_t ap_product[80]; 307 u_int8_t ap_maxio; /* maximum number of concurrent commands supported */ 308 u_int8_t ap_nschan; /* number of SCSI channels present */ 309 u_int8_t ap_fcloops; /* number of fibre loops present */ 310 u_int8_t ap_memtype; /* memory type */ 311 u_int32_t ap_signature; 312 u_int16_t ap_memsize; /* onboard memory in MB */ 313 u_int16_t ap_subsystem; /* subsystem identifier */ 314 u_int16_t ap_subvendor; /* subsystem vendor ID */ 315 u_int8_t ap_numnotifyctr; /* number of notify counters */ 316} __packed; 317 318/* 319 * Notify structure 320 */ 321struct amr_notify 322{ 323 u_int32_t an_globalcounter; /* change counter */ 324 325 u_int8_t an_paramcounter; /* parameter change counter */ 326 u_int8_t an_paramid; 327#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */ 328#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */ 329#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */ 330#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */ 331#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */ 332 u_int16_t an_paramval; 333 334 u_int8_t an_writeconfigcounter; /* write config occurred */ 335 u_int8_t res1[3]; 336 337 u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */ 338 u_int8_t an_ldrvopid; 339 u_int8_t an_ldrvopcmd; 340#define AMR_LDRVOP_CHECK 0x01 341#define AMR_LDRVOP_INIT 0x02 342#define AMR_LDRVOP_REBUILD 0x03 343 u_int8_t an_ldrvopstatus; 344#define AMR_LDRVOP_SUCCESS 0x00 345#define AMR_LDRVOP_FAILED 0x01 346#define AMR_LDRVOP_ABORTED 0x02 347#define AMR_LDRVOP_CORRECTED 0x03 348#define AMR_LDRVOP_STARTED 0x04 349 350 u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */ 351 u_int8_t an_ldrvstateid; 352 u_int8_t an_ldrvstatenew; 353 u_int8_t an_ldrvstateold; 354 355 u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */ 356 u_int8_t an_pdrvstateid; 357 u_int8_t an_pdrvstatenew; 358 u_int8_t an_pdrvstateold; 359 360 u_int8_t an_pdrvfmtcounter; 361 u_int8_t an_pdrvfmtid; 362 u_int8_t an_pdrvfmtval; 363#define AMR_FORMAT_START 0x01 364#define AMR_FORMAT_COMPLETE 0x02 365 u_int8_t res2; 366 367 u_int8_t an_targxfercounter; /* scsi xfer rate change */ 368 u_int8_t an_targxferid; 369 u_int8_t an_targxferval; 370 u_int8_t res3; 371 372 u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */ 373 u_int8_t an_fcloopidpdrvid; 374 u_int8_t an_fcloopid0; 375 u_int8_t an_fcloopid1; 376 377 u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */ 378 u_int8_t an_fcloopstate0; 379 u_int8_t an_fcloopstate1; 380 u_int8_t res4; 381} __packed; 382 383/* 384 * Enquiry3 structure 385 */ 386struct amr_enquiry3 387{ 388 u_int32_t ae_datasize; /* valid data size in this structure */ 389 union { /* event notify structure */ 390 struct amr_notify n; 391 u_int8_t pad[0x80]; 392 } ae_notify; 393 u_int8_t ae_rebuildrate; /* current rebuild rate in % */ 394 u_int8_t ae_cacheflush; /* flush interval in seconds */ 395 u_int8_t ae_sensealert; 396 u_int8_t ae_driveinsertcount; /* count of inserted drives */ 397 u_int8_t ae_batterystatus; 398 u_int8_t ae_numldrives; 399 u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */ 400 u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */ 401 u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */ 402 u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */ 403 u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* logical drive state */ 404 u_int8_t ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES]; /* physical drive state */ 405 u_int16_t ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES / 16]; 406 u_int8_t ae_targxfer[80]; /* physical drive transfer rates */ 407 408 u_int8_t res1[263]; /* pad to 1024 bytes */ 409} __packed; 410 411 412/******************************************************************************** 413 ******************************************************************************** 414 Mailbox and Command Structures 415 ******************************************************************************** 416 ********************************************************************************/ 417 418#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */ 419 420struct amr_mailbox 421{ 422 u_int8_t mb_command; 423 u_int8_t mb_ident; 424 u_int16_t mb_blkcount; /* u_int8_t opcode */ 425 /* u_int8_t subopcode */ 426 u_int32_t mb_lba; 427 u_int32_t mb_physaddr; 428 u_int8_t mb_drive; 429 u_int8_t mb_nsgelem; /* u_int8_t rserv[0] */ 430 u_int8_t res1; /* u_int8_t rserv[1] */ 431 u_int8_t mb_busy; /* u_int8_t rserv[2] */ 432 u_int8_t mb_nstatus; 433 u_int8_t mb_status; 434 u_int8_t mb_completed[46]; 435 u_int8_t mb_poll; 436 u_int8_t mb_ack; 437 u_int8_t res2[16]; 438} __packed; 439 440struct amr_mailbox64 441{ 442 u_int8_t pad[8]; /* Needed for alignment */ 443 u_int32_t sg64_lo; /* S/G pointer for 64-bit commands */ 444 u_int32_t sg64_hi; /* S/G pointer for 64-bit commands */ 445 struct amr_mailbox mb; 446} __packed; 447 448struct amr_mailbox_ioctl 449{ 450 u_int8_t mb_command; 451 u_int8_t mb_ident; 452 u_int8_t mb_channel; 453 u_int8_t mb_param; 454 u_int8_t mb_pad[4]; 455 u_int32_t mb_physaddr; 456 u_int8_t mb_drive; 457 u_int8_t mb_nsgelem; 458 u_int8_t res1; 459 u_int8_t mb_busy; 460 u_int8_t mb_nstatus; 461 u_int8_t mb_completed[46]; 462 u_int8_t mb_poll; 463 u_int8_t mb_ack; 464 u_int8_t res4[16]; 465} __packed; 466 467struct amr_sgentry 468{ 469 u_int32_t sg_addr; 470 u_int32_t sg_count; 471} __packed; 472 473struct amr_sg64entry 474{ 475 u_int64_t sg_addr; 476 u_int32_t sg_count; 477} __packed; 478 479struct amr_passthrough 480{ 481 u_int8_t ap_timeout:3; 482 u_int8_t ap_ars:1; 483 u_int8_t ap_dummy:3; 484 u_int8_t ap_islogical:1; 485 u_int8_t ap_logical_drive_no; 486 u_int8_t ap_channel; 487 u_int8_t ap_scsi_id; 488 u_int8_t ap_queue_tag; 489 u_int8_t ap_queue_action; 490 u_int8_t ap_cdb[AMR_MAX_CDB_LEN]; 491 u_int8_t ap_cdb_length; 492 u_int8_t ap_request_sense_length; 493 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 494 u_int8_t ap_no_sg_elements; 495 u_int8_t ap_scsi_status; 496 u_int32_t ap_data_transfer_address; 497 u_int32_t ap_data_transfer_length; 498} __packed; 499 500struct amr_ext_passthrough 501{ 502 u_int8_t ap_timeout:3; 503 u_int8_t ap_ars:1; 504 u_int8_t ap_rsvd1:1; 505 u_int8_t ap_cd_rom:1; 506 u_int8_t ap_rsvd2:1; 507 u_int8_t ap_islogical:1; 508 u_int8_t ap_logical_drive_no; 509 u_int8_t ap_channel; 510 u_int8_t ap_scsi_id; 511 u_int8_t ap_queue_tag; 512 u_int8_t ap_queue_action; 513 u_int8_t ap_cdb_length; 514 u_int8_t ap_rsvd3; 515 u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN]; 516 u_int8_t ap_no_sg_elements; 517 u_int8_t ap_scsi_status; 518 u_int8_t ap_request_sense_length; 519 u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN]; 520 u_int8_t ap_rsvd4; 521 u_int32_t ap_data_transfer_address; 522 u_int32_t ap_data_transfer_length; 523} __packed; 524 525struct amr_linux_ioctl { 526 u_int32_t inlen; 527 u_int32_t outlen; 528 union { 529 u_int8_t fca[16]; 530 struct { 531 u_int8_t opcode; 532 u_int8_t subopcode; 533 u_int16_t adapno; 534 u_int32_t buffer; 535 u_int8_t pad[4]; 536 u_int32_t length; 537 } __packed fcs; 538 } __packed ui; 539 u_int8_t mbox[18]; 540 struct amr_passthrough pthru; 541 u_int32_t data; 542 u_int8_t pad[4]; 543} __packed; 544 545#ifdef _KERNEL 546/******************************************************************************** 547 ******************************************************************************** 548 "Quartz" i960 PCI bridge interface 549 ******************************************************************************** 550 ********************************************************************************/ 551 552#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */ 553#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */ 554#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */ 555 556/* 557 * Doorbell registers 558 */ 559#define AMR_QIDB 0x20 560#define AMR_QODB 0x2c 561#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */ 562#define AMR_QIDB_ACK 0x00000002 /* mailbox done */ 563#define AMR_QODB_READY 0x10001234 /* work ready to be processed */ 564 565/* 566 * Initialisation status 567 */ 568#define AMR_QINIT_SCAN 0x01 /* init scanning drives */ 569#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */ 570#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */ 571#define AMR_QINIT_INPROG 0xdc /* init in progress */ 572#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */ 573#define AMR_QINIT_NOMEM 0xac /* insufficient memory */ 574#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */ 575#define AMR_QINIT_DONE 0x9c /* init successfully done */ 576 577/* 578 * I/O primitives 579 */ 580#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val) 581#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB) 582#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val) 583#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB) 584 585#ifdef AMR_BOARD_INIT 586#define AMR_QRESET(sc) \ 587 do { \ 588 pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \ 589 pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \ 590 } while (0) 591#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1) 592#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1) 593#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1) 594#endif 595 596/******************************************************************************** 597 ******************************************************************************** 598 "Standard" old-style ASIC bridge interface 599 ******************************************************************************** 600 ********************************************************************************/ 601 602/* 603 * I/O registers 604 */ 605#define AMR_SCMD 0x10 /* command/ack register (write) */ 606#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */ 607#define AMR_STOGGLE 0x11 /* interrupt enable bit here */ 608#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */ 609#define AMR_SMBOX_1 0x15 610#define AMR_SMBOX_2 0x16 611#define AMR_SMBOX_3 0x17 /* high byte */ 612#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */ 613#define AMR_SINTR 0x1a /* interrupt status */ 614 615/* 616 * I/O magic numbers 617 */ 618#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */ 619#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */ 620#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */ 621#define AMR_SINTR_VALID 0x40 /* in SINTR */ 622#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */ 623#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */ 624 625/* 626 * Initialisation status 627 */ 628#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */ 629#define AMR_SINIT_NOMEM 0xca /* insufficient memory */ 630#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */ 631#define AMR_SINIT_INPROG 0x11 /* init in progress */ 632#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */ 633#define AMR_SINIT_DONE 0x99 /* init successfully done */ 634 635/* 636 * I/O primitives 637 */ 638#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val) 639#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR) 640#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR) 641#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST) 642#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY) 643#define AMR_SENABLE_INTR(sc) \ 644 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 645 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE) 646#define AMR_SDISABLE_INTR(sc) \ 647 bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \ 648 bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE) 649#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val) 650 651#ifdef AMR_BOARD_INIT 652#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80) 653#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE) 654#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1) 655#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2) 656#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3) 657#endif 658 659#endif /* _KERNEL */ 660